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| ? mips technologies, inc. 1996 printed in japan document no. u12739ej2v0um00 (2nd edition) date published january 1998 n cp(k) v r 4102? 64/32-bit microprocessor preliminary users manual 1997 p p p p pd30102
2 [memo] 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. v r 3000, v r 4000, v r 4100, v r 4101, v r 4102, v r 4200, v r 4400, and v r series are trademarks of nec corporation. mips is a trademark of mips technologies, inc. iapx is a trademark of intel corp. dec vax is a trademark of digital equipment corp. unix is a registered trademark in the united states and other countries, licensed exclusively through x/open company, ltd. 4 the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96. 5 exporting this product or equipment that include this product may require a governmental license from the u.s.a. for some countries because this product utilizes technologies limited by the export control regulations of the u.s.a. 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 j97. 8 6 [memo] 7 preface readers this manual targets users who intends to understand the functions of the v r 4102 and to design application systems using this microprocessor. purpose this manual introduces the architecture and hardware functions of the v r 4102 to users, following the organization described below. organization this manual consists of the following contents: ? introduction ? pipeline operation ? cache organization and memory management system ? exception processing ? initialization interface ? interrupts ? peripheral units ? instruction set details how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electric engineering, logic circuits, and microcomputers. the v r 4000 tm in this manual includes the v r 4400 tm . to learn in detail about the function of a specific instruction, o read chapter 3 cpu instruction set summary and chapter 27 cpu instruction set details . to learn about the overall functions of the v r 4102, o read this manual in sequential order. to learn about electrical specifications, o refer to data sheet which is separately available. legend data significance: higher on left and lower on right active low: xxx# (trailing # after pin and signal names) numeric representation: binary/decimal ... xxxx hexadecimal ... 0xxxxx prefixes representing an exponent of 2 (for address space or memory capacity): k (kilo) 2 10 = 1024 m (mega) 2 20 = 1024 2 g (giga) 2 30 = 1024 3 t (tera) 2 40 = 1024 4 p (peta) 2 50 = 1024 5 e (exa) 2 60 = 1024 6 8 related documents the related documents indicated here may include preliminary version. however, preliminary versions are not marked as such. ? users manual v r 4102 users manual this manual v r 4100 tm users manual u10050e ? data sheet v r 4102 data sheet u12543e ? application note v r 4102 application note to be prepared v r series? application note programming guide u10710j note note this document number is that of the japanese version. 9 contents chapter 1 introduction ...................................................................................................... ........ 29 1.1 features.................................................................................................................... .......... 29 1.2 ordering information .................................................................................................. 30 1.3 64-bit architecture........................................................................................................ 30 1.4 v r 4102 processor ............................................................................................................ 30 1.4.1 internal block structure................................................................................................ ............. 31 1.4.2 i/o registers ........................................................................................................... .................... 33 1.5 v r 4100 cpu core ............................................................................................................... 4 3 1.5.1 v r 4100 cpu core .................................................................................................................. ..... 43 1.5.2 cpu registers ........................................................................................................... ................. 45 1.5.3 cpu instruction set overview............................................................................................ ....... 46 1.5.4 data formats and addressing ............................................................................................. ..... 47 1.5.5 coprocessors (cp0-cp3).................................................................................................. ......... 49 1.5.6 floating-point unit (fpu)............................................................................................... ............ 51 1.5.7 cache ................................................................................................................... ....................... 51 1.6 cpu core memory management system (mmu)................................................. 52 1.6.1 translation lookaside buffer (tlb) ...................................................................................... ... 52 1.6.2 operating modes ......................................................................................................... ............... 52 1.7 instruction pipeline ...................................................................................................... 5 3 1.8 clock interface............................................................................................................ .. 53 chapter 2 pin functions.................................................................................................... ......... 57 2.1 pin configuration.......................................................................................................... .57 2.2 pin function description............................................................................................ 62 2.2.1 system bus interface signals ............................................................................................ ....... 63 2.2.2 clock interface signals................................................................................................. ............. 65 2.2.3 battery monitor interface signals ....................................................................................... ...... 65 2.2.4 initialization interface signals........................................................................................ ........... 66 2.2.5 rs-232-c interface signals.............................................................................................. .......... 67 2.2.6 irda interface signals .................................................................................................. .............. 68 2.2.7 debug serial interface signals.......................................................................................... ........ 68 2.2.8 keyboard interface signals .............................................................................................. ......... 69 2.2.9 audio interface signals ................................................................................................. ............ 69 2.2.10 touch panel/general purpose a/d interface signals ........................................................... 69 2.2.11 general-purpose i/o signals ............................................................................................ ....... 70 2.2.12 hsp modem interface signals ............................................................................................ ... 71 2.2.13 led interface signal ................................................................................................... ............. 71 2.2.14 dedicated v dd and gnd signals ............................................................................................. 72 2.3 pin status upon specific states ........................................................................... 73 2.3.1 pin status upon reset ................................................................................................... ............ 73 2.3.2 connection of unused pins and pin i/o circuits .................................................................... 76 2.3.3 pin i/o circuits ........................................................................................................ ................... 79 10 chapter 3 cpu instruction set summary .......................................................................... 81 3.1 cpu instruction formats ........................................................................................... 81 3.2 instruction classes...................................................................................................... 82 3.2.1 load and store instructions............................................................................................. ......... 82 3.2.2 computational instructions.............................................................................................. ......... 86 3.2.3 jump and branch instructions............................................................................................ ...... 92 3.2.4 special instructions .................................................................................................... ............... 96 3.2.5 system control coprocessor (cp0) instructions .................................................................... 97 chapter 4 v r 4102 pipeline ........................................................................................................... 99 4.1 pipeline stages ............................................................................................................ .... 99 4.1.1 pipeline activities..................................................................................................... .................. 100 4.2 branch delay............................................................................................................... ..... 102 4.3 load delay ................................................................................................................. ........ 102 4.4 pipeline operation......................................................................................................... . 102 4.5 interlock and exception handling....................................................................... 109 4.5.1 exception conditions.................................................................................................... ............. 112 4.5.2 stall conditions ........................................................................................................ .................. 113 4.5.3 slip conditions ......................................................................................................... .................. 114 4.5.4 bypassing ............................................................................................................... .................... 115 4.6 code compatibility ......................................................................................................... 115 chapter 5 memory management system............................................................................. 117 5.1 translation lookaside buffer (tlb) .................................................................... 117 5.2 virtual address space................................................................................................ 117 5.2.1 virtual-to-physical address translation ................................................................................. . 118 5.2.2 32-bit mode address translation......................................................................................... ..... 119 5.2.3 64-bit mode address translation......................................................................................... ..... 120 5.2.4 operating modes ......................................................................................................... ............... 121 5.2.5 user mode virtual addressing ............................................................................................ ...... 121 5.2.6 supervisor-mode virtual addressing ...................................................................................... . 124 5.2.7 kernel-mode virtual addressing.......................................................................................... ..... 127 5.3 physical address space ............................................................................................. 135 5.3.1 rom space............................................................................................................... ................... 137 5.3.2 system bus space ........................................................................................................ ............. 138 5.3.3 internal i/o space ...................................................................................................... ................. 139 5.3.4 lcd space ............................................................................................................... ................... 140 5.3.5 dram space .............................................................................................................. ................. 140 5.4 system control coprocessor ................................................................................ 141 5.4.1 format of a tlb entry................................................................................................... ............. 142 5.5 cp0 registers.............................................................................................................. ...... 146 5.5.1 index register (0) ...................................................................................................... ................. 146 5.5.2 random register (1) ..................................................................................................... ............. 146 5.5.3 entryhi (10), entrylo0 (2), entrylo1 (3), and pagemask (5) registers.................................. 147 5.5.4 wired register (6)...................................................................................................... ................. 148 11 5.5.5 processor revision identifier (prid) register (15) ................................................................. 149 5.5.6 config register (16) .................................................................................................... ............... 150 5.5.7 load linked address (lladdr) register (17).......................................................................... 151 5.5.8 cache tag registers (taglo (28) and taghi (29)) .................................................................. 152 5.5.9 virtual-to-physical address translation ................................................................................. . 153 5.5.10 tlb misses ............................................................................................................. .................. 155 5.5.11 tlb instructions....................................................................................................... ................ 155 chapter 6 exception processing........................................................................................... 15 7 6.1 how exception processing works........................................................................ 157 6.2 precision of exceptions ............................................................................................. 158 6.3 exception processing registers ........................................................................... 159 6.3.1 context register (4) .................................................................................................... ............... 160 6.3.2 badvaddr register (8) ................................................................................................... ............ 161 6.3.3 count register (9) ...................................................................................................... ................ 161 6.3.4 compare register (11) ................................................................................................... ............ 162 6.3.5 status register (12) .................................................................................................... ............... 162 6.3.6 cause register (13)..................................................................................................... ............... 165 6.3.7 exception program counter (epc) register (14) .................................................................... 167 6.3.8 watchlo (18) and watchhi (19) registers ............................................................................... 16 8 6.3.9 xcontext register (20).................................................................................................. ............. 169 6.3.10 parity error register (26)............................................................................................. ............ 170 6.3.11 cache error register (27) .............................................................................................. .......... 171 6.3.12 errorepc register (30) ................................................................................................. ........... 171 6.4 details of exceptions ................................................................................................. 173 6.4.1 exception types......................................................................................................... ................ 173 6.4.2 exception vector locations .............................................................................................. ........ 173 6.4.3 priority of exceptions .................................................................................................. .............. 176 6.4.4 cold reset exception .................................................................................................... ............ 177 6.4.5 soft reset exception .................................................................................................... ............. 178 6.4.6 nmi exception ........................................................................................................... ................. 179 6.4.7 address error exception ................................................................................................. .......... 180 6.4.8 tlb exceptions .......................................................................................................... ................ 181 6.4.9 cache error exception................................................................................................... ............ 184 6.4.10 bus error exception.................................................................................................... ............. 185 6.4.11 system call exception.................................................................................................. ........... 186 6.4.12 breakpoint exception ................................................................................................... ........... 186 6.4.13 coprocessor unusable exception......................................................................................... . 187 6.4.14 reserved instruction exception ......................................................................................... .... 188 6.4.15 trap exception ......................................................................................................... ................ 188 6.4.16 integer overflow exception............................................................................................. ........ 189 6.4.17 watch exception ........................................................................................................ .............. 189 6.4.18 interrupt exception .................................................................................................... .............. 190 6.5 exception processing and servicing flowcharts ....................................... 191 12 chapter 7 initialization interface ........................................................................................ 1 99 7.1 reset function............................................................................................................. .... 199 7.1.1 rtc reset ............................................................................................................... .................... 199 7.1.2 rstsw ................................................................................................................... ..................... 201 7.1.3 deadmans switch........................................................................................................ .............. 202 7.1.4 software shutdown ....................................................................................................... ............. 203 7.1.5 haltimer shutdown ....................................................................................................... ........... 204 7.2 poweron sequence ........................................................................................................ 205 7.3 reset of the cpu core ............................................................................................... 207 7.3.1 cold reset.............................................................................................................. ..................... 207 7.3.2 soft reset.............................................................................................................. ...................... 208 7.4 v r 4102 processor modes ............................................................................................. 210 7.4.1 power modes ............................................................................................................. ................. 210 7.4.2 privilege mode .......................................................................................................... .................. 211 7.4.3 reverse endian .......................................................................................................... ................ 211 7.4.4 bootstrap exception vector (bev) ........................................................................................ ... 211 7.4.5 cache error check ....................................................................................................... .............. 212 7.4.6 parity error prohibit ................................................................................................... ................ 212 7.4.7 interrupt enable (ie) ................................................................................................... ................ 212 chapter 8 cache memory ..................................................................................................... ...... 213 8.1 memory organization ................................................................................................... 213 8.2 cache organization....................................................................................................... 21 4 8.2.1 organization of the instruction cache (i-cache) ..................................................................... 214 8.2.2 organization of the data cache (d-cache) .............................................................................. 21 5 8.2.3 accessing the caches .................................................................................................... ........... 216 8.3 cache operations........................................................................................................... 217 8.3.1 cache write policy ...................................................................................................... ............... 217 8.4 cache states ............................................................................................................... ..... 218 8.5 cache state transition diagrams ......................................................................... 219 8.5.1 data cache state transition............................................................................................. ......... 219 8.5.2 instruction cache state transition ...................................................................................... ..... 219 8.6 cache data integrity ................................................................................................... 220 8.7 manipulation of the caches by an external agent .................................. 230 chapter 9 cpu core interrupts............................................................................................. 231 9.1 non-maskable interrupt (nmi) .................................................................................. 231 9.2 ordinary interrupts ..................................................................................................... 231 9.3 software interrupts generated in cpu core ............................................... 232 9.4 timer interrupt............................................................................................................ .... 232 9.5 asserting interrupts ................................................................................................... 232 9.5.1 detecting hardware interrupts ........................................................................................... ....... 232 9.5.2 masking interrupt signals............................................................................................... ........... 234 13 chapter 10 bcu (bus control unit) ..................................................................................... 235 10.1 general.................................................................................................................... ............ 235 10.2 register set.............................................................................................................. ........ 235 10.2.1 bcucntreg 1 (0x0b00 0000) .............................................................................................. .. 236 10.2.2 bcucntreg 2 (0x0b00 0002) .............................................................................................. .. 238 10.2.3 bcuspeedreg (0x0b00 000a) .............................................................................................. 239 10.2.4 bcuerrstreg (0x0b00 000c) .............................................................................................. 241 10.2.5 bcurfcntreg (0x0b00 000e) .............................................................................................. 242 10.2.6 revidreg (0x0b00 0010)................................................................................................. ....... 243 10.2.7 bcurfcountreg (0x0b00 0012) ......................................................................................... 244 10.2.8 clkspeedreg (0x0b00 0014) .............................................................................................. . 245 10.3 connection of address pins.................................................................................... 246 10.4 notes on using bcu ...................................................................................................... 247 10.4.1 cpu core bus modes ..................................................................................................... ......... 247 10.4.2 access data size....................................................................................................... ............... 247 10.4.3 rom interface .......................................................................................................... ................. 248 10.4.4 flash memory interface ................................................................................................. .......... 249 10.4.5 lcd control interface .................................................................................................. ............ 250 10.4.6 illegal access notification............................................................................................ ........... 251 10.5 bus operations............................................................................................................ .... 252 10.5.1 rom access ............................................................................................................. ................ 252 10.5.2 system bus access ...................................................................................................... ........... 256 10.5.3 lcd interface.......................................................................................................... .................. 263 10.5.4 dram access (edo type) ................................................................................................. ..... 264 10.5.5 refresh................................................................................................................ ...................... 267 10.5.6 bus hold ............................................................................................................... .................... 268 chapter 11 dmaau (dma address unit)................................................................................ 271 11.1 general.................................................................................................................... ............ 271 11.2 register set.............................................................................................................. ........ 272 11.2.1 aiu in dma base address registers ..................................................................................... 2 73 11.2.2 aiu in dma address registers........................................................................................... .... 275 11.2.3 aiu out dma base address registers ................................................................................. 276 11.2.4 aiu out dma address registers.......................................................................................... . 278 11.2.5 fir dma base address registers ......................................................................................... . 279 11.2.6 fir dma address registers.............................................................................................. ...... 280 chapter 12 dcu (dma control unit) ..................................................................................... 281 12.1 general.................................................................................................................... ............ 281 12.2 dma priority control .................................................................................................. 281 12.3 register set.............................................................................................................. ........ 281 12.3.1 dmarstreg (0x0b00 0040) ................................................................................................ ... 282 12.3.2 dmaidlereg (0x0b00 0042) ............................................................................................... ... 283 12.3.3 dmasenreg (0x0b00 0044) ................................................................................................ ... 284 12.3.4 dmamskreg (0x0b00 0046) ................................................................................................ .. 285 14 12.3.5 dmareqreg (0x0b00 0048) ................................................................................................ ... 286 12.3.6 tdreg (0x0b00 004a) .................................................................................................... ......... 287 chapter 13 cmu (clock mask unit) ....................................................................................... 28 9 13.1 general.................................................................................................................... ............ 289 13.2 register set .............................................................................................................. ........ 289 13.2.1 cmuclkmsk (0x0b00 0060) ................................................................................................ ... 290 chapter 14 icu (interrupt control unit) .......................................................................... 291 14.1 general.................................................................................................................... ............ 291 14.2 register set .............................................................................................................. ........ 294 14.2.1 sysint1reg (0x0b00 0080)............................................................................................... ..... 295 14.2.2 piuintreg (0x0b00 0082) ................................................................................................ ....... 297 14.2.3 aiuintreg (0x0b00 0084)................................................................................................ ....... 298 14.2.4 kiuintreg (0x0b00 0086)................................................................................................ ....... 299 14.2.5 giuintlreg (0x0b00 0088) ............................................................................................... ..... 300 14.2.6 dsiuintreg (0x0b00 008a)............................................................................................... ..... 301 14.2.7 msysint1reg (0x0b00 008c) .............................................................................................. .. 302 14.2.8 mpiuintreg (0x0b00 008e)............................................................................................... ..... 304 14.2.9 maiuintreg (0x0b00 0090)............................................................................................... ..... 305 14.2.10 mkiuintreg (0x0b00 0092).............................................................................................. .... 306 14.2.11 mgiuintlreg (0x0b00 0094) ............................................................................................. .. 307 14.2.12 mdsiuintreg (0x0b00 0096) ............................................................................................. .. 308 14.2.13 nmireg (0x0b00 0098) .................................................................................................. ........ 309 14.2.14 softintreg (0x0b00 009a).............................................................................................. ... 310 14.2.15 sysint2reg (0x0b00 0200).............................................................................................. .... 311 14.2.16 giuinthreg (0x0b00 0202) .............................................................................................. .... 312 14.2.17 firintreg (0x0b00 0204) ............................................................................................... ...... 313 14.2.18 msysint2reg (0x0b00 0206)............................................................................................. .. 314 14.2.19 mgiuinthreg (0x0b00 0208) ............................................................................................. .. 315 14.2.20 mfirintreg (0x0b00 020a).............................................................................................. .... 316 14.3 notes for register setting ..................................................................................... 317 chapter 15 pmu (power management unit) ....................................................................... 319 15.1 general.................................................................................................................... ............ 319 15.1.1 reset control .......................................................................................................... .................. 319 15.1.2 shutdown control ....................................................................................................... ............. 320 15.1.3 power-on control ....................................................................................................... .............. 321 15.1.4 power mode ............................................................................................................. ................. 324 15.2 register set .............................................................................................................. ........ 327 15.2.1 pmuintreg (0x0b00 00a0) ................................................................................................ .... 328 15.2.2 pmucntreg (0x0b00 00a2) ................................................................................................ ... 330 15.2.3 pmuint2reg (0x0b00 00a4) ............................................................................................... ... 332 15.2.4 pmucnt2reg (0x0b00 00a6) ............................................................................................... .. 333 15 chapter 16 rtc (realtime clock unit) ................................................................................ 335 16.1 general.................................................................................................................... ............ 335 16.2 register set.............................................................................................................. ........ 336 16.2.1 elapsed time registers................................................................................................. .......... 337 16.2.2 elapsed time compare registers ......................................................................................... . 339 16.2.3 rtc long 1 registers................................................................................................... ........... 341 16.2.4 rtc long 1 count registers ............................................................................................. ..... 343 16.2.5 rtc long 2 registers................................................................................................... ........... 345 16.2.6 rtc long 2 count registers ............................................................................................. ..... 347 16.2.7 tclock counter registers ............................................................................................... ........ 349 16.2.8 tclock counter count registers......................................................................................... ... 351 16.2.9 rtc interrupt register................................................................................................. ............ 353 chapter 17 dsu (deadmans switch unit) ........................................................................... 355 17.1 general.................................................................................................................... ............ 355 17.2 register set.............................................................................................................. ........ 355 17.2.1 dsucntreg (0x0b00 00e0) ................................................................................................ ... 356 17.2.2 dsusetreg (0x0b00 00e2)................................................................................................ .... 357 17.2.3 dsuclrreg (0x0b00 00e4) ............................................................................................... ... 358 17.2.4 dsutimreg (0x0b00 00e6) ................................................................................................ .... 359 17.3 register setting flow ................................................................................................ 360 chapter 18 giu (general purpose i/o unit) ...................................................................... 361 18.1 general.................................................................................................................... ............ 361 18.2 register set.............................................................................................................. ........ 362 18.2.1 giuiosell (0x0b00 0100) ................................................................................................ ....... 363 18.2.2 giuioselh (0x0b00 0102)................................................................................................ ....... 364 18.2.3 giupiodl (0x0b00 0104) ................................................................................................. ........ 365 18.2.4 giupiodh (0x0b00 0106)................................................................................................. ........ 366 18.2.5 giuintstatl (0x0b00 0108).............................................................................................. ..... 367 18.2.6 giuintstath (0x0b00 010a).............................................................................................. .... 368 18.2.7 giuintenl (0x0b00 010c) ................................................................................................ ...... 369 18.2.8 giuintenh (0x0b00 010e) ................................................................................................ ...... 370 18.2.9 giuinttypl (0x0b00 0110) ............................................................................................... ...... 371 18.2.10 giuinttyph (0x0b00 0112).............................................................................................. ..... 372 18.2.11 giuintalsell (0x0b00 0114) ............................................................................................ .. 373 18.2.12 giuintalselh (0x0b00 0116)............................................................................................ .. 374 18.2.13 giuinthtsell (0x0b00 0118) ............................................................................................ .. 375 18.2.14 giuinthtselh (0x0b00 011a) ............................................................................................ . 376 18.2.15 giupodatl (0x0b00 011c)............................................................................................... .... 378 18.2.16 giupodath (0x0b00 011e) ............................................................................................... ... 380 16 chapter 19 piu (touch panel interface unit) ................................................................. 381 19.1 general.................................................................................................................... ............ 381 19.1.1 block diagrams ......................................................................................................... ............... 382 19.2 scan sequencer state transition ........................................................................ 384 19.3 register set .............................................................................................................. ........ 386 19.3.1 piucntreg (0x0b00 0122) ................................................................................................ ..... 387 19.3.2 piuintreg (0x0b00 0124) ................................................................................................ ....... 390 19.3.3 piusivlreg (0x0b00 0126)............................................................................................... ...... 391 19.3.4 piustblreg (0x0b00 0128) ............................................................................................... .... 392 19.3.5 piucmdreg (0x0b00 012a) ................................................................................................ .... 393 19.3.6 piuascnreg (0x0b00 0130)............................................................................................... .... 395 19.3.7 piuamskreg (0x0b00 0132) ............................................................................................... ... 397 19.3.8 piucivlreg (0x0b00 013e) ............................................................................................... ..... 398 19.3.9 piupbnmreg (0x0b00 02a0 to 0x0b00 02ae, 0x0b00 02bc to 0x0b00 02be) ................. 399 19.3.10 piuabnreg (0x0b00 02b0 to 0x0b00 02b6) ....................................................................... 400 19.4 register setting flow................................................................................................. 401 19.5 relationships among tpx, tpy, and adin pins and states ....................... 403 19.6 timing..................................................................................................................... ................ 404 19.6.1 touch/release detection timing ......................................................................................... ... 404 19.6.2 a/d port scan timing................................................................................................... ............ 404 19.7 data loss interrupt conditions ............................................................................ 405 19.8 comparison of VR4102 and vr4101 tm ....................................................................... 407 chapter 20 aiu (audio interface unit)................................................................................. 409 20.1 general.................................................................................................................... ............ 409 20.2 register set .............................................................................................................. ........ 409 20.2.1 mdmadatreg (0x0b00 0160) ............................................................................................... . 410 20.2.2 sdmadatreg (0x0b00 0162) ............................................................................................... .. 411 20.2.3 sodatreg (0x0b00 0166) ................................................................................................. ..... 412 20.2.4 scntreg (0x0b00 0168) .................................................................................................. ....... 413 20.2.5 scnvrreg (0x0b00 016a)................................................................................................. ..... 414 20.2.6 midatreg (0x0b00 0170) ................................................................................................. ...... 415 20.2.7 mcntreg (0x0b00 0172) .................................................................................................. ...... 416 20.2.8 mcnvrreg (0x0b00 0174)................................................................................................. ..... 417 20.2.9 dvalidreg (0x0b00 0178)................................................................................................ ...... 418 20.2.10 seqreg (0x0b00 017a).................................................................................................. ....... 419 20.2.11 intreg (0x0b00 017c) .................................................................................................. ........ 420 20.3 operation sequence ...................................................................................................... 421 20.3.1 output (speaker) ....................................................................................................... ............... 421 20.3.2 input (mic)............................................................................................................ ..................... 422 chapter 21 kiu (keyboard interface unit)........................................................................ 423 21.1 general.................................................................................................................... ............ 423 21.2 register set .............................................................................................................. ........ 423 21.2.1 kiudatn (0x0b00 0180 to 0x0b00 018a) ............................................................................... 424 17 21.2.2 kiuscanrep (0x0b00 0190)............................................................................................... .... 425 21.2.3 kiuscans (0x0b00 0192)................................................................................................. ....... 427 21.2.4 kiuwks (0x0b00 0194)................................................................................................... ......... 429 21.2.5 kiuwki (0x0b00 0196) ................................................................................................... .......... 430 21.2.6 kiuint (0x0b00 0198) ................................................................................................... ........... 431 21.2.7 kiurst (0x0b00 019a) ................................................................................................... ......... 432 21.2.8 kiugpen (0x0b00 019c) .................................................................................................. ....... 433 21.2.9 scanline (0x0b00 019e)................................................................................................. ....... 434 chapter 22 dsiu (debug serial interface unit) ............................................................. 435 22.1 general.................................................................................................................... ............ 435 22.2 register set.............................................................................................................. ........ 435 22.2.1 portreg (0x0b00 01a0) .................................................................................................. ...... 436 22.2.2 modemreg (0x0b00 01a2) ................................................................................................. ... 437 22.2.3 asim00reg (0x0b00 01a4) ................................................................................................ ..... 438 22.2.4 asim01reg (0x0b00 01a6) ................................................................................................ ..... 439 22.2.5 rxb0rreg (0x0b00 01a8)................................................................................................. ..... 440 22.2.6 rxb0lreg (0x0b00 01aa)................................................................................................. ..... 441 22.2.7 txs0rreg (0x0b00 01ac)................................................................................................. ..... 442 22.2.8 txs0lreg (0x0b00 01ae) ................................................................................................. ..... 443 22.2.9 asis0reg (0x0b00 01b0)................................................................................................. ....... 444 22.2.10 intr0reg (0x0b00 01b2)................................................................................................ ...... 445 22.2.11 bprm0reg (0x0b00 01b6) ................................................................................................ ... 446 22.2.12 dsiuresetreg (0x0b00 01b8) ........................................................................................... 4 47 22.3 description of operations........................................................................................ 448 22.3.1 data format ............................................................................................................ .................. 448 22.3.2 transmission........................................................................................................... ................. 449 22.3.3 reception.............................................................................................................. .................... 451 chapter 23 led (led control unit) ...................................................................................... 45 3 23.1 general.................................................................................................................... ............ 453 23.2 register set.............................................................................................................. ........ 453 23.2.1 ledhtsreg (0x0b00 0240) ................................................................................................ .... 454 23.2.2 ledltsreg (0x0b00 0242)................................................................................................ ..... 455 23.2.3 ledcntreg (0x0b00 0248) ................................................................................................ .... 456 23.2.4 ledastcreg (0x0b00 024a) ............................................................................................... .. 457 23.2.5 ledintreg (0x0b00 024c) ................................................................................................ ..... 458 23.3 operation flow ............................................................................................................ ... 459 chapter 24 siu (serial interface unit) ............................................................................... 461 24.1 general.................................................................................................................... ............ 461 24.2 register set.............................................................................................................. ........ 461 24.2.1 siurb (0x0c00 0000: lcr[7] = 0, read) ................................................................................ 46 2 24.2.2 siuth (0x0c00 0000: lcr[7] = 0, write)................................................................................. 462 24.2.3 siudll (0x0c00 0000: lcr[7] = 1) ....................................................................................... .. 463 18 24.2.4 siuie (0x0c00 0001: lcr[7] = 0) ........................................................................................ ..... 464 24.2.5 siudlm (0x0c00 0001: lcr[7] = 1)....................................................................................... .. 465 24.2.6 siuiid (0x0c00 0002: read) ............................................................................................. ........ 467 24.2.7 siufc (0x0c00 0002: write)............................................................................................. ........ 469 24.2.8 siulc (0x0c00 0003).................................................................................................... ............ 472 24.2.9 siumc (0x0c00 0004) .................................................................................................... ........... 473 24.2.10 siuls (0x0c00 0005) ................................................................................................... ........... 474 24.2.11 siums (0x0c00 0006) ................................................................................................... .......... 476 24.2.12 siusc (0x0c00 0007)................................................................................................... ........... 477 24.2.13 siuirsel (0x0c00 0008) ................................................................................................ ........ 478 chapter 25 hsp (modem interface unit) ............................................................................. 481 25.1 general.................................................................................................................... ............ 481 25.2 register set .............................................................................................................. ........ 483 25.2.1 hsp initialize register................................................................................................ .............. 484 25.2.2 hsp data register, hsp index register ................................................................................. 4 85 25.2.3 hsp id register, hsp i/o address program confirmation register ................................... 493 25.2.4 hsp signature checking port ............................................................................................ ..... 493 25.3 power control ............................................................................................................. ... 494 chapter 26 fir (fast irda interface unit).......................................................................... 497 26.1 general.................................................................................................................... ............ 497 26.2 register set .............................................................................................................. ........ 498 26.2.1 frstr (0x0c00 0040).................................................................................................... ........... 499 26.2.2 dpintr (0x0c00 0042) ................................................................................................... .......... 500 26.2.3 dpcntr (0x0c00 0044)................................................................................................... ......... 501 26.2.4 tdr (0x0c00 0050) ...................................................................................................... ............. 502 26.2.5 rdr (0x0c00 0052)...................................................................................................... ............. 503 26.2.6 imr (0x0c00 0054) ...................................................................................................... .............. 504 26.2.7 fsr (0x0c00 0056) ...................................................................................................... ............. 505 26.2.8 irsr1 (0x0c00 0058) .................................................................................................... ............ 507 26.2.9 crcsr (0x0c00 005c) .................................................................................................... ......... 508 26.2.10 fircr (0x0c00 005e) ................................................................................................... .......... 509 26.2.11 mircr (0x0c00 0060)................................................................................................... .......... 511 26.2.12 dmacr (0x0c00 0062) ................................................................................................... ........ 512 26.2.13 dmaer (0x0c00 0064) ................................................................................................... ........ 513 26.2.14 txir (0x0c00 0066) .................................................................................................... ............ 514 26.2.15 rxir (0x0c00 0068) .................................................................................................... ............ 515 26.2.16 ifr (0x0c00 006a) ..................................................................................................... ............. 517 26.2.17 rxsts (0x0c00 006c) ................................................................................................... ......... 519 26.2.18 txfl (0x0c00 006e) .................................................................................................... ........... 521 26.2.19 mrxf (0x0c00 0070) .................................................................................................... .......... 522 26.2.20 rxfl (0x0c00 0074) .................................................................................................... ........... 523 19 chapter 27 cpu instruction set details ........................................................................... 525 27.1 instruction notation conventions ....................................................................... 525 27.2 load and store instructions.................................................................................. 527 27.3 jump and branch instructions............................................................................... 528 27.4 system control coprocessor (cp0) instructions ....................................... 528 27.5 cpu instruction........................................................................................................... .... 529 27.6 cpu instruction opcode bit encoding ................................................................ 674 chapter 28 v r 4102 coprocessor 0 hazards ..................................................................... 677 chapter 29 pll passive components ................................................................................... 683 appendix a differences between v r 4102 and v r 4101 .................................................... 685 a.1 summary of differences ............................................................................................ 685 a.2 details of differences ............................................................................................... 686 a.2.1 cpu core ................................................................................................................ .................... 686 a.2.2 address mapping......................................................................................................... .............. 686 a.2.3 bcu..................................................................................................................... ........................ 687 a.2.4 dma ..................................................................................................................... ....................... 688 a.2.5 icu ..................................................................................................................... ......................... 688 a.2.6 pmu..................................................................................................................... ........................ 688 a.2.7 rtc ..................................................................................................................... ........................ 688 a.2.8 giu ..................................................................................................................... ......................... 689 a.2.9 piu..................................................................................................................... .......................... 690 a.2.10 aiu .................................................................................................................... ........................ 691 a.2.11 kiu .................................................................................................................... ........................ 691 a.2.12 dsiu ................................................................................................................... ....................... 692 a.2.13 siu.................................................................................................................... ......................... 692 a.2.14 newly added units ...................................................................................................... ............ 693 appendix b index ............................................................................................................ ................. 695 20 list of figures (1/4) fig. no. title page 1-1 v r 4102 internal block diagram and example of connection to external blocks................................... 30 1-2 v r 4100 cpu core internal block diagram ........................................................................................... .43 1-3 v r 4102 cpu registers ............................................................................................................. ............. 45 1-4 cpu instruction formats..................................................................................................... ................... 46 1-5 little-endian byte ordering in word data.................................................................................... .......... 47 1-6 little-endian byte ordering in double word data ............................................................................. .... 48 1-7 misaligned word accessing (little-endian) ................................................................................... ........ 48 1-8 cp0 registers............................................................................................................... ......................... 49 1-9 external circuit of clock oscillator........................................................................................ ................. 54 1-10 examples of oscillator with bad connection ................................................................................. ........ 55 2-1 v r 4102 signal classification..................................................................................................... ............. 62 3-1 cpu instruction formats..................................................................................................... ................... 81 3-2 byte specification related to load and store instructions ................................................................... .83 4-1 pipeline stages ............................................................................................................. ......................... 99 4-2 instruction execution in the pipeline....................................................................................... ............... 100 4-3 pipeline activities......................................................................................................... .......................... 100 4-4 branch delay ................................................................................................................ ......................... 102 4-5 add instruction pipeline activities......................................................................................... ................. 103 4-6 jalr instruction pipeline activities ........................................................................................ ............... 104 4-7 beq instruction pipeline activities......................................................................................... ................ 105 4-8 tlt instruction pipeline activities......................................................................................... ................. 106 4-9 lw instruction pipeline activities.......................................................................................... ................. 107 4-10 sw instruction pipeline activities ......................................................................................... ................. 108 4-11 interlocks, exceptions, and faults ......................................................................................... ................ 109 4-12 exception detection ........................................................................................................ ....................... 112 4-13 data cache miss stall...................................................................................................... ...................... 113 4-14 cache instruction stall.................................................................................................... ..................... 113 4-15 load data interlock........................................................................................................ ........................ 114 4-16 md busy interlock.......................................................................................................... ........................ 114 5-1 virtual-to-physical address translation ..................................................................................... ............ 118 5-2 32-bit mode virtual address translation..................................................................................... ........... 119 5-3 64-bit mode virtual address translation..................................................................................... ........... 120 5-4 user mode address space ..................................................................................................... ............... 122 5-5 supervisor mode address space ............................................................................................... ........... 125 5-6 kernel mode address space ................................................................................................... .............. 128 5-7 xkphys area address space................................................................................................... ............... 129 5-8 v r 4102 physical address space .................................................................................................... ....... 135 5-9 cp0 registers and the tlb ................................................................................................... ................ 141 5-10 format of a tlb entry...................................................................................................... ...................... 142 5-11 format of a tlb entry...................................................................................................... ...................... 143 21 list of figures (2/4) fig. no. title page 5-12 index register ............................................................................................................. ........................... 146 5-13 random register............................................................................................................ ........................ 146 5-14 positions indicated by the wired register.................................................................................. ............ 148 5-15 wired register ............................................................................................................. ........................... 148 5-16 prid register .............................................................................................................. ........................... 149 5-17 config register format..................................................................................................... ...................... 150 5-18 lladdr register............................................................................................................ .......................... 151 5-19 taglo and taghi registers.................................................................................................. .................. 152 5-20 tlb address translation .................................................................................................... .................... 154 6-1 context register format..................................................................................................... .................... 160 6-2 badvaddr register format.................................................................................................... ................. 161 6-3 count register format ....................................................................................................... .................... 161 6-4 compare register format ..................................................................................................... ................. 162 6-5 status register format...................................................................................................... ..................... 162 6-6 status register diagnostic status field ..................................................................................... ............ 163 6-7 cause register format....................................................................................................... .................... 165 6-8 epc register format......................................................................................................... ..................... 167 6-9 watchlo and watchhi register format ......................................................................................... ........ 168 6-10 xcontext register format ................................................................................................... ................... 169 6-11 parity error register format............................................................................................... .................... 170 6-12 cacheerr register format................................................................................................... ................... 171 6-13 the errorepc register format ............................................................................................... ............... 172 6-14 common exception handler................................................................................................... ................ 192 6-15 tlb/xtlb refill exception handler.......................................................................................... .............. 194 6-16 cache error exception handler .............................................................................................. ................ 196 6-17 cold reset, soft reset, and nmi exception handler .......................................................................... ... 197 7-1 rtc reset ................................................................................................................... ........................... 200 7-2 rstsw....................................................................................................................... ............................ 201 7-3 deadmans switch ............................................................................................................ ...................... 202 7-4 software shutdown........................................................................................................... ...................... 203 7-5 haltimer shutdown........................................................................................................... .................... 204 7-6 v r 4102 activation sequence (when battery check is ok) .................................................................... 206 7-7 v r 4102 activation sequence (when battery check is ng) .................................................................... 206 7-8 cold reset .................................................................................................................. ............................ 209 7-9 soft reset .................................................................................................................. ............................. 209 8-1 logical hierarchy of memory ................................................................................................. ................. 213 8-2 cache support............................................................................................................... ......................... 214 8-3 cache line format ........................................................................................................... ...................... 215 8-4 data cache line format...................................................................................................... ................... 215 8-5 cache data and tag organization ............................................................................................. ............ 216 8-6 data cache state diagram.................................................................................................... ................. 219 22 list of figures (3/4) fig. no. title page 8-7 instruction cache state diagram ............................................................................................. .............. 219 8-8 data flow on instruction fetch .............................................................................................. ................. 220 8-9 data integrity on load operations ........................................................................................... .............. 221 8-10 data integrity on store operations ......................................................................................... ............... 222 8-11 data integrity on index_invalidate operations.............................................................................. ......... 223 8-12 data integrity on index_writeback_invalidate operations.................................................................... . 223 8-13 data integrity on index_load_tag operations ................................................................................ ...... 224 8-14 data integrity on index_store_tag operations ............................................................................... ...... 224 8-15 data integrity on create_dirty operations.................................................................................. ........... 225 8-16 data integrity on hit_invalidate operations ................................................................................ ........... 225 8-17 data integrity on hit_writeback_invalidate operations ...................................................................... ... 226 8-18 data integrity on fill operations .......................................................................................... .................. 226 8-19 data integrity on hit_writeback operations................................................................................. .......... 227 8-20 data integrity on writeback flow ........................................................................................... ................ 228 8-21 data integrity on refill flow .............................................................................................. ..................... 228 8-22 data integrity on writeback & refill flow.................................................................................. ............. 229 9-1 non-maskable interrupt signal ............................................................................................... ............... 231 9-2 hardware interrupt signals .................................................................................................. .................. 233 9-3 masking of the cpu core interrupts .......................................................................................... ............ 234 10-1 rom 4-byte read, 16-bit mode (wroma[2:0] = 110)........................................................................... 2 53 10-2 rom 4-byte read, 32-bit mode (wroma[2:0] = 110)........................................................................... 2 53 10-3 pagerom 4-word read, 16-bit mode (wroma[2:0] = 111, wprom[1:0] = 10) .................................. 254 10-4 pagerom 4-word read, 32-bit mode (wroma[2:0] = 111, wprom[1:0] = 10) .................................. 255 10-5 flash memory mode, 2-byte access........................................................................................... ........... 255 10-6 1-byte access to even address using 16-bit bus (wisaa[2:0] = 101).................................................. 256 10-7 2-byte access when sampling iochrdy at high level using 16-bit bus (wisaa[2:0] = 101) ............ 257 10-8 1-byte access to odd address using 16-bit bus (wisaa[2:0] = 101) ................................................... 258 10-9 1-byte access to odd address using 8-bit bus (wisaa[2:0] = 101) ..................................................... 258 10-10 2-byte access when sampling zws# at low level on 16-bit bus (wisaa[2:0] = 101) ........................ 259 10-11 2-byte access when sampling zws# at low level on 8-bit bus (wisaa[2:0] = 101) .......................... 260 10-12 2-byte access on 16-bit bus (wlcd/m[2:0] = 101) ........................................................................... .... 261 10-13 1-byte access on 8-bit bus (wlcd/m[2:0] = 101) ............................................................................ ..... 261 10-14 2-byte access when sampling zws# at low level on 16-bit bus (wlcd/m[2:0] = 101)..................... 262 10-15 1-byte access when sampling zws# at low level on 8-bit bus (wlcd/m[2:0] = 101)....................... 262 10-16 2-byte access to lcd controller (wlcd/m[2:0] = 010)....................................................................... .. 263 10-17 2-byte access to lcd controller (wlcd/m[2:0] = 011)....................................................................... .. 263 10-18 4-byte access to dram (16-bit mode) ....................................................................................... ........... 264 10-19 8-byte access to dram (32-bit mode) ....................................................................................... ........... 264 10-20 byte read of odd address in dram (16-bit mode)............................................................................ ... 265 10-21 byte read of even address in dram (16-bit mode) ........................................................................... .. 265 10-22 byte write to odd address in dram (16-bit mode)........................................................................... .... 266 10-23 byte write to even address in dram (16-bit mode) .......................................................................... ... 266 23 list of figures (4/4) fig. no. title page 10-24 cbr refresh (16-bit mode) ................................................................................................. ................... 267 10-25 self refresh (16-bit mode)................................................................................................ ...................... 267 10-26 bus hold in fullspeed mode................................................................................................ ................... 268 10-27 bus hold in suspend mode .................................................................................................. .................. 269 11-1 dma space used in dma transfers ............................................................................................ .......... 271 13-1 block diagram of cmu and peripheral blocks ................................................................................. ...... 289 14-1 interrupt control outline .................................................................................................. ....................... 293 15-1 activation via power switch interrupt (battinh/battint# = 1)........................................................... 321 15-2 activation via power switch interrupt (battinh/battint# = 0)........................................................... 321 15-3 activation via gpio activation interrupt (battinh/battint# = 1)....................................................... 322 15-4 activation via gpio activation interrupt (battinh/battint# = 0)....................................................... 322 15-5 activation via dcd interrupt (battinh/battint# = 1)........................................................................ . 323 15-6 activation via dcd interrupt (battinh/battint# = 0)........................................................................ . 323 15-7 activation via alarm interrupt (battinh/battint# = 1) ...................................................................... . 324 15-8 activation via alarm interrupt (battinh/battint# = 0) ...................................................................... . 324 15-9 power mode state transition ................................................................................................ ................. 325 19-1 piu peripheral block diagram ............................................................................................... ................. 382 19-2 equivalent circuit of coordinate detection ................................................................................. ............ 382 19-3 internal block diagram of piu .............................................................................................. .................. 383 19-4 scan sequencer state transition diagram .................................................................................... ........ 384 19-5 interval times and states .................................................................................................. ..................... 391 19-6 touch/release detection timing............................................................................................. ............... 404 19-7 a/d port scan timing ....................................................................................................... ...................... 404 22-1 data format for transmission and reception ................................................................................. ....... 448 22-2 transmit complete interrupt timing ......................................................................................... .............. 450 22-3 receive complete interrupt timing .......................................................................................... .............. 451 22-4 receive error timing ....................................................................................................... ....................... 452 24-1 connection example between the v r 4102 and irda module ............................................................... 479 25-1 hsp unit block diagram..................................................................................................... .................... 482 25-2 circuit configuration block diagram examples ............................................................................... ....... 482 25-3 block diagram of hsp interface power control ............................................................................... ...... 494 27-1 v r 4102 opcode bit encoding....................................................................................................... .......... 674 29-1 example of connection of pll passive components ............................................................................ 683 24 list of tables (1/4) table. no. title page 1-1 bcu registers ............................................................................................................... ........................ 33 1-2 dmaau registers............................................................................................................. ..................... 33 1-3 dcu registers ............................................................................................................... ........................ 34 1-4 cmu register ................................................................................................................ ........................ 34 1-5 icu registers............................................................................................................... .......................... 35 1-6 pmu registers............................................................................................................... ........................ 35 1-7 rtc registers ............................................................................................................... ........................ 36 1-8 dsu registers ............................................................................................................... ........................ 37 1-9 giu registers ............................................................................................................... ......................... 37 1-10 piu registers.............................................................................................................. ........................... 38 1-11 aiu registers.............................................................................................................. ........................... 39 1-12 kiu registers.............................................................................................................. ........................... 40 1-13 dsiu registers ............................................................................................................. ......................... 40 1-14 led registers.............................................................................................................. .......................... 41 1-15 siu registers.............................................................................................................. ........................... 41 1-16 hsp registers .............................................................................................................. ......................... 41 1-17 fir registers .............................................................................................................. ........................... 42 1-18 system control coprocessor (cp0) register definitions ...................................................................... 50 2-1 system bus interface signals ................................................................................................ ................ 63 2-2 clock interface signals ..................................................................................................... ..................... 65 2-3 battery monitor interface signals........................................................................................... ................ 65 2-4 initialization interface signals ............................................................................................ .................... 66 2-5 rs-232-c interface signals .................................................................................................. ................. 67 2-6 irda interface signals ...................................................................................................... ...................... 68 2-7 debug serial interface signals .............................................................................................. ................ 68 2-8 keyboard interface signals.................................................................................................. .................. 69 2-9 audio interface signals ..................................................................................................... ..................... 69 2-10 touch panel/general purpose a/d interface signals.......................................................................... .. 69 2-11 general-purpose i/o signals ................................................................................................ ................. 70 2-12 hsp modem interface signals ................................................................................................ ............. 71 2-13 led interface signal ....................................................................................................... ....................... 71 2-14 dedicated v dd and gnd signals ........................................................................................................... 72 2-15 status of pins upon reset .................................................................................................. ................... 73 2-16 connection of unused pins and pin i/o circuit type ......................................................................... ... 76 3-1 number of delay slot cycles necessary for load and store instructions............................................. 82 3-2 load/store instruction ...................................................................................................... ...................... 84 3-3 load/store instruction (extended isa) ....................................................................................... ............ 85 3-4 alu immediate instruction................................................................................................... .................. 86 3-5 alu immediate instruction (extended isa) .................................................................................... ....... 87 3-6 three operand type instruction .............................................................................................. .............. 87 3-7 three operand type instruction (extended isa)............................................................................... .... 88 3-8 shift instruction ........................................................................................................... ........................... 88 25 list of tables (2/4) table. no. title page 3-9 shift instruction (extended isa)............................................................................................ .................. 89 3-10 multiply/divide instructions ............................................................................................... ...................... 90 3-11 multiply/divide instructions (extended isa)................................................................................ ............ 90 3-12 number of stall cycles in multiply and divide instructions................................................................. .... 91 3-13 number of delay slot cycles in jump and branch instructions ............................................................. 92 3-14 jump instructions .......................................................................................................... ......................... 93 3-15 branch instructions........................................................................................................ ......................... 94 3-16 branch instructions (extended isa)......................................................................................... ............... 95 3-17 special instructions ....................................................................................................... ......................... 96 3-18 special instructions (extended isa) ........................................................................................ ............... 96 3-19 system control coprocessor (cp0) instructions .............................................................................. ...... 97 4-1 description of pipeline activities during each stage ........................................................................ ...... 101 4-2 correspondence of pipeline stage to interlock and exception condition .............................................. 110 4-3 description of pipeline exception ........................................................................................... ................ 111 4-4 pipeline interlock .......................................................................................................... .......................... 111 5-1 comparison of useg and xuseg ................................................................................................ .............. 122 5-2 32-bit and 64-bit supervisor mode segments .................................................................................. ...... 126 5-3 32-bit kernel mode segments ................................................................................................. ............... 130 5-4 64-bit kernel mode segments ................................................................................................. ............... 132 5-5 cacheability and the xkphys address space ................................................................................... ...... 133 5-6 v r 4102 physical address space.................................................................................................... ........ 136 5-7 rom addresses (when using 16-bit data bus) .................................................................................. ..... 137 5-8 rom addresses (when using 32-bit data bus) .................................................................................. ..... 137 5-9 internal i/o space 1........................................................................................................ ........................ 139 5-10 internal i/o space 2....................................................................................................... ......................... 139 5-11 dram addresses (when using 16-bit data bus)................................................................................ ..... 140 5-12 dram addresses (when using 32-bit data bus)................................................................................ ..... 140 5-13 cache algorithm ............................................................................................................ ......................... 145 5-14 mask values and page sizes ................................................................................................. ................ 147 6-1 cp0 exception processing registers .......................................................................................... ........... 159 6-2 cause register exception code field......................................................................................... ........... 166 6-3 64-bit mode exception vector base addresses ................................................................................. .... 174 6-4 32-bit mode exception vector base addresses ................................................................................. .... 174 6-5 exception priority order.................................................................................................... ...................... 176 10-1 bcu registers .............................................................................................................. .......................... 235 10-2 address bit correspondence between add bus and external devices ................................................ 246 10-3 address connection table with external devices ............................................................................. ..... 246 10-4 access size restrictions for address spaces................................................................................ ........ 247 10-5 summary of rom modes ....................................................................................................... ................ 248 10-6 example of bit inversion in data in v r 4102 and at data [15:0] pins .................................................... 250 26 list of tables (3/4) table. no. title page 10-7 illegal access notification methods ........................................................................................ ............... 251 10-8 access times during ordinary rom read mode ................................................................................. . 252 10-9 pagerom read mode access time .............................................................................................. ....... 254 10-10 system bus access times ................................................................................................... ................. 256 10-11 high-speed system bus access times ........................................................................................ ........ 260 10-12 access times for lcd interface ............................................................................................ ................ 263 11-1 dmaau registers............................................................................................................ ...................... 272 12-1 dma priority levels ........................................................................................................ ....................... 281 12-2 dcu registers .............................................................................................................. ......................... 281 13-1 cmu register ............................................................................................................... ......................... 289 14-1 icu registers.............................................................................................................. ........................... 294 15-1 bit operations during reset................................................................................................ ................... 319 15-2 bit operations during shutdown ............................................................................................. ............... 320 15-3 power mode................................................................................................................. .......................... 326 15-4 pmu registers.............................................................................................................. ......................... 327 16-1 rtc registers .............................................................................................................. ......................... 336 17-1 dsu registers .............................................................................................................. ......................... 355 18-1 gpio pin functions ......................................................................................................... ...................... 361 18-2 giu registers .............................................................................................................. .......................... 362 18-3 table of correspondences between gpio[47..32] and function pins .................................................. 379 18-4 table of correspondence between gpio[48] and function pin............................................................ 380 19-1 piu registers.............................................................................................................. ........................... 386 19-2 piucntreg bit manipulation and states ...................................................................................... ....... 389 19-3 piuascnreg bit manipulation and states..................................................................................... ...... 396 19-4 detected coordinates and page buffers ...................................................................................... ......... 399 19-5 a/d ports and data buffers................................................................................................. ................... 400 19-6 comparison of pius of v r 4102 and v r 4101.......................................................................................... 407 20-1 aiu registers.............................................................................................................. ........................... 409 21-1 kiu registers.............................................................................................................. ........................... 423 22-1 dsiu registers ............................................................................................................. ......................... 435 22-2 receive error causes....................................................................................................... ..................... 452 27 list of tables (4/4) table. no. title page 23-1 led registers.............................................................................................................. ........................... 453 24-1 siu registers.............................................................................................................. ............................ 461 24-2 correspondence between baud rates and divisors ............................................................................. . 466 24-3 interrupt function ......................................................................................................... .......................... 468 25-1 hsp registers .............................................................................................................. .......................... 483 25-2 control register definitions ............................................................................................... ..................... 485 26-1 fir registers.............................................................................................................. ............................ 498 27-1 cpu instruction operation notations........................................................................................ .............. 526 27-2 load and store common functions ............................................................................................ ........... 527 27-3 access type specifications for loads/stores ................................................................................ ........ 528 28-1 v r 4102 coprocessor 0 hazards..................................................................................................... ........ 678 28-2 calculation example of cp0 hazard and the number of instructions inserted ...................................... 681 28 [memo] 29 chapter 1 introduction this chapter describes the outline of the v r 4102 ( m pd30102), which is a 64-/32-bit risc microprocessor. 1.1 features the v r 4102, which is a high-performance 64-/32-bit microprocessor employing the risc (reduced instruction set computer) architecture developed by mips, is one of the risc microprocessor v r -seriestm products manufactured by nec. the v r 4102 is ideally suited for battery-driven high-performance portable information equipment. it mainly consists of the high-performance ultra-low-power consumption v r 4102 cpu core, and has various peripheral functions including a dma controller, software modem interface, serial interface, keyboard interface, irda interface, touch panel interface, real-time clock, a/d converter, and d/a converter. the external bus width of this device can be selected between 32 bits and 16 bits. this function enables the v r 4102 to process voluminous data at high speed. the features of the v r 4102 are described below. ? employs 64-bit risc cpu core (v r 4100 equivalent) ? internal 64-bit processing ? optimized 5-stage pipeline ? conforms to mips i, ii, iii instruction sets (with the fpu, ll, and sc instructions left out) ? supports high-speed product-sum operation instructions to execute applications in high speed ? on-chip 4-kbyte instruction cache and 1-kbyte data cache ? 32-double-entry translation lookaside buffer (tlb) for virtual address management ? 32-bit physical address space and 40-bit virtual address space (in 64-bit mode) ? on-chip peripheral units suited for portable equipment memory controller (supports rom, edo-type dram, and flash memory) isa-bus interface keyboard interface touch panel interface (on-chip 4-channel a/d converter) controller complying with irda 1.1 (fir) software modem interface dma controller serial interface debug serial interfaces interrupt controller audio interface (on-chip digital i/o, a/d and d/a converters) general-purpose a/d converter: 3 channels general-purpose ports ? effective power management features, which include the following four operating modes: fullspeed mode: normal operating mode in which all clocks operate standby mode: all internal clocks stop except for interrupt-related clocks suspend mode: bus clock and all internal clocks stop except for interrupt-related clocks hibernate mode: all clocks generated by the cpu core stop chapter 1 introduction 30 ? external input clock: 32.768 khz, 18.432 mhz (for internal cpu core and peripheral unit operation), 48 mhz (dedicated for fir irda interface) ? supports isa bus subset ? clock supply management function for each on-chip peripheral unit to implement low-power consumption ? operation supply voltage: v dd = 3.0 to 3.6 v 1.2 ordering information part number package maximum operation frequency m pd30102gm-54-8ev 216-pin plastic lqfp (fine pitch) (24 24 mm) 54 mhz m pd30102gm-66-8ev 216-pin plastic lqfp (fine pitch) (24 24 mm) 66 mhz m pd30102s1-54-3c 224-pin plastic fbga (16 16 mm) 54 mhz m pd30102s1-66-3c 224-pin plastic fbga (16 16 mm) 66 mhz 1.3 64-bit architecture the v r 4102 microprocessor has a 64-bit architecture. however, it can also run 32-bit applications. 1.4 v r 4102 processor the v r 4102 consists of the v r 4100 cpu core and seventeen peripheral units. it can connect external controllers directly. figure 1-1 is an internal block diagram of the v r 4102 processor. figure 1-1. v r 4102 internal block diagram and example of connection to external blocks m pd16666 48mhz v r 4100 cpu core bcu dmaau pmu icu dsu rtc cmu piu kiu giu aiu siu osb osb rs-232-c driver lcd module pcmcia / buffer v r 4102 32.768khz lcd panel m pd16661 touch panel edo dram pccard a/d d/a hsp codec afe 18.432mhz pll ir driver fir dcu led rom/ flash memory chapter 1 introduction 31 1.4.1 internal block structure the following provides an outline of the peripheral units. for the cpu core, refer to 1.5 v r 4100 cpu core . (1) bus control unit (bcu) in the v r 4102, the bus control unit (bcu) transfers data between the v r 4100 cpu core and sysad bus. it also controls external circuits, such as the lcd controller connected to the system bus, dram, rom (flash memory or masked rom), and pcmcia controller, and transfers data between the v r 4102 and these external devices, using the address and data buses. (2) real-time clock unit (rtc) the real-time clock (rtc) is provided with an accurate counter that operates on a 32.768-khz clock pulse supplied from the clock generator. it is also provided with several counters and compare registers for controlling various interrupts. (3) deadmans switch unit (dsu) the deadmans switch unit (dsu) is used to check whether the processor is running normally. if the register of this unit is not cleared by software within a specified period, the system is shut down. (4) interrupt control unit (icu) the interrupt control unit (icu) controls interrupt requests that are caused by factors either internal or external to the v r 4102, and informs the v r 4100 cpu core when an interrupt request occurs. (5) power management unit (pmu) the power management unit (pmu) outputs signals necessary to control the power of the entire system including the v r 4102. the signals are used to control the pll of the v r 4100 cpu core and the internal clocks (pipeline clock, tclock, and masterout) in low-power modes. (6) direct memory access address unit (dmaau) the direct memory access address unit (dmaau) controls the address of three different dma transfers. (7) direct memory access control unit (dcu) the direct memory access control unit (dcu) controls the arbitration of three different dma transfers. (8) clock mask unit (cmu) the clock mask unit (cmu) controls the way the clocks tclock and masterout are supplied from the v r 4100 cpu core to internal peripheral units. (9) general purpose i/o unit (giu) the general purpose i/o unit (giu) controls 49 gpio pins. (10) audio interface unit (aiu) the audio interface unit (aiu) executes mic-input sampling and audio signal output by controlling the internal a/d converter and d/a converter. chapter 1 introduction 32 (11) keyboard interface unit (kiu) the keyboard interface unit (kiu) has 12 scan lines and 8 detection lines. it can detect when any of 64/80/96 keys are pressed. it supports key rollover for two to three continuous strokes. (12) touch panel interface unit (piu) the touch panel interface unit (piu) detects when the touch panel is touched, by controlling the internal a/d converter. (13) debug serial interface unit (dsiu) the debug serial interface unit (dsiu) is a serial interface for debugging. it supports a maximum transfer rate of 115 kbps. (14) serial interface unit (siu) the serial interface unit (siu) conforms to the rs-232-c specification and is compatible with 16550. it supports a maximum transfer rate of 1.15 mbps. also available is an irda serial interface supporting a maximum transfer rate of 115 kbps, but this interface and the rs-232-c interface are mutually exclusive. (15) fast irda interface unit (fir) the fir unit is a unit for performing 0.5- to 4-mbps irda communication. this unit operates based on a dedicated 48-mhz clock input. (16) host signal processing unit (hsp) the hsp unit is used to realize a software modem. it interfaces the cpu core with an external codec device, and controls them. (17) light emitting diode unit (led) the led unit is used to control the lighting of external led. chapter 1 introduction 33 1.4.2 i/o registers the i/o registers are used for peripheral unit control. table 1-1. bcu registers register symbols function address bcucntreg 1 bcu control register 1 0x0b00 0000 bcucntreg 2 bcu control register 2 0x0b00 0002 bcuspeedreg bcu access cycle change register 0x0b00 000a bcuerrstreg bcu bus error status register 0x0b00 000c bcurfcntreg bcu refresh control register 0x0b00 000e revidreg peripheral unit revision id register 0x0b00 0010 bcurfcountreg bcu refresh cycle count register 0x0b00 0012 clkspeedreg clock setting register 0x0b00 0014 table 1-2. dmaau registers register symbols function address aiuibalreg aiu in dma base address register low 0x0b00 0020 aiuibahreg aiu in dma base address register high 0x0b00 0022 aiuialreg aiu in dma address register low 0x0b00 0024 aiuiahreg aiu in dma address register high 0x0b00 0026 aiuobalreg aiu out dma base address register low 0x0b00 0028 aiuobahreg aiu out dma base address register high 0x0b00 002a aiuoalreg aiu out dma address register low 0x0b00 002c aiuoahreg aiu out dma address register high 0x0b00 002e firbalreg fir dma base address register low 0x0b00 0030 firbahreg fir dma base address register high 0x0b00 0032 firalreg fir dma address register low 0x0b00 0034 firahreg fir dma address register high 0x0b00 0036 chapter 1 introduction 34 table 1-3. dcu registers register symbols function address dmarstreg dma reset register 0x0b00 0040 dmaidlereg dma sequencer status register 0x0b00 0042 dmasenreg dma sequencer enable register 0x0b00 0044 dmamskreg dma mask register 0x0b00 0046 dmareqreg dma request register 0x0b00 0048 tdreg transfer direction setting register 0x0b00 004a table 1-4. cmu register register symbol function address cmuclkmsk cmu clock mask register 0x0b00 0060 chapter 1 introduction 35 table 1-5. icu registers register symbols function address sysint1reg level 1 system interrupt register 1 0x0b00 0080 piuintreg level 2 piu interrupt register 0x0b00 0082 aiuintreg level 2 aiu interrupt register 0x0b00 0084 kiuintreg level 2 kiu interrupt register 0x0b00 0086 giuintlreg level 2 giu interrupt register low 0x0b00 0088 dsiuintreg level 2 dsiu interrupt register 0x0b00 008a msysint1reg level 1 mask system interrupt register 1 0x0b00 008c mpiuintreg level 2 mask piu interrupt register 0x0b00 008e maiuintreg level 2 mask aiu interrupt register 0x0b00 0090 mkiuintreg level 2 mask kiu interrupt register 0x0b00 0092 mgiuintlreg level 2 mask giu interrupt register low 0x0b00 0094 mdsiuintreg level 2 mask dsiu interrupt register 0x0b00 0096 nmireg battery interrupt select register 0x0b00 0098 softintreg software interrupt register 0x0b00 009a sysint2reg level 1 system interrupt register 2 0x0b00 0200 giuinthreg level 2 giu interrupt register high 0x0b00 0202 firintreg level 2 fir interrupt register 0x0b00 0204 msysint2reg level 1 mask system interrupt register 2 0x0b00 0206 mgiuinthreg level 2 mask giu interrupt register high 0x0b00 0208 mfirintreg level 2 mask fir interrupt register 0x0b00 020a table 1-6. pmu registers register symbols function address pmuintreg pmu interrupt/status register 0x0b00 00a0 pmucntreg pmu control register 0x0b00 00a2 pmuint2reg pmu interrupt register 2 0x0b00 00a4 pmucnt2reg pmu control register 2 0x0b00 00a6 chapter 1 introduction 36 table 1-7. rtc registers register symbols function address etimelreg elapsed time l register 0x0b00 00c0 etimemreg elapsed time m register 0x0b00 00c2 etimehreg elapsed time h register 0x0b00 00c4 ecmplreg elapsed compare l register 0x0b00 00c8 ecmpmreg elapsed compare m register 0x0b00 00ca ecmphreg elapsed compare h register 0x0b00 00cc rtcl1lreg rtc long 1 l register 0x0b00 00d0 rtcl1hreg rtc long 1 h register 0x0b00 00d2 rtcl1cntlreg rtc long 1 count l register 0x0b00 00d4 rtcl1cnthreg rtc long 1 count h register 0x0b00 00d6 rtcl2lreg rtc long 2 l register 0x0b00 00d8 rtcl2hreg rtc long 2 h register 0x0b00 00da rtcl2cntlreg rtc long 2 count l register 0x0b00 00dc rtcl2cnthreg rtc long 2 count h register 0x0b00 00de tclklreg tclock l register 0x0b00 01c0 tclkhreg tclock h register 0x0b00 01c2 tclkcntlreg tclock count l register 0x0b00 01c4 tclkcnthreg tclock count h register 0x0b00 01c6 rtcintreg rtc interrupt register 0x0b00 01de chapter 1 introduction 37 table 1-8. dsu registers register symbols function address dsucntreg dsu control register 0x0b00 00e0 dsusetreg dsu cycle (dead time) set register 0x0b00 00e2 dsuclrreg dsu clear register 0x0b00 00e4 dsutimreg dsu elapsed time register 0x0b00 00e6 table 1-9. giu registers register symbols function address giuiosell gpio input/output select register l 0x0b00 0100 giuioselh gpio input/output select register h 0x0b00 0102 giupiodl gpio port input/output data register l 0x0b00 0104 giupiodh gpio port input/output data register h 0x0b00 0106 giuintstatl gpio interrupt status register l 0x0b00 0108 giuintstath gpio interrupt status register h 0x0b00 010a giuintenl gpio interrupt enable register l 0x0b00 010c giuintenh gpio interrupt enable register h 0x0b00 010e giuinttypl gpio interrupt type (edge or level) select register l 0x0b00 0110 giuinttyph gpio interrupt type (edge or level) select register h 0x0b00 0112 giuintalsell gpio interrupt active level select register l 0x0b00 0114 giuintalselh gpio interrupt active level select register h 0x0b00 0116 giuinthtsell gpio interrupt hold/through select register l 0x0b00 0118 giuinthtselh gpio interrupt hold/through select register h 0x0b00 011a giupodatl gpio port output data register l 0x0b00 011c giupodath gpio port output data register h 0x0b00 011e chapter 1 introduction 38 table 1-10. piu registers register symbols function address piucntreg piu control register 0x0b00 0122 piuintreg piu interrupt cause register 0x0b00 0124 piusivlreg piu data sampling interval register 0x0b00 0126 piustblreg piu a/d converter start delay register 0x0b00 0128 piucmdreg piu a/d command register 0x0b00 012a piuascnreg piu a/d port scan register 0x0b00 0130 piuamskreg piu a/d scan mask register 0x0b00 0132 piucivlreg piu check interval register 0x0b00 013e piupb00reg piu page 0 buffer 0 register 0x0b00 02a0 piupb01reg piu page 0 buffer 1 register 0x0b00 02a2 piupb02reg piu page 0 buffer 2 register 0x0b00 02a4 piupb03reg piu page 0 buffer 3 register 0x0b00 02a6 piupb10reg piu page 1 buffer 0 register 0x0b00 02a8 piupb11reg piu page 1 buffer 1 register 0x0b00 02aa piupb12reg piu page 1 buffer 2 register 0x0b00 02ac piupb13reg piu page 1 buffer 3 register 0x0b00 02ae piuab0reg piu ad scan buffer 0 register 0x0b00 02b0 piuab1reg piu ad scan buffer 1 register 0x0b00 02b2 piuab2reg piu ad scan buffer 2 register 0x0b00 02b4 piuab3reg piu ad scan buffer 3 register 0x0b00 02b6 piupb04reg piu page 0 buffer 4 register 0x0b00 02bc piupb14reg piu page 1 buffer 4 register 0x0b00 02be chapter 1 introduction 39 table 1-11. aiu registers register symbols function address mdmadatreg mike dma data register 0x0b00 0160 sdmadatreg speaker dma data register 0x0b00 0162 sodatreg speaker output data register 0x0b00 0166 scntreg speaker output control register 0x0b00 0168 scnvrreg speaker conversion rate register 0x0b00 016a midatreg mike input data register 0x0b00 0170 mcntreg mike input control register 0x0b00 0172 mcnvrreg mike conversion rate register 0x0b00 0174 dvalidreg data valid register 0x0b00 0178 seqreg sequential operation enable register 0x0b00 017a intreg aiu interrupt register 0x0b00 017c chapter 1 introduction 40 table 1-12. kiu registers register symbols function address kiudat0 kiu data0 register 0x0b00 0180 kiudat1 kiu data1 register 0x0b00 0182 kiudat2 kiu data2 register 0x0b00 0184 kiudat3 kiu data3 register 0x0b00 0186 kiudat4 kiu data4 register 0x0b00 0188 kiudat5 kiu data5 register 0x0b00 018a kiuscanrep kiu scan/repeat register 0x0b00 0190 kiuscans kiu scan status register 0x0b00 0192 kiuwks kiu wait keyscan stable register 0x0b00 0194 kiuwki kiu wait keyscan interval register 0x0b00 0196 kiuint kiu interrupt register 0x0b00 0198 kiurst kiu reset register 0x0b00 019a kiugpen kiu general purpose output enable register 0x0b00 019c scanline kiu scan line register 0x0b00 019e table 1-13. dsiu registers register symbols function address portreg port change register 0x0b00 01a0 modemreg modem control register 0x0b00 01a2 asim00reg asynchronous mode 0 register 0x0b00 01a4 asim01reg asynchronous mode 1 register 0x0b00 01a6 rxb0rreg receive buffer register (extended) 0x0b00 01a8 rxb0lreg receive buffer register 0x0b00 01aa txs0rreg transmit data register (extended) 0x0b00 01ac txs0lreg transmit data register 0x0b00 01ae asis0reg status register 0x0b00 01b0 intr0reg debug siu interrupt register 0x0b00 01b2 bprm0reg baud-rate generator prescaler mode register 0x0b00 01b6 dsiuresetreg debug siu reset register 0x0b00 01b8 chapter 1 introduction 41 table 1-14. led registers register symbols function address ledhtsreg led h time set register 0x0b00 0240 ledltsreg led l time set register 0x0b00 0242 ledcntreg led control register 0x0b00 0248 ledastcreg led auto stop time count register 0x0b00 024a ledintreg led interrupt register 0x0b00 024c table 1-15. siu registers register symbols function lcr[7] address siurb receiver buffer register (read) siuth transmitter holding register (write) 0 siudll divisor latch (least significant byte) register 1 0x0c00 0000 siuie interrupt enable register 0 siudlm divisor latch (most significant byte) register 1 0x0c00 0001 siuiid interrupt identification register (read) siufc fifo control register (write) - 0x0c00 0002 siulc line control register - 0x0c00 0003 siumc modem control register - 0x0c00 0004 siuls line status register - 0x0c00 0005 siums modem status register - 0x0c00 0006 siusc scratch register - 0x0c00 0007 siuirsel siu/fir irda selector - 0x0c00 0008 remark lcr[7] is bit 7 of the siulc register. table 1-16. hsp registers register symbols function address hspinit hsp initialize register 0x0c00 0020 hspdata[7:0] hsp data register [7:0] 0x0c00 0022 hspdata[15:8] hsp data register [15:8] 0x0c00 0023 hspindex hsp index register 0x0c00 0024 hspid[7:0] hsp id register 0x0c00 0028 hsppcs[7:0] hsp i/o address program confirmation register 0x0c00 0029 hsppctel[7:0] hsp signature checking port 0x0c00 0029 chapter 1 introduction 42 table 1-17. fir registers register symbols function address frstr fir reset register 0x0c00 0040 dpintr dma page interrupt register 0x0c00 0042 dpcntr dma page control register 0x0c00 0044 tdr transmit data register 0x0c00 0050 rdr receive data register 0x0c00 0052 imr interrupt mask register 0x0c00 0054 fsr fifo setup register 0x0c00 0056 irsr1 ir setup register 1 0x0c00 0058 crcsr crc setup register 0x0c00 005c fircr fir control register 0x0c00 005e mircr mir control register 0x0c00 0060 dmacr dma control register 0x0c00 0062 dmaer dma enable register 0x0c00 0064 txir transmission indicate register 0x0c00 0066 rxir reception indicate register 0x0c00 0068 ifr interrupt flag register 0x0c00 006a rxsts reception status register 0x0c00 006c txfl transmit frame length register 0x0c00 006e mrxf maximum receive frame length register 0x0c00 0070 rxfl receive frame length register 0x0c00 0074 chapter 1 introduction 43 1.5 v r 4100 cpu core figure 1-2. v r 4100 cpu core internal block diagram v r 4100 cpu core cpu cp0 instruction cache (4k bytes) data cache (1k bytes) bus interface clock generator address/data(o) address/data(i) internal clock id bus va bus control(o) control(i) tlb 1.5.1 v r 4100 cpu core (1) cpu bus interface the cpu bus interface controls data transmission/reception between the v r 4100 cpu core and the bcu, which is one of peripheral units. the v r 4100 cpu interface consists of two 32-bit multiplexed address/data buses (one is for input, and another is for output), clock signals, and control signals such as interrupts. (2) clock generator the following clock inputs are oscillated and supplied to internal units. x 32.768-khz clock for rtc unit: oscillating a 32.768-khz crystal resonator input via an internal oscillator to supply to the rtc unit. x 8.432-mhz clock for serial interface and the v r 4102s reference operating clock: oscillating an 18.432-mhz crystal resonator input via an internal oscillator, and then multiplying it by phase- locked loop (pll) to generate a pipeline clock (pclock). the internal bus clock (tclock) is generated from pclock and supplied to peripheral units. (3) instruction cache the instruction cache employs direct mapping, virtual index, and physical tag. its capacity is 4k bytes. (4) cpu cpu has hardware resources to process an integer instruction. they are the 64-bit register file, 64-bit integer data bus, and multiply-and-accumulate operation unit. chapter 1 introduction 44 (5) coprocessor 0 (cp0) cp0 incorporates a memory management unit (mmu) and exception handling function. mmu checks whether there is an access between different memory segments (user, supervisor, and kernel) by executing address conversion. the translation lookaside buffer (tlb) converts virtual addresses to physical addresses. (6) data cache the data cache employs direct mapping, virtual index, physical tag, and write back. its capacity is 1k bytes. chapter 1 introduction 45 1.5.2 cpu registers the v r 4100 cpu core has thirty two 64-bit general-purpose registers (gprs). in addition, the processor provides the following special, registers: ? 64-bit program counter (pc) ? 64-bit hi register, containing the integer multiply and divide upper doubleword result ? 64-bit lo register, containing the integer multiply and divide lower doubleword result two of the general-purpose registers have assigned the following functions: ? r0 is hardwired to a value of zero, and can be used as the target register for any instruction whose result is to be discarded. r0 can also be used as a source when a zero value is needed. ? r31 is the link register used by link instruction, such as jal/jalr instructions. this register can be used for other instructions. however, be careful that use of the register by a link instruction will not coincide with use of the register for other operations. the register group is provided within the cp0, to process exceptions and to manage addresses. cpu registers can operate as either 32-bit or 64-bit registers, depending on the v r 4102 processor mode of operation. figure 1-3 shows the cpu registers. figure 1-3. v r 4102 cpu registers general-purpose register r0 = 0 0 31 multiply/divide register 32 63 hi 0 31 32 63 lo program counter 0 pc 0 63 63 r1 r2 ? ? ? ? r29 r30 r31 = linkaddress 31 32 31 32 the v r 4102 has no program status word (psw) register as such; this is covered by the status and cause registers incorporated within the system control coprocessor (cp0). the cp0 registers are used for exception handling or address management. the overview of these registers is described in 1.5.5 coprocessors (cp0-cp3). chapter 1 introduction 46 1.5.3 cpu instruction set overview each cpu instruction is 32 bits long. as shown in figure 1-4, there are three instruction formats: ? immediate (i-type) ? jump (j-type) ? register (r-type) figure 1-4. cpu instruction formats i-type (immediate) op 0 15 16 20 21 25 26 31 j-type (jump) op target 0 25 26 31 r-type (register) op 0 15 16 20 21 25 26 31 5 6 10 11 rs rt immediate rs rt rd sa funct the instruction set can be further divided into the following five groupings: (1) load and store instructions move data between memory and general-purpose registers. they are all immediate (i-type) instructions, since the only addressing mode supported is base register plus 16-bit, signed immediate offset. (2) computational instructions perform arithmetic, logical, shift, multiply, and divide operations on values in registers. they include r-type (in which both the operands and the result are stored in registers) and i-type (in which one operand is a 16-bit signed immediate value) formats. (3) jump and branch instructions change the control flow of a program. jumps are always made to an absolute address formed by combining a 26-bit target address with the high-order bits of the program counter (j-type format) or register address (r-type format). the format of the branch instructions is i type. branches have 16-bit offsets relative to the program counter. jal instructions save their return address in register 31. (4) coprocessor 0 (system control coprocessor, cp0) instructions perform operations on cp0 registers to control the memory-management and exception-handling facilities of the processor. (5) special instructions perform system calls and breakpoint operations, or cause a branch to the general exception-handling vector based upon the result of a comparison. these instructions occur in both r-type (both the operands and the result are stored in registers) and i-type (one operand is a 16-bit signed immediate value) formats. chapter 3 provides a more detailed summary (refer to chapter 27 for detailed descriptions of the operation of each instruction) . chapter 1 introduction 47 1.5.4 data formats and addressing the v r 4102 uses following four data formats: doubleword (64 bits) word (32 bits) halfword (16 bits) byte (8 bits) for the v r 4100 cpu core, byte ordering within all of the larger data formats - halfword, word, doubleword - can be configured in either big-endian or little-endian order. however, the v r 4102 supports the little-endian order only. endianness refers to the location of byte 0 within the multi-byte data structure. figure 1-5 shows the ordering of bytes within words and the ordering of words within doubleword structures for the little-endian conventions. when configured as a little-endian system, byte 0 is always the least-significant (rightmost) byte, which is compatible with iapx tm and dec vax tm conventions. figure 1-5 shows this configuration. figure 1-5. little-endian byte ordering in word data 12 12 13 14 15 0 15 16 8 23 24 7 31 8 8 9 10 11 4 4 5 6 7 0 0 1 2 3 lower address higher address word address bit no. remarks 1. the lowest byte is the lowest address. 2. the address of word data is specified by the lowest bytes address. in this manual, bit 0 is always the least-significant (rightmost) bit; thus, bit designations are always little-endian. figure 1-6 shows little-endian byte ordering in doublewords. chapter 1 introduction 48 figure 1-6. little-endian byte ordering in double word data 16 23 0 31 32 87 63 8 0 lower address higher address double word address half word 22 15 14 7 6 21 20 13 12 5 4 19 18 11 10 3 2 17 16 9 8 1 0 16 15 word byte remarks 1. the lowest byte is the lowest address. 2. the address of word data is specified by the lowest bytes address. the cpu uses following byte boundaries for halfword, word, and doubleword accesses: ? halfword: an even byte boundary (0, 2, 4...) ? word: a byte boundary divisible by four (0, 4, 8...) ? doubleword: a byte boundary divisible by eight (0, 8, 16...) the following special instructions to load and store data that are not aligned on 4-byte (word) or 8-byte (doubleword) boundaries: lwl lwr swl swr ldl ldr sdl sdr these instructions are used in pairs to provide an access to misaligned data. accessing misaligned data incurs one additional instruction cycle over that required for accessing aligned data. figure 1-7 shows the access of a misaligned word that has byte address 3 for the little-endian conventions. figure 1-7. misaligned word accessing (little-endian) 5 6 4 0 15 16 8 23 24 7 31 3 lower address higher address bit no. chapter 1 introduction 49 1.5.5 coprocessors (cp0-cp3) mips isa defines 4 types of coprocessors (cp0 to cp3). cp1 is reserved to execute a floating-point instruction. cp2 and cp3 are reserved for future use. cp0 is an on- chip system control coprocessor, which supports the virtual memory system and exception handling. the virtual memory system is implemented using an on-chip tlb and the cp0 registers in the cpu. cp0 translates virtual addresses to physical addresses, switches the operating mode, (kernel, supervisor, or user mode), and management exceptions. it also controls the cache subsystem to analyze a cause and to return from the error state. figure 1-8 shows the definitions of the cp0 register, and table 1-18 shows simple descriptions of each register. for the detailed descriptions of the registers related to the virtual system memory, refer to chapter 5. for the detailed descriptions of the registers related to exception handling, refer to chapter 6. figure 1-8. cp0 registers 0 * for memory management ** for exception handling - reserved register no. register name index* 1 random* 2 entrylo0* 3 entrylo1* 4 context** 5 pagemask* 6 wired* 7 C 8 badvaddr** 9 count** 10 entryhi* 11 compare** 12 status** 13 cause** 14 epc** 15 prid* 16 register no. register name config* 17 lladdr* 18 watchlo** 19 watchhi** 20 xcontext** 21 C 22 C 23 C 24 C 25 C 26 perr** 27 cacheerr** 28 taglo* 29 taghi* 30 errorepc** 31 C chapter 1 introduction 50 table 1-18. system control coprocessor (cp0) register definitions number register description 0 index programmable pointer to tlb array 1 random pseudo-random pointer to tlb array (read only) 2 entrylo0 low half of tlb entry for even vpn 3 entrylo1 low half of tlb entry for odd vpn 4 context pointer to kernel virtual pte in 32-bit mode 5 pagemask tlb page mask 6 wired number of wired tlb entries 7 ? reserved for future use 8 badvaddr virtual address where the most recent error occurred 9 count timer count 10 entryhi high half of tlb entry (including asid) 11 compare timer compare 12 status status register 13 cause cause of last exception 14 epc exception program counter 15 prid processor revision identifier 16 config configuration register (specifying memory mode system) 17 lladdr reserved 18 watchlo memory reference trap address low bits 19 watchhi memory reference trap address high bits 20 xcontext pointer to kernel virtual pte in 64-bit mode 21 to 25 ? reserved for future use 26 perr cache parity bits 27 cacheerr index and status of cache error 28 taglo cache tag register (low) 29 taghi cache tag register (high) 30 errorepc error exception program counter 31 ? reserved for future use chapter 1 introduction 51 1.5.6 floating-point unit (fpu) the v r 4102 does not support the floating-point unit (fpu). coprocessor unusable exception will occur if any fpu instructions are executed. if necessary, fpu instructions should be emulated by software in an exception handler. 1.5.7 cache the v r 4102 chip incorporates instruction and data caches, which are independent of each other. this configuration enables high-performance pipeline operations. both caches have a 64-bit data bus, enabling a one- clock access. these buses can be accessed in parallel. the instruction cache of the v r 4102 has a storage capacity of 4 kb, while the data cache has a capacity of 1 kb. a detailed description of caches is given in chapete 8 cache organization and operation . chapter 1 introduction 52 1.6 cpu core memory management system (mmu) the v r 4102 has a 32-bit physical addressing range of 4 gbytes. however, since it is rare for systems to implement a physical memory space as large as that memory space, the cpu provides a logical expansion of memory space by translating addresses composed in the large virtual address space into available physical memory addresses. the v r 4102 supports the following two addressing modes: 32-bit mode, in which the virtual address space is divided into 2 gbytes for user process and 2 gbytes for the kernel. 64-bit mode, in which the virtual address is expanded to1 tbyte (2 40 bytes) of user virtual address space. a detailed description of these address spaces is given in chapter 4. 1.6.1 translation lookaside buffer (tlb) the tlb converts virtual addresses to physical addresses. it runs by a full-associative method. it has 32 entries, each mapping a pair of pages having a variable size (1 kb to 256 kb). (1) joint tlb (jtlb) for fast virtual-to-physical address decoding, the v r 4102 uses a large, fully associative tlb (joint tlb) that translates 64 virtual pages to their corresponding physical addresses. the tlb is organized as 32 pairs of even-odd entries, and maps a virtual address and address space identifier (asid) into the 4-gbyte physical address space. the page size can be configured, on a per-entry basis, to map a page size of 1 kb to 256 kb. a cp0 register stores the size of the page to be mapped, and that size is entered into the tlb when a new entry is written. thus, operating systems can provide special purpose maps; for example, a typical frame buffer can be memory-mapped using only one tlb entry. translating a virtual address to a physical address begins by comparing the virtual address from the processor with the physical addresses in the tlb; there is a match when the virtual page number (vpn) of the address is the same as the vpn field of the entry, and either the global (g) bit of the tlb entry is set, or the asid field of the virtual address is the same as the asid field of the tlb entry. this match is referred to as a tlb hit. if there is no match, a tlb miss exception is taken by the processor and software is allowed to refill the tlb from a page table of virtual/physical addresses in memory. 1.6.2 operating modes the v r 4102 has three operating modes: ? user mode ? supervisor mode ? kernel mode the manner in which memory addresses are translated or mapped depends on these operating modes. refer to chapter 5 memory management system for details. chapter 1 introduction 53 1.7 instruction pipeline the v r 4102 has a 5-stage instruction pipeline. under normal circumstances, one instruction is issued each cycle. a detailed description of pipeline is provided in chapter 4. 1.8 clock interface the v r 4102 has the following nine clocks. ? ? ? ? clkx1, clkx2 (input) these are oscillation inputs of 18.432 mhz, and used to generate operation clocks for the cpu core and serial interface. ? ? ? ? rtcx1, rtcx2 (input) these are oscillation inputs of 32.768 khz, and used for pmu and rtc. ? ? ? ? firclk (input) this is a 48-mhz clock input, and used for fir. ? ? ? ? pclock (internal) this clock is used to control the pipeline used in the v r 4100 cpu core, and for units relating to the pipeline. this clock is generated from the clock input of clkx1 and clkx2 pins. its frequency is determined by clksel[2..0] pins. ? ? ? ? masterout (internal) this is a bus clock of the v r 4100 cpu core, and used for interrupt control. its frequency is 1/4 of pclock frequency. ? ? ? ? tclock (internal) this is an operation clock for v r 4100 cpu core bus, internal bus of the v r 4102, and on-chip peripheral unit. in the current v r 4102, its frequency is 1/2 of pclock frequency. ? ? ? ? busclk (output) this clock is supplied to the controller on the system bus. its frequency in determined by clksel[2..0] pins. ? ? ? ? hspmclk (output) this clock is supplied to the external codec. its frequency is determined by the hspmclkd register. ? ? ? ? hspsclk (input) this is an operation clock for the external codec and the modem interface. figure 1-9 shows an external circuit of the clock oscillator. chapter 1 introduction 54 figure 1-9. external circuit of clock oscillator (a) crystal oscillation (b) external clock v r 4102 gnd note1 note2 v r 4102 note1 note2 external clock open notes 1. clkx1, rtcx1 2. clkx2, rtcx2 cautions 1. when using a clock oscillator, run wires in the area of this figure shown by broken lines, according to the following rules, to avoid effects such as stray capacitance: minimize the wire. never cause the wires to cross other signal lines or run near a line carrying a large varying current. cause the grounding point of the capacitor of the oscillator circuit to have the same potential as gnd. never connect the capacitor to a ground pattern carrying a large current. never extract a signal from the oscillator. 2. take it into consideration that no load such as wiring capacity is applied to the clkx2 or rtcx2 pin when inputting an external clock. figure 1-10 shows examples of oscillator having bad connection. chapter 1 introduction 55 figure 1-10. examples of oscillator with bad connection (a) connection circuit wiring is too long. gnd note2 note1 (b) there is another signal line crossing. gnd note2 note1 (c) a high varying current flows near a signal line. gnd note2 note1 (d) a current flows over the ground line of the generator circuit (the potentials of points a, b, and c change). gnd note2 note1 large current abc v dd (e) a signal is extracted. gnd note1 note2 notes 1. clkx2, rtcx2 2. clkx1, rtcx1 56 [memo] 57 chapter 2 pin functions 2.1 pin configuration x 216-pin plastic lqfp (fine-pitch) (24 u 24 mm) (top view) p pd30102gm-54-8ev gnd iow# ior# shb# busclk ledout# firclk gnd hldack# hldrq iochrdy iocs16# memcs16# zws# memw# memr# add25 add24 add23 add22 v dd gnd add21 add20 add19 add18 add17 add16 add15 add14 add13 add12 add8 v dd gnd add7 add6 add5 add4 v dd gnd rxd cts# dcd#/gpio15 dsr# dtr#/clksel0 rts#/clksel1 txd/clksel2 irdin firdin#/sel irdout# iring battinh/battint# v dd gnd ilcsense offhook mute aferst# sdi fs sdo hspsclk telcon hc0 hspmclk opd# kport0 kport1 kport2 kport3 kport4 kport5 kport6 kport7 v dd gnd v dd gnd kscan11/gpio43 kscan10/gpio42 kscan9/gpio41 kscan8/gpio40 kscan7/gpio39 kscan6/gpio38 kscan5/gpio37 kscan4/gpio36 kscan3/gpio35 kscan2/gpio34 kscan1/gpio33 kscan0/gpio32 ic (open) gnd gnd gnd v dd v dd gnd v dd p gndp cv dd clkx1 clkx2 rtcx2 rtcx1 cgnd gpio0 v dd 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 v dd agnd piugnd tpx0 tpx1 tpy0 tpy1 piuv dd adin0 adin1 adin2 audioin av dd dgnd audioout dv dd lcas# ucas# mras3#/uucas# mras2#/ulcas# mras1# mras0# romcs3# romcs2# romcs1# romcs0# rstout rd# gnd v dd wr# lcdrdy lcdcs# gpio49 dbus32/gpio48 dcts#/gpio47 drts#/gpio46 ddin/gpio45 ddout/gpio44 gpio14 gpio13 gpio12 gpio11 gpio10 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 v dd data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 gnd v dd gnd v dd data16/gpio16 data17/gpio17 data18/gpio18 data19/gpio19 data20/gpio20 data21/gpio21 data22/gpio22 data23/gpio23 data24/gpio24 data25/gpio25 data26/gpio26 data27/gpio27 data28/gpio28 data29/gpio29 data30/gpio30 data31/gpio31 gnd v dd gnd v dd add11 add10 add9 add3 add2 add1 add0 power poweron mpower rtcrst# rstsw# gnd remark # indicates actrive low. chapter 2 pin functions 58 x 224-pin plastic fgba (16 u 16 mm) p pd30102s1-54-3c a b c d e f g h j k l m n p r t u v v u t r p n m l k j h g f e d c b a 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 index mark bottom view top view chapter 2 pin functions 59 pin no. pin name pin no. pin name pin no. pin name a1 v dd c15 rts#/clksel1 h15 gnd a2 shb# c16 gnd h16 kport6 a3 busclk c17 ilcsense h17 kport4 a4 hldack# c18 aferst# h18 v dd a5 iochrdy d1 data5 j1 data20/gpio20 a6 memw# d2 data3 j2 data17/gpio17 a7 add23 d3 data6 j3 data22/gpio22 a8 v dd d4 gnd j4 data19/gpio19 a9 add18 d5 memcs16# j15 kscan9/gpio41 a10 add15 d6 add25 j16 v dd a11 add8 d7 gnd j17 gnd a12 add7 d8 add19 j18 kscan11/gpio43 a13 v dd d9 add16 k1 data23/gpio23 a14 dcd#/gpio15 d10 add14 k2 data26/gpio26 a15 txd/clksel2 d11 v dd k3 data25/gpio25 a16 irdout# d12 gnd k4 data21/gpio21 a17 iring d13 add4 k15 kscan7/gpio39 a18 v dd d14 cts# k16 kscan10/gpio42 b1 data1 d15 gnd k17 kscan5/gpio37 b2 ior# d16 gnd k18 kscan8/gpio40 b3 iow# d17 sdi l1 data27/gpio27 b4 ledout# d18 sdo l2 data31/gpio31 b5 firclk e1 data9 l3 data29/gpio29 b6 hldrq# e2 data4 l4 data24/gpio24 b7 zws# e3 data7 l15 kscan3/gpio35 b8 add24 e4 data10 l16 kscan6/gpio38 b9 add21 e15 opd# l17 kscan0/gpio32 b10 add12 e16 hspsclk l18 kscan4/gpio36 b11 add6 e17 fs m1 data30/gpio30 b12 gnd e18 hc0 m2 v dd b13 dsr# f1 data13 m3 gnd b14 irdin f2 data8 m4 data28/gpio28 b15 firdin#/sel f3 data11 m15 kscan2/gpio34 b16 battinh/battint# f4 data14 m16 ic (open) b17 offhook f15 kport3 m17 gnd b18 mute f16 hspmclk m18 kscan1/gpio33 c1 data2 f17 telcon n1 v dd c2 data0 f18 kport1 n2 add3 c3 gnd g1 v dd n3 add10 c4 gnd g2 data12 n4 gnd c5 gnd g3 data15 n15 gnd c6 iocs16# g4 gnd n16 v dd c7 memr# g15 kport7 n17 v dd p c8 add22 g16 kport2 n18 gnd c9 add20 g17 kport0 p1 add9 c10 add17 g18 kport5 p2 add0 c11 add13 h1 data16/gpio16 p3 add2 c12 add5 h2 gnd p4 add11 c13 rxd h3 data18/gpio18 p15 v dd c14 dtr#/clksel0 h4 v dd p16 gndp chapter 2 pin functions 60 pin no. pin name pin no. pin name pin no. pin name p17 clkx2 t6 av dd u13 gpio9 p18 gnd t7 lcas# u14 gpio6 r1 add1 t8 romcs2# u15 gpio5 r2 power t9 rd# u16 gpio1 r3 gnd t10 wr# u17 gpio2 r4 gnd t11 dbus32/gpio48 u18 cgnd r5 audioin t12 ddout#/gpio44 v1 v dd r6 dv dd t13 gpio11 v2 piugnd r7 mras2#/ulcas# t14 gpio8 v3 tpx0 r8 mras1# t15 gnd v4 tpy1 r9 romcs1# t16 gnd v5 adin2 r10 rstout t17 gpio0 v6 audioout r11 gnd t18 rtcx1 v7 mras3#/uucas# r12 gpio49 u1 mpower v8 mras0# r13 ddin/gpio45 u2 rtcrst# v9 romcs0# r14 gpio12 u3 agnd v10 v dd r15 gnd u4 tpx1 v11 lcdcs# r16 cv dd u5 tpy0 v12 dcts#/gpio47 r17 rtcx2 u6 adin1 v13 gpio14 r18 clkx1 u7 dgnd v14 gpio10 t1 poweron u8 ucas# v15 gpio7 t2 rstsw# u9 romcs3# v16 gpio4 t3 gnd u10 ldcrdy v17 gpio3 t4 piuv dd u11 drts#/gpio46 v18 v dd t5 adin0 u12 gpio13 chapter 2 pin functions 61 pin identification add [0:25] : address bus irdout# : irda data output adin [0:2] : general purpose input for a/d iring : input ring aferst# : afe reset kport [0:7] : key code data input agnd : gnd for a/d kscan [0:11] : key scan line audioin : audio input lcas# : lower column address strobe audioout : audio output lcdcs# : lcd chip select av dd : v dd for a/d lcdrdy : lcd ready battinh : battery inhibit ledout# : led output battint# : battery interrupt request memcs16# : memory chip select 16 busclk : system bus clock memr# : memory read cgnd : gnd for oscillator memw# : memory write clksel [0:2] : clock select mpower : main power clkx1 : clock x1 mras [0:3]# : dram row address strobe clkx2 : clock x2 mute : mute cts# : clear to send offhook : off hook cv dd : v dd for oscillator opd# : output power down data [0:31] : data bus piugnd : gnd for touch panel interface dbus32 : data bus 32 piuv dd : v dd for touch panel interface dcd# : data carrier detect power : power switch dcts# : debug serial clear to send poweron : power on state ddin : debug serial data input rd# : read ddout : debug serial data output romcs [0:3]# : rom chip select dgnd : gnd for d/a rstout : system bus reset output drts# : debug serial request to send rstsw# : reset switch dsr# : data set ready rtcrst# : real-time clock reset dtr# : data terminal ready rtcx1 : real-time clock x1 dv dd : v dd for d/a rtcx2 : real-time clock x2 firclk : fir clock rts# : request to send firdin# : fir data input rxd : receive data fs : frame synchronization sdi : hsp serial data input gnd : ground sdo : hsp serial data output gndp : ground for pll sel : irda module select gpio [0:49] : general purpose i/o shb# : system hi-byte enable hc0 : hardware control 0 telcon : telephone control hldack# : hold acknowledge tpx [0:1] : touch panel x i/o hldrq# : hold request tpy [0:1] : touch panel y i/o hspmclk : hsp codec master clock txd : transmit data hspsclk : hsp codec serial clock ucas# : upper column address strobe ic : internally connected ulcas# : lower byte of upper column ilcsense : input loop current sensing address strobe iochrdy : i/o channel ready uucas# : upper byte of upper column iocs16# : i/o chip select 16 address strobe ior# : i/o read v dd : power supply voltage iow# : i/o write v dd p: v dd for pll irdin : irda data input wr# : write zws# : zero wait state remark # indicates active low. chapter 2 pin functions 62 2.2 pin function description the functional classification of the v r 4102 pins is listed below. remark # indicates active low. figure 2-1. v r 4102 signal classification rxd txd/clksel2 rts#/clksel1 dtr#/clksel0 cts# dcd#/gpio15 dsr# firdin#/sel irdin irdout# ddout/gpio44 ddin/gpio45 drts#/gpio46 dcts#/gpio47 power rstsw# rtcrst# mpower poweron battinh/ battint# audioout audioin clkx1 clkx2 rtcx1 rtcx2 firclk ledout# v dd p gndp cv dd cgnd dv dd dgnd av dd agnd piuv dd piugnd add (0:25) data (0:15) data (16:31)/ gpio (16:31) lcdrdy lcdcs# rd# wr# romcs (0:3)# uucas#/mras3# ulcas#/mras2# mras (0:1)# ucas# lcas# busclk shb# ior# iow# memr# memw# zws# rstout memcs16# iocs16# iochrdy hldrq# hldack# dbus32/gpio48 tpx (0:1) tpy (0:1) adin (0:2) gpio (0:49) iring ilcsense offhook mute aferst# sdi fs sdo hspsclk telcon hc0 hspmclk opd# kport (0:7) kscan (0:11)/ gpio (32:43) 8 12 26 16 16 4 2 2 2 3 50 v r 4102 system bus interface dedicated v dd , gnd rs-232c interface irda interface debug serial interface initialization interface battery monitor interface keyboard interface audio interface clock interface led interface lcd interface memory interface isa bus interface touch panel/ general-purpose a/d interface hsp modem interface general-purpose i/o (including alternate-function pins and dcd# inputs) chapter 2 pin functions 63 2.2.1 system bus interface signals these signals are used when the v r 4102 is connected to a dram, rom, or lcd, or other devices in the system through the system bus. table 2-1. system bus interface signals (1/2) signal i/o description of function add[25..0] o this is a 26-bit address bus. the v r 4102 uses this to specify addresses for the dram, rom, lcd, or system bus (isa). data[15..0] i/o this is a 16-bit data bus. the v r 4102 uses this to transmit and receive data with a dram, rom, lcd, or system bus. data[31..16]/ gpio[31..16] i/o this function differs depending on how the dbus32 pin is set. chapter 2 pin functions 64 table 2-1. system bus interface signals (2/2) signal i/o description of function busclk o this is the system bus clock. it is used to output the clock that is s upplied to the controller on the system bus. its fr equency is determined by the state of the clksel2/t x d, clksel1/rts#, and clksel0/dtr pins. (see 2.2.5 rs-232-c interface signals .) shb# o this is the system bus high-byte enable signal. during system bus access, this si gnal is active when the high-order byte is valid on the data bus. ior# o this is the system bus i/o r ead signal. it is active when the v r 4102 accesses the system bus to read data from an i/o port. iow# o this is the system bus i/o write si gnal. it is active when the v r 4102 accesses the system bus to write data to an i/o port. memr# o this is the system bus memory r ead signal. it is active when the v r 4102 accesses the system bus to read data from memory. memw# o this is the system bus memory write si gnal. it is active when the v r 4102 accesses the system bus to write data to memory. zws# i this is the system bus zero wait state si gnal. set this signal as active to enable the controller on the system bus to be accessed by the v r 4102 without a wait interval. rstout o this is the system bus reset si gnal. it is active when the v r 4102 resets the system bus controller. memcs16# i this is a dynamic bus sizing request signal. set this signal as active when system bus memory accesses data in 16-bit width. (however, the dram bus memory space that is controlled by the dbus 32 pin is excepted.) iocs16# i this is a dynamic bus sizing request signal. set this signal as active when system bus i/o accesses data in 16-bit width. iochrdy i this is the system bus r eady signal. set this signal as active when the system bus controller is r eady to be accessed by the v r 4102. hldrq# i this is a hold request signal for the system bus and dram bus that is sent from an external bus master. hldack# o this is a hold acknowledge signal for the system bus and dram bus that is sent to an external bus master. dbus32/ gpio[48] i/o this function differs depending on the operating status. ? in normal operation (output) it can be used as a general-purpose output port. ? after rtc reset (input) it is a data bus width switching signal. sampling occurs when the rtcrst signal changes from low to high. 1 : use 32-bit width for data bus 0 : use 16-bit width for data bus chapter 2 pin functions 65 2.2.2 clock interface signals these signals are used to supply clocks. table 2-2 lists functions of these signals. table 2-2. clock interface signals signal i/o description of function rtcx1 i this is the 32.768-khz oscillators input pin. it is connected to one side of a crystal resonator. rtcx2 o this is the 32.768-khz oscillators output pin. it is connected to one side of a crystal resonator. clkx1 i this is the 18.432-mhz oscillators input pin. it is connected to one side of a crystal resonator. clkx2 o this is the 18.432-mhz oscillators output pin. it is connected to one side of a crystal resonator. firclk i this the 48-mhz clock input pin. fix this at high level when fir is not used. 2.2.3 battery monitor interface signals these signals indicate when an external agent is able to provide enough power for system operations. table 2-3 describes the functions of these signals. table 2-3. battery monitor interface signals signal i/o description of function battinh/ battint# i this function differs depending on how the mpower pin is set. chapter 2 pin functions 66 2.2.4 initialization interface signals these signals are used when an external agent initializes the processor operation parameters. table 2-4 describes the functions of these signals. table 2-4 initialization interface signals signal i/o description of function mpower o this signal is used to turn on the main power source. the v r 4102 asserts the signal at this pin to turn on the power source for the external dc/dc converter. poweron o this signal indicates when the v r 4102 is ready to operate. it becomes active when a power-on factor is detected and becomes inactive when the battinh/battint# signal check operation is completed. power i this signal indicates that the power on switch has been pressed. when the power on switch has been pressed, an external agent must assert the signal at this pin. rstsw# i this signal indicates that the reset switch has been pressed. when the reset switch has been pressed, an external agent must assert the signal at this pin. rtcrst# i this signal resets the rtc. when power is first supplied to a device, the external agent must assert the signal at this pin for about 600 ms. chapter 2 pin functions 67 2.2.5 rs-232-c interface signals these signals control data transmission and reception between the v r 4102 and an rs-232-c controller. table 2- 5 describes the functions of these signals. table 2-5. rs-232-c interface signals signal i/o description of function rxd i this is a receive data signal. it is used when the rs-232-c controller sends serial data to the v r 4102. cts# i this is the transmit enable (clear-to-send) signal. this signal is asserted when the rs-232-c controller is ready to receive transmission of serial data. dcd#/ gpio[15] i this is a carrier detection signal. this signal is asserted when valid serial data is being received. it is also used when detecting a power-on factor for the v r 4102. when this pin is not used for dcd# signal, this pin can be used as an interrupt detection function for the giu unit. dsr# i this is the data set ready signal. assert this signal to set up transmission and reception of serial data between the rs-232c controller and the v r 4102. txd/ clksel[2], rts#/ clksel[1], dtr#/ clksel[0] i/o this function differs depending on the operating status. ? in normal operation (output) txd signal (output): this is a transmit data signal. it is used when the v r 4102 sends serial data to the rs-232c controller. rts# signal (output): this is a transmit request signal. this signal is asserted when the v r 4102 is ready to receive serial data from the rs-232c controller. dtr# signal (output): this is a terminal equipment ready signal. this signal is asserted when the v r 4102 is ready to transmit or receive serial data. ? after rtc reset (input) these signals are used to set the cpu core operation and busclk frequency (clksel[2..0]: input). sampling occurs when the rtcrst signal changes from low to high. clksel[2..0] cpu core frequency busclk frequency 111 rfu rfu 110 rfu rfu 101 53.6 mhz 6.700 mhz 100 49.2 mhz 6.075 mhz 011 45.4 mhz 5.675 mhz 010 42.1 mhz 5.275 mhz 001 36.9 mhz 9.200 mhz 000 32.8 mhz 8.200 mhz caution some of these settings of frequency may not be able to select in the future. chapter 2 pin functions 68 2.2.6 irda interface signals these signals are used to control data transmission and reception between the v r 4102 and an irda controller. table 2-6 describes the functions of these signals. table 2-6. irda interface signals signal i/o description of function irdin i this is the irda serial data input signal. it is used when the v r 4102 sends serial data to the irda controller, for both fir and sir. if the irda controller used is an hp product, however, this signal should be used for only sir. firdin#/sel i/o this function differs according to the irda controller used (for how to switch a controller, refer to 24.2.13 ). x hps controller firdin#: it is a fir receive data input signal. x temics controller sel: it is an output port for external fir/sir switching. x sharps controller use is prohibited. irdout# o this is the irda serial data output signal for both sir and fir. it is used when the irda controller sends serial data to the v r 4102. 2.2.7 debug serial interface signals these signals are used to control data transmission and reception between the v r 4102 and a external debug serial controller. table 2-7 describes the functions of these signals. table 2-7. debug serial interface signals signal i/o description of function ddout/ gpio[44] o this is the debug serial data output signal. it is used when an external debug serial data controller sends serial data to the v r 4102. when this pin is not used for the ddout signal, it can be used as a general-purpose output port. ddin/ gpio[45] i/o this is the debug serial data input signal. it is used when the v r 4102 sends serial data to an external debug serial controller. when this pin is not used for the ddin signal, it can be used as a general-purpose output port. drts#/ gpio[46] o this is a transmission request signal. the v r 4102 asserts this signal before sending serial data. when this pin is not used for the drts# signal, it can be used as a general-purpose output port. dcts#/ gpio[47] i/o this is a transmit acknowledge signal. the v r 4102 asserts this signal when it is ready to receive transmitted serial data. when this pin is not used for the dcts# signal, it can be used as a general-purpose output port. chapter 2 pin functions 69 2.2.8 keyboard interface signals these signals are used to control a keyboard circuit to the v r 4102. table 2-8 describes the functions of these signals. table 2-8. keyboard interface signals signal i/o description of function kport[7..0] i this is a keyboard scan data input signal. it is used to scan for pressed keys on the keyboard. kscan[11..0]/ gpio[43..32] o these signal are used as keyboard scan data output signals and a general-purpose output port. the scan line is set as active when scanning for pressed keys on the keyboard. pins that are not used for the key scan operation can be used as a general-purpose output port. 2.2.9 audio interface signals this signal is used to input/output audio signals. table 2-9 describes the functions of this signal. table 2-9. audio interface signals signal i/o description of function audioout o this is an audio output signal. analog signals that have been converted via the on-chip 10-bit d/a converter are output. audioin i this pin is the audio input pin. 2.2.10 touch panel/general purpose a/d interface signals these are the signals to the on-chip a/d converter of the v r 4102. four of these signals are used for a touch panel, one is used for audio input, and the remaining three are used as general-purpose pins. table 2-10 describes the functions of these signals. table 2-10. touch panel/general purpose a/d interface signals signal i/o description of function tpx[1..0] i/o this is an i/o signal that is used for the touch panel. it uses the voltage applied to the x coordinate and the voltage input to the y coordinate to detect which coordinates on the touch panel are being pressed. tpy[1..0] i/o this is an i/o signal that is used for the touch panel. it uses the voltage applied to the y coordinate and the voltage input to the x coordinate to detect which coordinates on the touch panel are being pressed. adin[2..0] i this is a general-purpose a/d input signal. chapter 2 pin functions 70 2.2.11 general-purpose i/o signals these are general-purpose i/o pins of the v r 4102. ordinary, 33 of the 49 gpio pins are used as alternate- function pins. table 2-11 describes the functions of these signals. table 2-11. general-purpose i/o signals signal i/o description of function gpio[3..0] i/o these are maskable power-on factors. after start-up, they are used as ordinary gpio pins. gpio[8..4] i/o these are ordinary gpio pins. gpio[12..9] i/o these are maskable power-on factors. after start-up, they are used as ordinary gpio pins. gpio[14..13] i/o these are ordinary gpio pins. data[31..16]/ gpio[31..16] i/o see 2.2.1 system bus interface signals . kscan[11..0]/ gpio[43..32] o see 2.2.8 keyboard interface signals . ddout/ gpio[44] o see 2.2.7 debug serial interface signals . ddin/gpio[45] i/o see 2.2.7 debug serial interface signals . drts#/ gpio[46] o see 2.2.7 debug serial interface signals . dcts#/ gpio[47] i/o see 2.2.7 debug serial interface signals . dbus32/ gpio[48] i/o see 2.2.1 system bus interface signals . gpio[49] i/o this function differs depending on the operating status. ? in normal operation it can be used as a general-purpose output port. ? after rtc reset input state. input low level. sampling occurs when the rtcrst signal changes from low to high. chapter 2 pin functions 71 2.2.12 hsp modem interface signals table 2-12. hsp modem interface signals signal i/o function iring i ring signal detect signal. this pin becomes active when the ring signal is detected. ilcsense i handset detect signal. offhook o on-hook relay control signal. mute o modem speaker mute control signal. aferst# o codec reset signal. sdi i serial input signal from codec. fs i frame synchronization signal from codec. sdo o serial output signal to codec. hspsclk i operation clock input of modem interface block for codec. telcon o handset relay control signal. hc0 o codec control signal. hspmclk o clock output to codec. opd# o use this pin for controlling power of codec and daa. this signal is set as active when to set power supply to them on. 2.2.13 led interface signal table 2-13. led interface signal signal i/o description of function ledout# o this is an output signal for lighting leds. chapter 2 pin functions 72 2.2.14 dedicated v dd and gnd signals table 2-14. dedicated v dd and gnd signals signal description of function v dd p this is the dedicated v dd for the pll. gndp this is the dedicated gnd for the pll. cv dd this is the dedicated v dd for the internal oscillator. cgnd this is the dedicated gnd for the internal oscillator. dv dd this is the dedicated v dd for the d/a converter. the voltage applied to this pin becomes the maximum value for audioouts analog output. dgnd this is the dedicated gnd for the d/a converter. the voltage applied to this pin becomes the minimum value for audioouts analog output. av dd this is the dedicated v dd for the a/d converter. the voltage applied to this pin becomes the maximum voltage value for the a/d interface signals. agnd this is the dedicated gnd for the a/d converter. the voltage applied to this pin becomes the minimum voltage value detectable by the a/d interface signals. piuv dd this is the dedicated v dd for the touch panel interface. piugnd this is the dedicated gnd for the touch panel interface. chapter 2 pin functions 73 2.3 pin status upon specific states 2.3.1 pin status upon reset table 2-15. status of pins upon reset (1/3) signal when reset by rtcrst when reset by deadmans switch or rstsw during suspend mode during hibernate mode or when shut down by hal timer during bus hold add[25..0] 0 0 note 1 0hi-z data[15..0] 0 0 note 1 0hi-z data[31..16]/ gpio[31..16] 0/ hi-z 0/ hi-z note 1 0/ hi-z hi-z/ note 1 lcdcs# hi-z 1 1 hi-z 1 rd# hi-z 1 1 hi-z hi-z wr# hi-z 1 1 hi-z hi-z lcdrdy eeeee romcs[3..0]# hi-z 1 1 hi-z 1 uucas#/mras[3] # 1 note 3 00hi-z ulcas#/mras[2]# 1 note 3 00hi-z mras[1..0]# 1 note 3 00hi-z ucas# 1 note 3 00hi-z lcas# 1 note 3 00hi-z busclk 0 0 0 0 note 2 shb# hi-z 1 1 hi-z hi-z ior# hi-z 1 1 hi-z hi-z iow# hi-z 1 1 hi-z hi-z memr# hi-z 1 1 hi-z hi-z memw# hi-z 1 1 hi-z hi-z zws# eeeee rstout hi-z 1 0 hi-z note 4 iocs16# eeeee memcs16# eeeee iochrdy eeeee notes 1. the state at the previous fullspeed mode is retained. 2. bus hold from suspend mode: outputs the low-level signal bus hold from fullspeed mode or standby mode: outputs clocks. 3. reset by rstsw# signal: this pin outputs the low-level signal (self refresh) reset by deadmans switch: this pin outputs the high-level signal 4. normal operations are performed. remark 0: outputs low level, 1: outputs high level, hi-z: high-impedance chapter 2 pin functions 74 table 2-15. status of pins upon reset (2/3) signal when reset by rtcrst when reset by deadmans switch or rstsw during suspend mode during hibernate mode or when shut down by hal timer during bus hold hldrq# eeeee hldack# hi-z 1 note 1 hi-z note 1 rtcx1 eeeee rtcx2 eeeee clkx1 eeeee clkx2 eeeee firclk eeeee battinh/ battint# eeeee mpower01101 poweron00000 power eeeee rstsw# eeeee rtcrst# eeeee rxd eeeee txd/clksel[2] hi-z 1 1 1 note 1 rts#/clksel[1] hi-z 1 1 1 note 1 cts# eeeee dcd#/gpio[15] eeeee dtr#/clksel[0] hi-z 1 1 1 note 1 dsr# eeeee irdin eeeee irdout# 0 0 0 0 note 1 firdin#/sel hi-z hi-z note 2 hi-z note 2 ddin/ gpio[45] note3 hi-z/ hi-z hi-z/ hi-z hi-z/ note 2 hi-z/ hi-z hi-z/ note 2 ddout/ gpio[44] note3 11111 drts#/ gpio[46] note3 11111 dcts#/ gpio[47] note3 hi-z/ hi-z hi-z/ hi-z hi-z/ note 2 hi-z/ hi-z hi-z/ note 2 notes 1. normal operations are performed. 2. the state at the previous fullspeed mode is retained. 3. this pin can be switched by software between function-pin and output-port uses. remark 0: outputs low level, 1: outputs high level, hi-z: high-impedance chapter 2 pin functions 75 table 2-15. status of pins upon reset (3/3) signal when reset by rtcrst when reset by deadmans switch or rstsw during suspend mode during hibernate mode or when shut down by hal timer during bus hold kport[7..0] eeeee kscan[11..0]/ gpio[43..32] note 1 hi-z hi-z note 2 hi-z note 3 audioout 0 0 note 2 0 note 3 tpx[1..0] hi-z 1 note 2 1 note 3 tpy[1..0] hi-z hi-z note 2 hi-z note 3 adin[2..0] eeeee audioin eeeee gpio[14..0] hi-z hi-z note 2 hi-z note 3 iring eeeee ilcsense eeeee offhook note 4 hi-z hi-z note 2 hi-z note 2 mute note 4 hi-z hi-z note 2 hi-z note 2 aferst# note 4 00 note 2 0 note 2 sdi eeeee fs eeeee sdo 0 0 note 2 0 note 2 hspsclk eeeee telcon note 4 hi-z hi-z note 2 hi-z note 2 hc0 note 4 00 note 2 0 note 2 hspmclk note 4 00 note 2 0 note 2 opd# 0 0 note 2 0 note 2 ledout# 1 note 3 note 3 note 3 note 3 dbus32/ gpio[48] note 5 hi-z hi-z note 2 hi-z note 2 gpio[49] note 5 hi-z hi-z note 2 hi-z note 2 notes 1. this pin can be switched by software between function-pin and output-port uses. 2. the state at the previous fullspeed mode is retained. 3. normal operations are performed. 4. be sure to set the bsc bit (di) of the hspint register (0x0c00 0020) to 1 during initialization. 5. after rtc reset is canceled, this signal functions as an output port. remark 0: outputs low level, 1: outputs high level, hi-z: high-impedance chapter 2 pin functions 76 2.3.2 connection of unused pins and pin i/o circuits table 2-16. connection of unused pins and pin i/o circuit type (1/3) signal internal processing external processing drive capability i/o circuit type add[25..0] ee 120 pf a data[15..0] ee 40 pf a data[31..16]/ gpio[31..16] ee / pull up pull down 40 pf a lcdcs# ee 40 pf a rd# e note 1 120 pf a wr# e note 1 120 pf a lcdrdy e pull up e a romcs[3..0]# ee 40 pf a uucas#/mras[3]# e note 1 40 pf a ulcas#/mras[2]# e note 1 40 pf a mras[1..0]# e note 1 40 pf a ucas# e note 1 40 pf a lcas# e note 1 40 pf a busclk ee 40 pf a shb# e note 1 40 pf a ior# e note 1 40 pf a iow# e note 1 40 pf a memr# e note 1 40 pf a memw# e note 1 40 pf a zws# note 2 pull up e a rstout e pull up 40 pf a iocs16# note 2 pull up e a memcs16# note 2 pull up e a iochrdy note 2 pull up e a notes 1. pull up when the bus hold function is used. 2. intermediate-level input is enabled when the mpower pin is set for low-level output. chapter 2 pin functions 77 table 2-16. connection of unused pins and pin i/o circuit type (2/3) signal internal processing external processing drive capability i/o circuit type hldrq# note 1 note 2 e a hldack# ee 40 pf a rtcx1 e resonator ee rtcx2 e resonator ee clkx1 e resonator ee clkx2 e resonator ee firclk e note 3 e a battinh/ battint# schmitt ee b mpower ee 40 pf a poweron ee 40 pf a power schmitt ee b rstsw# schmitt ee b rtcrst# schmitt ee b rxd eee a txd/clksel[2] e pull up pull down 40 pf a rts#/clksel[1] e pull up pull down 40 pf a cts# eee a dcd#/gpio[15] e pull up e a dtr#/clksel[0] e pull up pull down 40 pf a dsr# eee a irdin e pull up e a irdout# ee 40 pf a firdin#/sel e pull up pull down 40 pf a ddin/ gpio[45] note 4 ee 40 pf a ddout/ gpio[44] note 4 ee 40 pf a drts#/ gpio[46] note 4 ee 40 pf a dcts#/ gpio[47] note 4 ee 40 pf a notes 1. intermediate-level input is enabled when the mpower pin is set for low-level output. 2. when the bus hold function is used : pull up. when the bus hold function is not used : connect to v dd . 3. when fir unit is used : attach an oscillator. when fir unit is not used : connect to v dd . 4. this pin can be switched by software between function-pin and output-port uses. chapter 2 pin functions 78 table 2-16. connection of unused pins and pin i/o circuit type (3/3) signal internal processing external processing drive capability i/o circuit type kport[7..0] schmitt, pull down ee f kscan[11..0]/ gpio[43..32] note 1 ee 40 pf a audioout e note 2 e g tpx[1..0] ee 120 pf or more c tpy[1] ee 120 pf or more d tpy[0] ee 120 pf or more c adin[2..0] eee e audioin eee e gpio[14..13] e pull up pull down 40 pf a gpio[12..9] schmitt pull up pull down 40 pf b gpio[8..5] e pull up pull down 40 pf a gpio[4..0] schmitt pull up pull down 40 pf b iring schmitt pull down e b ilcsense e pull down e a offhook note 3 ee 40 pf a mute note 3 ee 40 pf a aferst# note 3 ee 40 pf a sdi e pull up pull down e a fs e pull up pull down e a sdo ee 40 pf a hspsclk eee a telcon note 3 ee 40 pf a hc0 note 3 ee 40 pf a hspmclk note 3 ee 40 pf a opd# ee 40 pf a ledout# ee 40 pf a dbus32/ gpio[48] note 4 e pull up pull down 40 pf a gpio[49] note 4 e pull down e a notes 1. this pin can be switched by software between function-pin and output-port uses. 2. connect an operation amplifier which has high-impedance input characteristics, since the output level of audioout pin varies according to the external impedance. 3. be sure to set bsc bit (di) of the hspint register (0x0c00 0020) to 1 during initialization. 4. after rtc reset is canceled, this signal functions as an output port. chapter 2 pin functions 79 2.3.3 pin i/o circuits v dd input enable output disable n-ch p-ch data in/out type a output disable vref n-ch n-ch v dd in/out p-ch p-ch data input enable n-ch type d p-ch n-ch vref in type e output disable n-ch v dd in/out p-ch data input enable type b output disable vref n-ch n-ch v dd in/out p-ch p-ch data type c open drain pulldown enable output disable n-ch p-ch data v dd in/out n-ch input enable type f out analog output voltage type g 80 [memo] 81 chapter 3 cpu instruction set summary this chapter is an overview of the central processing unit (cpu) instruction set; refer to the chapter 27 for detailed descriptions of individual cpu instructions. 3.1 cpu instruction formats each cpu instruction consists of a single 32-bit word, aligned on a word boundary. there are three instruction formats - immediate (i-type), jump (j-type), and register (r-type) - as shown in figure 3-1. the use of a small number of instruction formats simplifies instruction decoding, allowing the compiler to synthesize more complicated and less frequently used instruction and addressing modes from these three formats as needed. figure 3-1. cpu instruction formats i-type (immediate) op 0 15 16 20 21 25 26 31 j-type (jump) op target 0 25 26 31 r-type (register) immediate: func: sa: rd: target: 6-bit function field 5-bit shift amount 5-bit destination register specifier 26-bit unconditional branch target address 16-bit immediate value, branch displacement or address displacement 5-bit target (source/destination) register or branch condition 6-bit operation code 5-bit source register specifier rt: rs: op: op 0 15 16 20 21 25 26 31 5 6 10 11 rs rt immediate rs rt rd sa func (1) support of the mips isa the v r 4102 does not support a multiprocessor operating environment. thus the synchronization support instructions defined in the mips ii and mips iii isa - the load linked and store conditional instructions - cause reserved instruction exception. the load/link (ll) bit is eliminated. note that the sync instruction is handled as a nop instruction since all load/store instructions in this processor are executed in program order. chapter 3 cpu instruction set summary 82 3.2 instruction classes 3.2.1 load and store instructions load and store are immediate (i-type) instructions that move data between memory and the general-purpose registers. the only addressing mode that load and store instructions directly support is base register plus 16-bit signed immediate offset. (1) scheduling a load delay slot a load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction. the instruction slot immediately following this delayed load instruction is referred to as the load delay slot. in the v r 4000 series, a load instruction can be followed directly by an instruction that accesses a register that is loaded by the load instruction. in this case, however, an interlock occurs for a necessary number of cycles. any instruction can follow a load instruction, but the load delay slot should be scheduled appropriately for both performance and compatibility with the v r 3000 tm series microprocessors. for detail, see chapter 4 v r 4102 pipeline . (2) store delay slot when a store instruction is writing data to a cache, the data cache is kept busy at the dc and wb stages. if an instruction (such as load) that follows directly the store instruction accesses the data cache in the dc stage, a hardware-driven interlock occurs. to overcome this problem, the store delay slot should be scheduled. table 3-1. number of delay slot cycles necessary for load and store instructions instruction necessary number of pcycles load 1 store 1 (3) defining access types access type indicates the size of a v r 4102 processor data item to be loaded or stored, set by the load or store instruction opcode. access types and accessed byte are shown in table 3-2 . regardless of access type or byte ordering (endianness), the address given specifies the low-order byte in the addressed field. for a little-endian configuration, the low-order byte is the least-significant byte. the access type, together with the three low-order bits of the address, define the bytes accessed within the addressed doubleword (shown in table 3-2). only the combinations shown in table 3-2 are permissible; other combinations cause address error exceptions. tables 3-3 and 3-4 list the isa-defined load/store instructions and expand-isa instructions, respectively. chapter 3 cpu instruction set summary 83 figure 3-2. byte specification related to load and store instructions accessed byte low-order address bit (little endian) access type (value) 21063 0 doubleword (7) 0 0 0 7 6 5 4 3 2 1 0 7-byte (6) 000 6543210 0017654321 6-byte (5) 000 543210 010765432 5-byte (4) 0 0 0 4 3 2 1 0 01176543 word (3) 0 0 0 3 2 1 0 1007654 triple byte (2) 0 0 0 2 1 0 001 321 100 654 101765 halfword (1) 0 0 0 1 0 010 32 100 54 11076 byte (0) 0 0 0 0 001 1 010 2 011 3 100 4 101 5 110 6 1117 chapter 3 cpu instruction set summary 84 table 3-2. load/store instruction instruction format and description load byte lb rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the bytes of the memory location specified by the address are sign extended and loaded into register rt. load byte unsigned lbu rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the bytes of the memory location specified by the address are zero extended and loaded into register rt. load halfword lh rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the halfword of the memory location specified by the address is sign extended and loaded to register rt. load halfword unsigned lhu rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the halfword of the memory location specified by the address is zero extended and loaded to register rt. load word lw rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the word of the memory location specified by the address is sign extended and loaded to register rt. in the 64-bit mode, it is further sign extended to 64 bits. load word left lwl rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. shifts to the left the word whose address is specified so that the address-specified byte is at the left- most position of the word. the result of the shift operation is merged with the contents of register rt and loaded to register rt. in the 64-bit mode, it is further sign extended to 64 bits. load word right lwr rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. shifts to the right the word whose address is specified so that the address-specified byte is at the right- most position of the word. the result of the shift operation is merged with the contents of register rt and loaded to register rt. in the 64-bit mode, it is further sign extended to 64 bits. store byte sb rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the least significant byte of register rt is stored to the memory location specified by the address. store halfword sh rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the least significant halfword of register rt is stored to the memory location specified by the address. store word sw rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the lower word of register rt is stored to the memory location specified by the address. store word left swl rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. shifts to the right the contents of register rt so that the left-most byte of the word is in the position of the address-specified byte. the result is stored to the lower word in memory. store word right swr rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. shifts to the left the contents of register rt so that the right-most byte of the word is in the position of the address-specified byte. the result is stored to the upper word in memory. op b ase rt offset chapter 3 cpu instruction set summary 85 table 3-3. load/store instruction (extended isa) instruction format and description load doubleword ld rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the doubleword of the memory location specified by the address are loaded into register rt. load doubleword left ldl rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. shifts to the left the double word whose address is specified so that the address-specified byte is at the left-most position of the double word. the result of the shift operation is merged with the contents of register rt and loaded to register rt. load doubleword right ldr rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. shifts to the right the double word whose address is specified so that the address-specified byte is at the right-most position of the double word. the result of the shift operation is merged with the contents of register rt and loaded to register rt. load word unsigned lwu rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the word of the memory location specified by the address are zero extended and loaded into register rt store doubleword sd rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. the contents of register rt are stored to the memory location specified by the address. store doubleword left sdl rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. shifts to the right the contents of register rt so that the left-most byte of the double word is in the position of the address-specified byte. the result is stored to the lower doubleword in memory. store doubleword right sdr rt, offset (base) the offset is sign extended and then added to the contents of the register base to form the virtual address. shifts to the left the contents of register rt so that the right-most byte of the double word is in the position of the address-specified byte. the result is stored to the upper doubleword in memory. op b ase rt offset chapter 3 cpu instruction set summary 86 3.2.2 computational instructions computational instructions perform arithmetic, logical, and shift operations on values in registers. computational instructions can be either in register (r-type) format, in which both operands are registers, or in immediate (i-type) format, in which one operand is a 16-bit immediate. computational instructions are classified as: (1) alu immediate instructions (tables 3-4 and 3-5) (2) three-operand type instructions (tables 3-6 and 3-7) (3) shift instructions (tables 3-8 and 3-9) (4) multiply/divide instructions (table 3-10 and 3-11) to maintain data compatibility between the 64- and 32-bit modes, it is necessary to sign-extend 32-bit operands correctly. if the sign extension is not correct, the 32-bit operation result is meaningless. table 3-4. alu immediate instruction instruction format and description add immediate addi rt, rs, immediate the 16-bit immediate is sign extended and then added to the contents of register rs to form a 32-bit result. the result is stored into register rt. in the 64-bit mode, the operand must be sign extended. an exception occurs on the generation of 2s complement overflow. add immediate unsigned addiu rt, rs, immediate the 16-bit immediate is sign extended and then added to the contents of register rs to form a 32-bit result. the result is stored into register rt. in the 64-bit mode, the operand must be sign extended. no exception occurs on the generation of integer overflow. set on less than immediate slti rt, rs, immediate the 16-bit immediate is sign extended and then compared to the contents of register rt treating both operands as signed integers. if rs is less than the immediate, the result is set to 1; otherwise, the result is set to 0. the result is stored to register rt. set on less than immediate unsigned sltiu rt, rs, immediate the 16-bit immediate is sign extended and then compared to the contents of register rt treating both operands as unsigned integers. if rs is less than the immediate, the result is set to 1; otherwise, the result is set to 0. the result is stored to register rt. and immediate andi rt, rs, immediate the 16-bit immediate is zero extended and then anded with the contents of the register. the result is stored into register rt. or immediate ori rt, rs, immediate the 16-bit immediate is zero extended and then ored with the contents of the register. the result is stored into register rt. exclusive or immediate xori rt, rs, immediate the 16-bit immediate is zero extended and then ex-ored with the contents of the register. the result is stored into register rt. load upper immediate lui rt, immediate the 16-bit immediate is shifted left by 16 bits to set the lower 16 bits of word to 0. the result is stored into register rt. in the 64-bit mode, the operand must be sign extended. op rs rt immediate chapter 3 cpu instruction set summary 87 table 3-5. alu immediate instruction (extended isa) instruction format and description doubleword add immediate daddi rt, rs, immediate the 16-bit immediate is sign extended to 64 bits and then added to the contents of register rs to form a 64-bit result. the result is stored into register rt. an exception occurs on the generation of integer overflow. doubleword add immediate unsigned daddiu rt, rs, immediate the 16-bit immediate is sign extended to 64 bits and then added to the contents of register rs to form a 64-bit result. the result is stored into register rt. no exception occurs on the generation of overflow. table 3-6. three operand type instruction instruction format and description add add rd, rs, rt the contents of registers rs and rt are added together to form a 32-bit result. the result is stored into register rd. in the 64-bit mode, the operand must be sign extended. an exception occurs on the generation of integer overflow. add unsigned addu rd, rs, rt the contents of registers rs and rt are added together to form a 32-bit result. the result is stored into register rd. in the 64-bit mode, the operand must be sign extended. no exception occurs on the generation of integer overflow. subtract sub rd, rs, rt the contents of register rt are subtracted from the contents of register rs. the 32-bit result is stored into register rd. in the 64-bit mode, the operand must be sign extended. an exception occurs on the generation of integer overflow. subtract unsigned subu rd, rs, rt the contents of register rt are subtracted from the contents of register rs. the 32-bit result is stored into register rd. in the 64-bit mode, the operand must be sign extended. no exception occurs on the generation of integer overflow. set on less than slt rd, rs, rt the contents of registers rs and rt are compared, treating both operands as signed integers. if the contents of register rs is less than that of register rt, the result is set to 1; otherwise, the result is set to 0. the result is stored to register rd. set on less than unsigned sltu rd, rs, rt the contents of registers rs and rt are compared treating both operands as unsigned integers. if the contents of register rs is less than that of register rt, the result is set to 1; otherwise, the result is set to 0. the result is stored to register rd. and and rd, rt, rs the contents of register rs are logical anded with that of general register rt bit-wise. the result is stored to register rd. or or rd, rt, rs the contents of register rs are logical ored with that of general register rt bit-wise. the result is stored to register rd. exclusive or xor rd, rt, rs the contents of register rs are logical ex-ored with that of general register rt bit-wise. the result is stored to register rd. nor nor rd, rt, rs the contents of register rs are logical nored with that of general register rt bit-wise. the result is stored to register rd. op rs rt immediate op rs rt funct r d sa chapter 3 cpu instruction set summary 88 table 3-7. three operand type instruction (extended isa) instruction format and description doubleword add dadd rd, rt, rs the contents of register rs are added to that of register rt. the 64-bit result is stored into register rd. an exception occurs on the generation of integer overflow. doubleword add unsigned daddu rd, rt, rs the contents of register rs are added to that of register rt. the 64-bit result is stored into register rd. no exception occurs on the generation of integer overflow. doubleword subtract dsub rd, rt, rs the contents of register rt are subtracted from that of register rs. the 64-bit result is stored into register rd. an exception occurs on the generation of integer overflow. doubleword subtract unsigned dsubu rd, rt, rs the contents of register rt are subtracted from that of register rs. the 64-bit result is stored into register rd. no exception occurs on the generation of integer overflow. table 3-8. shift instruction instruction format and description shift left logical sll rd, rs, sa the contents of register rt are shifted left by sa bits and zeros are inserted into the emptied lower bits. the 32-bit result is stored into register rd. in the 64-bit mode, the operand must be sign extended. shift right logical srl rd, rs, sa the contents of register rt are shifted right by sa bits and zeros are inserted into the emptied higher bits. the 32-bit result is stored into register rd. in the 64-bit mode, the operand must be sign extended. shift right arithmetic sra rd, rt, sa the contents of register rt are shifted right by sa bits and the emptied higher bits are sign extended. the 32-bit result is stored into register rd. in the 64-bit mode, the operand must be sign extended. shift left logical variable sllv rd, rt, rs the contents of register rt are shifted left and zeros are inserted into the emptied lower bits. the lower five bits of register rs specify the shift count. the 32-bit result is stored into register rd. in the 64-bit mode, the operand must be sign extended. shift right logical variable srlv rd, rt, rs the contents of register rt are shifted right and zeros are inserted into the emptied higher bits. the lower five bits of register rs specify the shift count. the 32-bit result is stored into register rd. in the 64- bit mode, the operand must be sign extended. shift right arithmetic variable srav rd, rt, rs the contents of register rt are shifted right and the emptied higher bits are sign extended. the lower five bits of register rs specify the shift count. the 32-bit result is stored into register rd. in the 64-bit mode, the operand must be sign extended. op rs rt funct r d sa op rs rt funct r d sa chapter 3 cpu instruction set summary 89 table 3-9. shift instruction (extended isa) instruction format and description doubleword shift left logical dsll rd, rs, sa the contents of register rt are shifted left by sa bits and zeros are inserted into the emptied lower bits. the 64-bit result is stored into register rd. doubleword shift right logical dsrl rd, rs, sa the contents of register rt are shifted right by sa bits and zeros are inserted into the emptied higher bits. the 64-bit result is stored into register rd. doubleword shift right arithmetic dsra rd, rt, sa the contents of register rt are shifted right by sa bits and the emptied higher bits are sign extended. the 64-bit result is stored into register rd. doubleword shift left logical variable dsllv rd, rt, rs the contents of register rt are shifted left and zeros are inserted into the emptied lower bits. the lower six bits of register rs specify the shift count. the 64-bit result is stored into register rd. doubleword shift right logical variable dsrlv rd, rt, rs the contents of register rt are shifted right and zeros are inserted into the emptied higher bits. the lower six bits of register rs specify the shift count. the 64-bit result is stored into register rd. doubleword shift right arithmetic variable dsrav rd, rt, rs the contents of register rt are shifted right and the emptied higher bits are sign extended. the lower six bits of register rs specify the shift count. the 64-bit result is stored into register rd. doubleword shift left logical + 32 dsll32 rd, rt, sa the contents of register rt are shifted left by 32 + sa bits and zeros are inserted into the emptied lower bits. the 64-bit result is stored into register rd. doubleword shift right logical + 32 dsrl32 rd, rt, sa the contents of register rt are shifted right by 32 + sa bits and zeros are inserted into the emptied higher bits. the 64-bit result is stored into register rd. doubleword shift right arithmetic + 32 dsra32 rd, rt, sa the contents of register rt are shifted right by 32 + sa bits and the emptied higher bits are sign extended. the 64-bit result is stored into register rd. op rs rt funct r d sa chapter 3 cpu instruction set summary 90 table 3-10. multiply/divide instructions instruction format and description multiply mult rs, rt the contents of registers rt and rs are multiplied, treating both operands as 32-bit signed integers. the 64-bit result is stored into special registers hi and lo. in the 64-bit mode, the operand must be sign extended. multiply unsigned multu rs, rt the contents of registers rt and rs are multiplied, treating both operands as 32-bit unsigned integers. the 64-bit result is stored into special registers hi and lo. in the 64-bit mode, the operand must be sign extended. divide div rs, rt the contents of register rs are divided by that of register rt, treating both operands as 32-bit signed integers. the 32-bit quotient is stored into special register lo, and the 32-bit remainder is stored into special register hi. in the 64-bit mode, the operand must be sign extended. divide unsigned divu rs, rt the contents of register rs are divided by that of register rt, treating both operands as 32-bit unsigned integers. the 32-bit quotient is stored into special register lo, and the 32-bit remainder is stored into special register hi. in the 64-bit mode, the operand must be sign extended. move from hi mfhi rd the contents of special register hi are loaded into register rd. move from lo mflo rd the contents of special register lo are loaded into register rd. move to hi mthi rs the contents of register rs are loaded into special register hi. move to lo mtlo rs the contents of register rs are loaded into special register lo. table 3-11. multiply/divide instructions (extended isa) (1/2) instruction format and description doubleword multiply dmult rs, rt the contents of registers rt and rs are multiplied, treating both operands as signed integers. the 128- bit result is stored into special registers hi and lo. doubleword multiply unsigned dmultu rs, rt the contents of registers rt and rs are multiplied, treating both operands as unsigned integers. the 128-bit result is stored into special registers hi and lo. doubleword divide ddiv rs, rt the contents of register rs are divided by that of register rt, treating both operands as signed integers. the 64-bit quotient is stored into special register lo, and the 64-bit remainder is stored into special register hi. doubleword divide unsigned ddivu rs, rt the contents of register rs are divided by that of register rt, treating both operands as unsigned integers. the 64-bit quotient is stored into special register lo, and the 64-bit remainder is stored into special register hi. op rs rt funct r d sa op rs rt funct r d sa chapter 3 cpu instruction set summary 91 table 3-11. multiply/divide instructions (extended isa) (2/2) instruction format and description multiply and add 16- bit integer madd16 rs, rt the contents of registers rt and rs are multiplied, treating both operands as 16-bit signed integers (by sign extending to 64 bits). the result is added to the combined value of special registers hi and lo. the 64-bit result is stored into special registers hi and lo. doubleword multiply and add 16-bit integer dmadd16 rs, rt the contents of registers rt and rs are multiplied, treating both operands as 16-bit signed integers (by sign extending to 64 bits). the result is added to value of special register lo. the 64-bit result is stored into special register lo. mfhi and mflo instructions after a multiply or divide instruction generate interlocks to delay execution of the next instruction, inhibiting the result from being read until the multiply or divide instruction completes. table 3-12 gives the number of processor cycles (pcycles) required to resolve interlock or stall between various multiply or divide instructions and a subsequent mfhi or mflo instruction. table 3-12. number of stall cycles in multiply and divide instructions instruction number of instruction cycles mult 1 multu 1 div 35 divu 35 dmult 4 dmultu 4 ddiv 67 ddivu 67 madd16 1 dmadd16 1 op rs rt funct r d sa chapter 3 cpu instruction set summary 92 3.2.3 jump and branch instructions jump and branch instructions change the control flow of a program. all jump and branch instructions occur with a delay of one instruction: that is, the instruction immediately following the jump or branch instruction (this is known as the instruction in the delay slot) always executes while the target instruction is being fetched from memory. for instructions involving a link (such as jal and bltzal), the return address is saved in register r31. table 3-13. number of delay slot cycles in jump and branch instructions instruction necessary number of cycles branch instruction 1 jump instruction 1 (1) overview of jump instructions subroutine calls in high-level languages are usually implemented with j or jal instructions, both of which are j- type instructions. in j-type format, the 26-bit target address shifts left 2 bits and combines with the high-order 4 bits of the current program counter to form a 32-bit or 64-bit absolute address. returns, dispatches, and cross-page jumps are usually implemented with the jr or jalr instructions. both are r-type instructions that take the 32-bit or 64-bit byte address contained in one of the general-purpose registers. for more information, refer to chapter 27. (2) overview of branch instructions a branch instruction has a pc-related signed 16-bit offset. tables 3-14 through 3-16 show the lists of jump, branch, and extended isa instructions, respectively. chapter 3 cpu instruction set summary 93 table 3-14. jump instruction instruction format and description jump j target the contents of 26-bit target address is shifted left by two bits and combined with the high-order four bits of the pc. the program jumps to this calculated address with a delay of one instruction. jump and link jal target the contents of 26-bit target address is shifted left by two bits and combined with the high-order four bits of the pc. the program jumps to this calculated address with a delay of one instruction. the address of the instruction following the delay slot is stored into r31 (link register). instruction format and description jump register jr rs the program jumps to the address specified in register rs with a delay of one instruction. jump and link register jalr rs, rd the program jumps to the address specified in register rs with a delay of one instruction. the address of the instruction following the delay slot is stored into rd. there are the following common restrictions for tables 3-15 and 3-16. (1) branch address all branch instruction target addresses are computed by adding the address of the instruction in the delay slot to the 16-bit offset (shifted left by 2 bits and sign-extended to 64 bits). all branches occur with a delay of one instruction. (2) operation when unbranched if the branch condition does not meet in executing a likely instruction, the instruction in its delay slot is nullified. for all other branch instructions, the instruction in its delay slot is unconditionally executed. remark the target instruction of the branch is fetched at the ex stage of the branch instruction. comparison of the operands of the branch instruction and calculation of the target address is performed at phase 2 of the rf stage and phase 1 of the ex stage of the instruction. branch instructions require one cycle of the branch delay slot defined by the architecture. jump instructions also require one cycle of delay slot. if the branch condition is not satisfied in a branch likely instruction, the instruction in its delay slot is nullified. op rs rt funct r d sa op target chapter 3 cpu instruction set summary 94 there are special symbols used in the instruction formats of tables 3-15 through 3-19. regimm : opcode sub : sub-operation code co : sub-operation identifier bc : bc sub-operation code br : branch condition identifier op : operation code table 3-15. branch instructions instruction format and description branch on equal beq rs, rt, offset if the contents of register rs are equal to that of register rt, the program branches to the target address. branch on not equal bne rs, rt, offset if the contents of register rs are not equal to that of register rt, the program branches to the target address. branch on less than or equal to zero blez rs, offset if the contents of register rs are less than or equal to zero, the program branches to the target address. branch on greater than zero bgtz rs, offset if the contents of register rs are greater than zero, the program branches to the target address. instruction format and description branch on less than zero bltz rs, offset if the contents of register rs are less than zero, the program branches to the target address. branch on greater than or equal to zero bgez rs, offset if the contents of register rs are greater than or equal to zero, the program branches to the target address. branch on less than zero and link bltzal rs, offset the address of the instruction that follows delay slot is stored to register r31 (link register). if the contents of register rs are less than zero, the program branches to the target address. branch on greater than or equal to zero and link bgezal rs, offset the address of the instruction that follows delay slot is stored to register r31 (link register). if the contents of register rs are greater than or equal to zero, the program branches to the target address. instruction format and description branch on coprocessor 0 true bc0t offset adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the instruction in the delay slot to calculate out the branch target address. if the conditional signal of the coprocessor 0 is true, the program branches to the target address with one-instruction delay. branch on coprocessor 0 false bc0f offset adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the instruction in the delay slot to calculate out the branch target address. if the conditional signal of the coprocessor 0 is false, the program branches to the target address with one-instruction delay. op rs rt offset regimm offset rs sub cop0 offset bc br chapter 3 cpu instruction set summary 95 table 3-16. branch instructions (extended isa) instruction format and description branch on equal likely beql rs, rt, offset if the contents of register rs are equal to that of register rt, the program branches to the target address. if the branch condition is not met, the instruction in the delay slot is discarded. branch on not equal likely bnel rs, rt, offset if the contents of register rs are not equal to that of register rt, the program branches to the target address. if the branch condition is not met, the instruction in the delay slot is discarded. branch on less than or equal to zero likely blezl rs, offset if the contents of register rs are less than or equal to zero, the program branches to the target address. if the branch condition is not met, the instruction in the delay slot is discarded. branch on greater than zero bgtz rs, offset if the contents of register rs are greater than zero, the program branches to the target address. if the branch condition is not met, the instruction in the delay slot is discarded. instruction format and description branch on less than zero likely bltzl rs, offset if the contents of register rs are less than zero, the program branches to the target address. if the branch condition is not met, the instruction in the delay slot is discarded. branch on greater than or equal to zero likely bgezl rs, offset if the contents of register rs are greater than or equal to zero, the program branches to the target address. if the branch condition is not met, the instruction in the delay slot is discarded. branch on less than zero and link likely bltzall rs, offset the address of the instruction that follows delay slot is stored to register r31 (link register). if the contents of register rs are less than zero, the program branches to the target address. if the branch condition is not met, the instruction in the delay slot is discarded. branch on greater than or equal to zero and link likely bgezall rs, offset the address of the instruction that follows delay slot is stored to register r31 (link register). if the contents of register rs are greater than or equal to zero, the program branches to the target address. if the branch condition is not met, the instruction in the delay slot is discarded. instruction format and description branch on coprocessor 0 true likely bc0tl offset adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the instruction in the delay slot to calculate out the branch target address. if the conditional signal of the coprocessor 0 is true, the program branches to the target address with one-instruction delay. if the branch condition is not met, the instruction in the delay slot is discarded. branch on coprocessor 0 false likely bc0fl offset adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the instruction in the delay slot to calculate out the branch target address. if the conditional signal of the coprocessor 0 is false, the program branches to the target address with one-instruction delay. if the branch condition is not met, the instruction in the delay slot is discarded. op rs rt offset regimm offset rs sub cop0 offset bc br chapter 3 cpu instruction set summary 96 3.2.4 special instructions special instructions generate software exceptions. their formats are r-type (syscall, break). the trap instruction is available only for the v r 4000 series. all the other instructions are available for all v r series. table 3-17. special instructions instruction format and description synchronize sync completes the load/store instruction executing in the current pipeline before the next load/store instruction starts execution. system call syscall generates a system call exception, and then transits control to the exception handling program. breakpoint break generates a break point exception, and then transits control to the exception handling program. table 3-18. special instructions (extended isa) (1/2) instruction format and description trap if greater than or equal tge rs, rt the contents of register rs are compared with that of register rt, treating both operands as signed integers. if the contents of register rs are greater than or equal to that of register rt, an exception occurs. trap if greater than or equal unsigned tgeu rs, rt the contents of register rs are compared with that of register rt, treating both operands as unsigned integers. if the contents of register rs are greater than or equal to that of register rt, an exception occurs. trap if less than tlt rs, rt the contents of register rs are compared with that of register rt, treating both operands as signed integers. if the contents of register rs are less than that of register rt, an exception occurs. trap if less than unsigned tltu rs, rt the contents of register rs are compared with that of register rt, treating both operands as unsigned integers. if the contents of register rs are less than that of register rt, an exception occurs. trap if equal teq rs, rt if the contents of registers rs and rt are equal, an exception occurs. trap if not equal tne rs, rt if the contents of registers rs and rt are not equal, an exception occurs. special rs rt funct r d sa special rs rt funct r d sa chapter 3 cpu instruction set summary 97 table 3-18. special instruction (extended isa) (2/2) instruction format and description trap if greater than or equal immediate tgei rs, immediate the contents of register rs are compared with 16-bit sign-extended immediate data, treating both operands as signed integers. if the contents of register rs are greater than or equal to 16-bit sign- extended immediate data, an exception occurs. trap if greater than or equal immediate unsigned tgeiu rs, immediate the contents of register rs are compared with 16-bit zero-extended immediate data, treating both operands as unsigned integers. if the contents of register rs are greater than or equal to 16-bit sign- extended immediate data, an exception occurs. trap if less than immediate tlti rs, immediate the contents of register rs are compared with 16-bit sign-extended immediate data, treating both operands as signed integers. if the contents of register rs are less than 16-bit sign-extended immediate data, an exception occurs. trap if less than immediate unsigned tltiu rs, immediate the contents of register rs are compared with 16-bit zero-extended immediate data, treating both operands as unsigned integers. if the contents of register rs are less than 16-bit sign-extended immediate data, an exception occurs. trap if equal immediate teqi rs, immediate if the contents of register rs and immediate data are equal, an exception occurs. trap if not equal immediate tnei rs, immediate if the contents of register rs and immediate data are not equal, an exception occurs. 3.2.5 system control coprocessor (cp0) instructions system control coprocessor (cp0) instructions perform operations specifically on the cp0 registers to manipulate the memory management and exception handling facilities of the processor. table 3-19. system control coprocessor (cp0) instructions (1/2) instruction format and description move to system control coprocessor mtc0 rt, rd the word data of general-purpose register rt in the cpu are loaded into general-purpose register rd in the cp0. move from system control coprocessor mfc0 rt, rd the word data of general-purpose register rd in the cp0 are loaded into general-purpose register rt in the cpu. doubleword move to system control coprocessor 0 dmtc0 rt, rd the doubleword data of general-purpose register rt in the cpu are loaded into general-purpose register rd in the cp0. doubleword move from system control coprocessor 0 dmfc0 rt, rd the doubleword data of general-purpose register rd in the cp0 are loaded into general-purpose register rt in the cpu. regimm immediate rs sub cop0 su b rt 0 r d chapter 3 cpu instruction set summary 98 table 3-19. system control coprocessor (cp0) instructions (2/2) instruction format and description read indexed tlb entry tlbr the tlb entry indexed by the index register is loaded into the entryhi, entrylo0, entrylo1, or page mask register. write indexed tlb entry tlbwi the contents of the entryhi, entrylo0, entrylo1, or page mask register are loaded into the tlb entry indexed by the index register. write random tlb entry tlbwr the contents of the entryhi, entrylo0, entrylo1, or page mask register are loaded into the tlb entry indexed by the random register. probe tlb for matching entry tlbp the address of the tlb entry that matches with the contents of entryhi register is loaded into the index register. return from exception eret the program returns from exception, interrupt, or error trap. instruction format and description standby standby the processors operating mode is transited from fullspeed mode to standby mode. suspend suspend the processors operating mode is transited from fullspeed mode to suspend mode. hibernate hibernate the processors operating mode is transited from fullspeed mode to hibernate mode. instruction format and description cache operation cache op, offset (base) the 16-bit offset is sign extended to 32 bits and added to the contents of the register case, to form virtual address. this virtual address is translated to physical address with tlb. for this physical address, cache operation that is indicated by 5-bit sub-opcode is performed. cop0 funct co cache offset base op cop0 funct co 99 chapter 4 v r 4102 pipeline this chapter describes the basic operation of the v r 4102 processor pipeline, which includes descriptions of the delay slots (instructions that follow a branch or load instruction in the pipeline), interrupts to the pipeline flow caused by interlocks and exceptions, and cp0 hazards. 4.1 pipeline stages the v r 4102 has a five-stage instruction pipeline; each stage takes one pcycle (one cycle of pclock), and each pcycle has two phases: ) 1 and ) 2, as shown in figure 4-1. thus, the execution of each instruction takes at least 5 pcycles. an instruction can take longer - for example, if the required data is not in the cache, the data must be retrieved from main memory. once the pipeline has been filled, five instructions are executed simultaneously. figure 4-1. pipeline stages cycle phase pcycle pclock if ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 rf ex dc wb the five pipeline stages are: ? if - instruction cache fetch ? rf - register fetch ? ex - execution ? dc - data cache fetch ? wb - write back figure 4-2 shows the five stages of the instruction pipeline. in this figure, a row indicates the execution process of each instruction, and a column indicates the processes executed simultaneously. chapter 4 v r 4102 pipeline 100 figure 4-2. instruction execution in the pipeline (five stages) current cpu cycle pcycle if1 if2 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 if1 if2 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 if1 if2 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 if1 if2 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 if1 if2 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 4.1.1 pipeline activities figure 4-3 shows the activities that can occur during each pipeline stage; table 4-1 describes these pipeline activities. figure 4-3. pipeline activities if1 i fetch and decode branch load/store alu cycle phase pcycle pclock if2 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 itlb idc itc ica idec wb wb dcw dtd sa dva ex bac rf dca dla dtlb dtc chapter 4 v r 4102 pipeline 101 table 4-1. description of pipeline activities during each stage cycle phase mnemonic description idc instruction cache address decode ) 1 itlb instruction address translation ica instruction cache array access if ) 2 itc instruction tag check ) 1 idec instruction decode rf register operand fetch rf ) 2 bac branch address calculation ex execution stage dva data virtual address calculation ) 1 sa store align dca data cache address decode/array access ex ) 2 dtlb data address translation dla data cache load align dtc data tag check dc ) 1 dtd data transfer to data cache dcw data cache write wb ) 1 wb write back to register file chapter 4 v r 4102 pipeline 102 4.2 branch delay during a v r 4102s pipeline operation, a one-cycle branch delay occurs when: x target address is calculated by a jump instruction x branch condition of branch instruction is met and then logical operation starts for branch-destination comparison the instruction address generated at the ex stage in the jump/branch instruction are available in the if stage, two instructions later. figure 4-4 illustrates the branch delay and the location of the branch delay slot. figure 4-4. branch delay branch delay (branch delay slot) target branch pcycle if rf ex dc wb if rf ex dc wb if rf ex dc wb 4.3 load delay a load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction. the instruction immediately following this delayed load instruction is referred to as the load delay slot. in the v r 4102, the instruction immediately following a load instruction can use the contents of the loaded register, however in such cases hardware interlocks insert additional delay cycles. consequently, scheduling load delay slots can be desirable, both for performance and v r -series processor compatibility. 4.4 pipeline operation the operation of the pipeline is illustrated by the following examples that describe how typical instructions are executed. the instructions described are: add, jalr, beq, tlt, lw, and sw. each instruction is taken through the pipeline and the operations that occur in each relevant stage are described. chapter 4 v r 4102 pipeline 103 (1) add instruction (add rd, rs, rt) if stage in ) 1 of the if stage, the eleven least-significant bits of the virtual address are used to access the instruction cache. in ) 2 of the if stage, the cache index is compared with the page frame number and the cache data is read out. the virtual pc is incremented by 4 so that the next instruction can be fetched. rf stage during ) 2, the 2-port register file is addressed with the rs and rt fields and the register data is valid at the register file output. at the same time, bypass multiplexers select inputs from either the ex- or dc-stage output in addition to the register file output, depending on the need for an operand bypass. ex stage the alu controls are set to do an a + b operation. the operands flow into the alu inputs, and the alu operation is started. the result of the alu operation is latched into the alu output latch during ) 1. dc stage this stage is a nop for this instruction. the data from the output of the ex stage (the alu) is moved into the output latch of the dc. wb stage during ) 1, the wb latch feeds the data to the inputs of the register file, which is accessed by the rd field. the file write strobe is enabled. by the end of ) 1, the data is written into the file. figure 4-5. add instruction pipeline activities if1 cycle phase pcycle pclock if2 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 itlb idc itc ica idec wb ex rf chapter 4 v r 4102 pipeline 104 (2) jump and link register instruction (jalr rd, rs) if stage same as the if stage for the add instruction. rf stage a register specified in the rs field is read from the file during ) 2 at the rf stage, and the value read from the rs register is input to the virtual pc latch synchronously. this value is used to fetch an instruction at the jump destination. the value of the virtual pc incremented during the if stage is incremented again to produce the link address pc + 8 where pc is the address of the jalr instruction. the resulting value is the pc to which the program will eventually return. this value is placed in the link output latch of the instruction address unit. ex stage the pc + 8 value is moved from the link output latch to the output latch of the ex stage. dc stage the pc + 8 value is moved from the output latch of the ex stage to the output latch of the dc stage. wb stage refer to the add instruction. note that if no value is explicitly provided for rd then register 31 is used as the default. if rd is explicitly specified, it cannot be the same register addressed by rs; if it is, the result of executing such an instruction is undefined. figure 4-6. jalr instruction pipeline activities if1 cycle phase pcycle pclock if2 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 itlb idc itc ica idec wb ex bac rf chapter 4 v r 4102 pipeline 105 (3) branch on equal instruction (beq rs, rt, offset) if stage same as the if stage for the add instruction. rf stage during ) 2, the register file is addressed with the rs and rt fields. a check is performed to determine if each corresponding bit position of these two operands has equal values. if they are equal, the pc is set to pc + target, where target is the sign-extended offset field. if they are not equal, the pc is set to pc + 4. ex stage the next pc resulting from the branch comparison is valid at the beginning of ) 2 for instruction fetch. dc stage this stage is a nop for this instruction. wb stage this stage is a nop for this instruction. figure 4-7. beq instruction pipeline activities if1 cycle phase pcycle pclock if2 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 itlb idc itc ica idec ex bac rf chapter 4 v r 4102 pipeline 106 (4) trap if less than instruction (tlt rs, rt) if stage same as the if stage for the add instruction. rf stage same as the rf stage for the add instruction. ex stage alu controls are set to do an a C b operation. the operands flow into the alu inputs, and the alu operation is started. the result of the alu operation is latched into the alu output latch during ) 1. the sign bits of operands and of the alu output latch are checked to determine if a less than condition is true. if this condition is true, a trap exception occurs. the value in the pc register is used as an exception vector value, and from now on any instruction will be invalid. dc stage no operation wb stage the epc register is loaded with the value of the pc if the less than condition was met in the ex stage. the cause register excode field and bd bit are updated appropriately, as is the exl bit of the status register. if the less than condition was not met in the ex stage, no activity occurs in the wb stage. figure 4-8. tlt instruction pipeline activities if1 cycle phase pcycle pclock if2 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 itlb idc itc ica idec ex rf chapter 4 v r 4102 pipeline 107 (5) load word instruction (lw rt, offset (base)) if stage same as the if stage for the add instruction. rf stage same as the rf stage for the add instruction. note that the base field is in the same position as the rs field. ex stage refer to the ex stage for the add instruction. for lw, the inputs to the alu come from gpr[base] through the bypass multiplexer and from the sign-extended offset field. the result of the alu operation that is latched into the alu output latch in ) 1 represents the effective virtual address of the operand (dva). dc stage the cache tag field is compared with the page frame number (pfn) field of the tlb entry. after passing through the load aligner, aligned data is placed in the dc output latch during ) 2. wb stage during ) 1, the cache read data is written into the register file addressed by the rt field. figure 4-9. lw instruction pipeline activities if1 cycle phase pcycle pclock if2 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 itlb idc itc ica idec wb dva ex rf dca dla dtlb dtc chapter 4 v r 4102 pipeline 108 (6) store word instruction (sw rt, offset (base)) if stage same as the if stage for the add instruction. rf stage same as the rf stage for the lw instruction. ex stage refer to the lw instruction for a calculation of the effective address. from the rf output latch, the gpr[rt] is sent through the bypass multiplexer and into the main shifter, where the shifter performs the byte-alignment operation for the operand. the results of the alu are latched in the output latches during ) 1. the shift operations are latched in the output latches during ) 2. dc stage refer to the lw instruction for a description of the cache access. wb stage if there was a cache hit, the content of the store data output latch is written into the data cache at the appropriate word location. note that all store instructions use the data cache for two consecutive pcycles. if the following instruction requires use of the data cache, the pipeline is slipped for one pcycle to complete the writing of an aligned store data. figure 4-10. sw instruction pipeline activities if1 cycle phase pcycle pclock if2 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 ) 2 ) 1 rf1 rf2 ex1 ex2 dc1 dc2 wb1 wb2 itlb idc itc ica idec dcw dtd sa dva ex rf dtlb dtc chapter 4 v r 4102 pipeline 109 4.5 interlock and exception handling smooth pipeline flow is interrupted when cache misses or exceptions occur, or when data dependencies are detected. interruptions handled using hardware, such as cache misses, are referred to as interlocks, while those that are handled using software are called exceptions. as shown in figure 4-11, all interlock and exception conditions are collectively referred to as faults. figure 4-11. interlocks, exceptions, and faults slip stall abort exceptions interlocks software hardware faults at each cycle, exception and interlock conditions are checked for all active instructions. because each exception or interlock condition corresponds to a particular pipeline stage, a condition can be traced back to the particular instruction in the exception/interlock stage, as shown in table 4-2. for instance, an ldi interlock is raised in the register fetch (rf) stage. tables 4-2 to 4-4 describe the pipeline interlocks and exceptions listed in table 4-2. chapter 4 v r 4102 pipeline 110 table 4-2. correspondence of pipeline stage to interlock and exception condition stage if rf ex dc wb status interlock stall e itm icm e dtm dcm dcb e slip e ldi mdi sli cp0 eee exception iaerr nmi itlb iperr intr ibe sysc bp cun rsvd trap ovf daerr reset dtlb tmod dperr wat dbe e remark in the above table, exception conditions are listed up in higher priority order. chapter 4 v r 4102 pipeline 111 table 4-3. description of pipeline exception exception description iaerr instruction address error exception nmi non-maskable interrupt exception itlb itlb exception iperr instruction parity error exception intr interrupt exception ibe instruction bus error exception sysc system call exception bp breakpoint exception cun coprocessor unusable exception rsvd reserved instruction exception trap trap exception ovf overflow exception daerr data address error exception reset reset exception dtlb dtlb exception dtmod dtlb modified exception dperr data parity error exception wat watch exception dbe data bus error exception table 4-4. pipeline interlock interlock description itm interrupt tlb miss icm interrupt cache miss ldi load data interlock mdi md busy interlock sli store-load interlock cp0 coprocessor 0 interlock dtm data tlb miss dcm data cache miss dcb data cache busy chapter 4 v r 4102 pipeline 112 4.5.1 exception conditions when an exception condition occurs, the relevant instruction and all those that follow it in the pipeline are cancelled. accordingly, any stall conditions and any later exception conditions that may have referenced this instruction are inhibited; there is no benefit in servicing stalls for a cancelled instruction. when an exceptional conditions is detected for an instruction, the v r 4102 will kill it and all following instructions. when this instruction reaches the wb stage, the exception flag and various information items are written to cp0 registers. the current pc is changed to the appropriate exception vector address and the exception bits of earlier pipeline stages are cleared. this implementation allows all preceding instructions to complete execution and prevents all subsequent instructions from completing. thus the value in the epc is sufficient to restart execution. it also ensures that exceptions are taken in the order of execution; an instruction taking an exception may itself be killed by an instruction further down the pipeline that takes an exception in a later cycle. figure 4-12. exception detection dc1 dc2 wb1 rf1 rf2 ex1 ex2 dc1 dc2 wb1 if1 if2 rf1 rf2 ex1 ex2 dc1 dc2 wb1 ex1 ex2 exception vector 2 ecxeption 1 1i 2i 1r 2r 1e 2e 1d 2d 1w 2w 1i 2i 1r 2r 1e 2e 1d 2d 1w 2w 1i 2i 1r 2r 1e 2e 1d 2d 1w 2w 1f 2f 1r 2r 1e 2e 1d 2d 1w 2w : killed stage : interpret chapter 4 v r 4102 pipeline 113 4.5.2 stall conditions stalls are used to stop the pipeline for conditions detected after the rf stage. when a stall occurs, the processor will resolve the condition and then the pipeline will continue. figure 4-13 shows a data cache miss stall, and figure 4-14 shows a cache instruction stall. figure 4-13. data cache miss stall 1 detect data cache miss if rf ex dc wb wb wb wb wb if rf ex dc dc dc dc dc wb if rf ex ex ex ex ex dc wb if rf rf rf rf rf ex dc wb 2 3 1 start moving data cache line to write buffer 2 get last word into cache and restart pipeline 3 if the cache line to be replaced is dirty the w bit is set the data is moved to the internal write buffer in the next cycle. the write-back data is returned to memory. the last word in the data is returned to the cache at 3, and pipelining restarts. figure 4-14. cache instruction stall 1 cache instruction start if rf ex dc wb wb wb wb wb if rf ex dc dc dc dc dc wb if rf ex ex ex ex ex dc wb if rf rf rf rf rf ex dc wb 2 1 cache instruction complete 2 when the cache instruction enters the dc pipe-stage, the pipeline stalls while the cache instruction is executed. the pipeline begins running again when the cache instruction is completed, allowing the instruction fetch to proceed. chapter 4 v r 4102 pipeline 114 4.5.3 slip conditions during ) 2 of the rf stage and ) 1 of the ex stage, internal logic will determine whether it is possible to start the current instruction in this cycle. if all of the source operands are available (either from the register file or via the internal bypass logic) and all the hardware resources necessary to complete the instruction will be available whenever required, then the instruction run; otherwise, the instruction will slip. slipped instructions are retired on subsequent cycles until they issue. the backend of the pipeline (stages dc and wb) will advance normally during slips in an attempt to resolve the conflict. nops will be inserted into the bubble in the pipeline. instructions killed by branch likely instructions, eret or exceptions will not cause slips. figure 4-15. load data interlock 1 add a, b load b load a bypass detect load interlock if rf ex dc wb if rf ex dc wb if rf rf ex dc wb if rf ex dc wb 1 get the target data 2 2 load data interlock is detected in the rf stage shown in as figure 4-15 and also the pipeline slips in the stage. load data interlock occurs when data fetched by a load instruction and data moved from hi, lo or cp0 register is required by the next immediate instruction. the pipeline begins running again when the clock after the target of the load is read from the data cache, hi, lo and cp0 register. the data returned at the end of the dc stage is input into the end of the rf stage, using the bypass multiplexers. figure 4-16. md busy interlock 1 mflo/mfhi bypass detect md busy interlock if rf ex dc wb if rf rf ex dc wb if rf ex dc wb 1 get target data 2 2 chapter 4 v r 4102 pipeline 115 md busy interlock is detected in the rf stage as shown in figure 4-16 and also the pipeline slips in the stage. md busy interlock occurs when hi/lo register is required by mfhi/lo instruction before finishing mult/div execution. the pipeline begins running again the clock after finishing mult/div execution. the data returned from the hi/lo register at the end of the dc stage is input into the end of the rf stage, using the bypass multiplexers. store-load interlock is detected in the ex stage and the pipeline slips in the rf stage. store-load interlock occurs when store instruction followed by load instruction is detected. the pipeline begins running again one clock after. coprocessor 0 interlock is detected in the ex stage and the pipeline slips in the rf stage. a coprocessor interlock occurs when an mtc0 instruction for the configuration or status register is detected. the pipeline begins running again one clock after. 4.5.4 bypassing in some cases, data and conditions produced in the ex, dc and wb stages of the pipeline are made available to the ex stage (only) through the bypass data path. operand bypass allows an instruction in the ex stage to continue without having to wait for data or conditions to be written to the register file at the end of the wb stage. instead, the bypass control unit is responsible for ensuring data and conditions from later pipeline stages are available at the appropriate time for instructions earlier in the pipeline. the bypass control unit is also responsible for controlling the source and destination register addresses supplied to the register file. 4.6 code compatibility the v r 4100 cpu core can execute all programs that can be executed in other v r -series processors. but the reverse is not necessarily true. programs complied using a standard mips compiler can be executed in both types of processors. when using manual assembly, however, write programs carefully so that compatibility with other v r- series processors can be maintained. matters which should be paid attention to when porting programs between the v r 4100 cpu core and other v r -series processors are listed below. the v r 4100 cpu core does not support floating-point instructions since it has no floating-point unit (fpu). multiply-add instructions (dmadd16, madd16) are added in the v r 4100 cpu core. instructions for power modes (hibernate, standby, suspend) are added in the v r 4100 cpu core to support power modes. the v r 4100 cpu core does not have the ll bit to perform synchronization of multiprocessing. therefore, the cpu core does not support instructions which manipulate the ll bit (ll, lld, sc, scd). the cp0 hazards of the v r 4100 cpu core are equally or less stringent than those of other processors (see chapter 28 for details). for more information, refer to chapter 27, the v r 4000, v r 4400 users manual , or the v r 4200 tm users manual . 116 [memo] 117 chapter 5 memory management system the v r 4102 provides a memory management unit (mmu) which uses a translation lookaside buffer (tlb) to translate virtual addresses into physical addresses. this chapter describes the virtual and physical address spaces, the virtual-to-physical address translation, the operation of the tlb in making these translations, and the cp0 registers that provide the software interface to the tlb. 5.1 translation lookaside buffer (tlb) virtual addresses are translated into physical addresses using an on-chip tlb 22. the on-chip tlb is a fully- associative memory that holds 32 entries, which provide mapping to 32 odd/even page pairs for one entry. the pages can have five different sizes, 1 k, 4 k, 16 k, 64 k, and 256 k, and can be specified in each entry. if it is supplied with a virtual address, each of the 32 tlb entries is checked simultaneously to see whether they match the virtual addresses that are provided with the asid field and saved in the entryhi register. if there is a virtual address match, or hit, in the tlb, the physical page number is extracted from the tlb and concatenated with the offset to form the physical address. if no match occurs (tlb miss), an exception is taken and software refills the tlb from the page table resident in memory. the software writes to an entry selected using the index register or a random entry indicated in the random register. if more than one entry in the tlb matches the virtual address being translated, the operation is undefined and the tlb may be disabled. in this case, the tlb-shutdown (ts) bit of the status register is set to 1, and the tlb becomes unusable (an attempt to access the tlb results in a tlb mismatch exception regardless of whether there is an entry that hits). the ts bit can be cleared only by a reset. note that virtual addresses may be converted to physical addresses without using a tlb, depending on the address space that is being subjected to address translation. for example, address translation for the kseg0 or kseg1 address space does not use mapping. the physical addresses of these address spaces are determined by subtracting the base address of the address space from the virtual addresses. 5.2 virtual address space the address space of the cpu is extended in memory management system, by converting (translating) huge virtual memory addresses into physical addresses. the physical address space of the v r 4102 is 4 gbytes and 32-bit width addresses are used. for the virtual address space, up to 2 gbytes (2 31 ) are provided as a users area and 32-bit width addresses are used in the 32-bit mode. in the 64-bit mode, up to 1 tbyte (2 40 ) is provided as a users area and 64-bit width addresses are used. for the format of the tlb entry in each mode, refer to 5.4.1. as shown in figures 4-2 and 4-3, the virtual address is extended with an address space identifier (asid), which reduces the frequency of tlb flushing when switching contexts. this 8-bit asid is in the cp0 entryhi register, and the global (g) bit is in the entrylo0 and entrylo1 registers, described later in this chapter. chapter 5 memory management system 118 figure 5-1. virtual-to-physical address translation virtual address the offset is then added to the pfn passing through the tlb. if there is a match, the page frame number (pfn) representing the high- order bits of the physical address is output from the tlb. the virtual page number (vpn) in the virtual address (va) is compared with the vpn in the tlb. tlb entry physical address 3 2 tlb 1 asid offset vpn offset pfn pfn g asid vpn 5.2.1 virtual-to-physical address translation converting a virtual address to a physical address begins by comparing the virtual address from the processor with the virtual addresses in the tlb; there is a match when the virtual page number (vpn) of the address is the same as the vpn field of the entry, and either: ? the global (g) bit of the tlb entry is set to 1, or ? the asid field of the virtual address is the same as the asid field of the tlb entry. this match is referred to as a tlb hit. if there is no match, a tlb mismatch exception is taken by the processor and software is allowed to refill the tlb from a page table of virtual/physical addresses in memory. if there is a virtual address match in the tlb, the physical address is output from the tlb and concatenated with the offset, which represents an address within the page frame space. the offset does not pass through the tlb. instead, the low-order bits of the virtual address are output without being translated. see descriptions about the virtual address space for details. for details about the physical address, see 5.4.9 virtual-to-physical address translation . the next two sections describe the 32-bit and 64-bit mode address translations. chapter 5 memory management system 119 5.2.2 32-bit mode address translation figure 5-2 shows the virtual-to-physical-address translation of a 32-bit mode address. the pages can have five different sizes between 1 kbyte (10 bits) and 256 kbytes (18 bits), each being 4 times as large as the preceding one in ascending order, that is 1 k, 4 k, 16 k, 64 k, and 256 k. ? shown at the top of figure 5-2 is the virtual address space in which the page size is 1 kbyte and the offset is 10 bits. the 22 bits excluding the asid field represents the virtual page number (vpn), enabling selecting a page table of 4 m entries. ? shown at the bottom of figure 5-2 is the virtual address space in which the page size is 256 kbytes and the offset is 18 bits. the 14 bits excluding the asid field represents the vpn, enabling selecting a page table of 16 k entries. figure 5-2. 32-bit mode virtual address translation bits 31 to 29 of the virtual address select the user, supervisor, or kernel address space. 31 pfn virtual address for 16k ( 2 14 ) 256-kb y te pa g es virtual address for 4m (2 22 ) 1-kbyte pages 22 bits = 4m pages the offset is passed to ph y sical address without bein g chan g ed. the offset is passed to ph y sical address without bein g chan g ed. virtual-to-ph y sical address translation with the tlb virtual-to- ph y sical address translation with the tlb 10 22 8 0 0 9 10 28 29 31 32 39 asid offset vpn offset tlb 14 bits = 16k pa g es 18 14 8 0 17 18 28 29 31 32 39 asid vpn offset tlb chapter 5 memory management system 120 5.2.3 64-bit mode address translation figure 5-3 shows the virtual-to-physical-address translation of a 64-bit mode address. the pages can have five different sizes between 1 kbyte (10 bits) and 256 kbytes (18 bits), each being 4 times as large as the preceding one in ascending order, that is 1k, 4k, 16k, 64k, and 256k. this figure illustrates the two possible page sizes: a 1- kbyte page (10 bits) and a 256-kbyte page (18 bits). ? shown at the top of figure 5-3 is the virtual address space in which the page size is 1 kbyte and the offset is 10 bits. the 30 bits excluding the asid field represents the virtual page number (vpn), enabling selecting a page table of 1 g entry. ? shown at the bottom of figure 5-3 is the virtual address space in which the page size is 256 kbytes and the offset is 18 bits. the 22 bits excluding the asid field represents the vpn, enabling selecting a page table of 4 m entries. figure 5-3. 64-bit mode virtual address translation 31 pfn 32-bit physical address 10 22 30 8 0 0 9 10 39 40 61 62 63 64 71 asid offset tlb 18 22 22 8 0 17 18 39 40 61 62 63 64 71 asid tlb 0 or -1 0 or -1 vpn offset vpn offset bits 62 and 63 of the virtual address select the user, supervisor, or kernel address space. virtual address for 4m (2 22 ) 256-kbyte pages virtual address for 1g (2 30 ) 1-kb y te pa g es 30 bits = 1g pages the offset is passed to ph y sical address without bein g chan g ed. the offset is passed to ph y sical address without bein g chan g ed. virtual-to-ph y sical address translation with the tlb virtual-to-ph y sical address translation with the tlb 22 bits = 4m pages 2 2 chapter 5 memory management system 121 5.2.4 operating modes the processor has three operating modes that function in both 32- and 64-bit operations: ? user mode ? supervisor mode ? kernel mode user and kernel modes are common to all v r -series processors. generally, kernel mode is used to executing the operating system, while user mode is used to run application programs. the v r 4000 series processors have a third mode, which is called supervisor mode and categorized in between user and kernel modes. this mode is used to configure a high-security system. when an exception occurs, the cpu enters kernel mode, and remains in this mode until an exception return instruction (eret) is executed. the eret instruction brings back the processor to the mode in which it was just before the exception occurs. these modes are described in the next three sections. 5.2.5 user mode virtual addressing during the single user mode, a 2-gbyte (2 31 bytes) virtual address space (useg) can be used in the 32-bit mode. in the 64-bit mode, a 1-tbyte (2 40 bytes) virtual address space (xuseg) can be used. as shown in tables 5-2 and 5-3, each virtual address is extended independently as another virtual address by setting an 8-bit address space id area (asid), to support user processes of up to 256. the contents of tlb can be retained after context switching by allocating each process by asid. useg and xuseg can be referenced via tlb. whether a cache is used or not is determined for each page by the tlb entry (depending on the c bit setting in the tlb entry). the user segment starts at address 0 and the current active user process resides in either useg (in 32-bit mode) or xuseg (in 64-bit mode). the tlb identically maps all references to useg/xuseg from all modes, and controls cache accessibility. the processor operates in user mode when the status register contains the following bit-values: ? ksu = 10 ? exl = 0 ? erl = 0 in conjunction with these bits, the ux bit in the status register selects 32- or 64-bit user mode addressing as follows: ? when ux = 0, 32-bit useg space is selected. ? when ux = 1, 64-bit xuseg space is selected. table 5-1 lists the characteristics of each user segment (useg and xuseg). chapter 5 memory management system 122 figure 5-4. user mode address space 64-bit mode 32-bit mode note 0x8000 0000 0xffff ffff address error 0x0000 0100 0000 0000 0xffff ffff ffff ffff address error xuse g use g 0x0000 0000 0x7fff ffff 2 gbytes with tlb mapping 0x0000 0000 0000 0000 0x0000 00ff ffff ffff 1 tbyte with tlb mapping note the v r 4102 uses 64-bit addresses within it. when the processor is running in kernel mode, it saves the contents of each register or restores their previous contents to initialize them before switching the context. for 32-bit mode addressing, bit 31 is sign-extended to bits 32 to 63, and the resulting 32 bits are used for addressing. usually, it is impossible for 32-bit mode programs to generate invalid addresses. if context switching occurs and the processor enters kernel mode, however, an attempt may be made to save an address other than the sign-extended 32-bit address mentioned above to a 64-bit register. in this case, user-mode programs are likely to generate an invalid address. table 5-1. comparison of useg and xuseg address bit status register bit value segment address range size value ksu exl erl ux name 32-bit a[31] = 0 10 0 0 0 useg 0x0000 0000 to 0x7fff ffff 2 gbytes (2 31 bytes) 64-bit a[63..40] = 0 10 0 0 1 xuseg 0x0000 0000 0000 0000 to 0x0000 00ff ffff ffff 1 tbyte (2 40 bytes) chapter 5 memory management system 123 (1) useg (32-bit mode) in user mode, when ux = 0 in the status register and the most significant bit of the virtual address is 0, user mode addressing is compatible with the 32-bit addressing model shown in figure 5-4, and a 2-gbyte user address space is available, labeled useg. any attempt to reference an address with the most-significant bit set while in user mode causes an address error exception (see chapter 6 exception processing ). the tlb mismatch exception vector is used for tlb misses. (2) xuseg (64-bit mode) in user mode, when ux = 1 in the status register and bits 63 to 40 of the virtual address are all 0, user mode addressing is extended to the 64-bit addressing model shown in figure 5-4. in 64-bit user mode, the processor provides a single address space of 240 bytes, labeled xuseg. any attempt to reference an address with bits 63:40 equal to 1 causes an address error exception (see chapter 6 exception processing ). the xtlb mismatch exception vector is used for tlb misses. chapter 5 memory management system 124 5.2.6 supervisor-mode virtual addressing supervisor mode is designed for layered operating systems in which a true kernel runs in kernel mode, and the rest of the operating system runs in supervisor mode. all of the suseg, sseg, xsuseg, xsseg, and csseg spaces are referenced via tlb. whether cache can be used or not is determined by bit c of each pages tlb entry. the processor operates in supervisor mode when the status register contains the following bit-values: ? ksu = 01 ? exl = 0 ? erl = 0 in conjunction with these bits, the sx bit in the status register selects 32- or 64-bit supervisor mode addressing: ? when sx = 0, 32-bit supervisor space is selected. ? when sx = 1, 64-bit supervisor space is selected. table 5-2 lists the characteristics of the supervisor mode segments. chapter 5 memory management system 125 figure 5-5. supervisor mode address space 64-bit mode 32-bit mode note 0xdfff ffff 0xe000 0000 0xc000 0000 0xffff ffff address error 0x0000 0010 0000 0000 0xffff ffff ffff ffff suseg sseg 0x7fff ffff 0x0000 0000 0x8000 0000 xsuseg xsseg csseg 0xbfff ffff 0x4000 00ff ffff ffff 0x4000 0100 0000 0000 0x0000 000f ffff ffff 0.5 gbytes with tlb mapping address error 2 gbytes with tlb mapping address error 0.5 gbytes with tlb mapping address error 1 tbyte with tlb mapping address error 1 tbyte with tlb mapping 0xffff ffff e000 0000 0xffff ffff dfff ffff 0xffff ffff c000 0000 0xffff ffff bfff ffff 0x3fff ffff ffff ffff 0x4000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 00ff ffff ffff 0x0000 0100 0000 0000 note the v r 4102 uses 64-bit addresses within it. for 32-bit mode addressing, bit 31 is sign-extended to bits 32 to 63, and the resulting 32 bits are used for addressing. usually, it is impossible for 32-bit mode programs to generate invalid addresses. in an operation of base register + offset for addressing, however, a twos complement overflow may occur, causing an invalid address. note that the result becomes undefined. two factors that can cause a twos complement follow: ? when offset bit 15 is 0, base register bit 31 is 0, and bit 31 of the operation base register + offset is 1 ? when offset bit 15 is 1, base register bit 31 is 1, and bit 31 of the operation base register + offset is 0 chapter 5 memory management system 126 table 5-2. 32-bit and 64-bit supervisor mode segments address bit status register bit value segment address range size value ksu exl erl sx name 32-bit a[31] = 0 01 0 0 0 suseg 0x0000 0000 to 0x7fff ffff 2 gbytes (2 31 bytes) 32-bit a[31..29] = 110 01 0 0 0 sseg 0xc000 0000 to 0xdfff ffff 512 mbytes (2 29 bytes) 64-bit a[63..62] = 00 01 0 0 1 xsuseg 0x0000 0000 0000 0000 to 0x0000 00ff ffff ffff 1 tbyte (2 40 bytes) 64-bit a[63..62] = 01 01 0 0 1 xsseg 0x 4000 0000 0000 0000 to 0x4000 00ff ffff ffff 1 tbyte (2 40 bytes) 64-bit a[63..62] = 11 01 0 0 1 csseg 0xffff ffff c 000 0000 to 0xffff ffff dfff ffff 512 mbytes (2 29 bytes) (1) suseg (32-bit supervisor mode, user space) when sx = 0 in the status register and the most-significant bit of the virtual address space is set to 0, the suseg virtual address space is selected; it covers 2 gbytes (2 31 bytes) of the current user address space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. this mapped space starts at virtual address 0x0000 0000 and runs through 0x7fff ffff. (2) sseg (32-bit supervisor mode, supervisor space) when sx = 0 in the status register and the three most-significant bits of the virtual address space are 110, the sseg virtual address space is selected; it covers 512 mbytes (229 bytes) of the current supervisor virtual address space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. this mapped space begins at virtual address 0xc000 0000 and runs through 0xdfff ffff. (3) xsuseg (64-bit supervisor mode, user space) when sx = 1 in the status register and bits 63 and 62 of the virtual address space are set to 00, the xsuseg virtual address space is selected; it covers 1 tbyte (2 40 bytes) of the current user address space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. this mapped space starts at virtual address 0x0000 0000 0000 0000 and runs through 0x0000 00ff ffff ffff. chapter 5 memory management system 127 (4) xsseg (64-bit supervisor mode, current supervisor space) when sx = 1 in the status register and bits 63 and 62 of the virtual address space are set to 01, the xsseg virtual address space is selected; it covers 1 tbyte (2 40 bytes) of the current supervisor virtual address space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. this mapped space begins at virtual address 0x4000 0000 0000 0000 and runs through 0x4000 00ff ffff ffff. (5) csseg (64-bit supervisor mode, separate supervisor space) when sx = 1 in the status register and bits 63 and 62 of the virtual address space are set to 11, the csseg virtual address space is selected; it covers 512 mbytes (2 29 bytes) of the separate supervisor virtual address space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. this mapped space begins at virtual address 0xffff ffff c000 0000 and runs through 0xffff ffff dfff ffff. 5.2.7 kernel-mode virtual addressing if the status register satisfies any of the following conditions, the processor runs in kernel mode. ? ksu = 00 ? exl = 1 ? erl = 1 the addressing width in kernel mode varies according to the state of the kx bit of the status register, as follows: ? when kx = 0, 32-bit kernel space is selected. ? when kx = 1, 64-bit kernel space is selected. the processor enters kernel mode whenever an exception is detected and it remains in kernel mode until an exception return (eret) instruction is executed and results in erl and/or exl = 0. the eret instruction restores the processor to the mode existing prior to the exception. kernel mode virtual address space is divided into regions differentiated by the high-order bits of the virtual address, as shown in figure 5-6. table 5-3 lists the characteristics of the 32-bit kernel mode segments, and table 5-4 lists the characteristics of the 64-bit kernel mode segments. chapter 5 memory management system 128 figure 5-6. kernel mode address space 32-bit mode note 1 0.5 gbytes with tlb mapping 0.5 gbytes with tlb mapping 0.5 gbytes without tlb mapping uncacheable 64-bit mode 0xdfff ffff 0xe000 0000 0xc000 0000 0xffff ffff 0xffff ffff ffff ffff kuseg kseg0 kseg1 ksseg kseg3 0x7fff ffff 0x0000 0000 0x8000 0000 xkuseg xksseg xkphys xkseg ckseg0 ckseg1 ckseg cksseg 0xbfff ffff 0xffff ffff 9fff ffff 0xffff ffff a000 0000 0.5 gbytes without tlb mapping cacheable 2 gbytes with tlb mapping 0xffff ffff e000 0000 0xffff ffff dfff ffff 0xffff ffff c000 0000 0xffff ffff bfff ffff 0xffff ffff 7fff ffff 0xffff ffff 8000 0000 0xc000 00ff 7fff ffff 0xc000 00ff 8000 0000 0.5 gbytes with tlb mapping 0.5 gbytes with tlb mapping 0.5 gbytes without tlb mapping uncacheable 0.5 gbytes without tlb mapping cacheable address error with tlb mapping without tlb mapping (see table 5-7 for details.) address error 1 tbyte with tlb mapping address error 1 tbyte with tlb mapping 0x4000 00ff ffff ffff 0x4000 0100 0000 0000 0xc000 0000 0000 0000 0xbfff ffff ffff ffff 0x8000 0000 0000 0000 0x7fff ffff ffff ffff 0x3fff ffff ffff ffff 0x4000 0000 0000 0000 0x0000 0000 0000 0000 0x0000 00ff ffff ffff 0x0000 0100 0000 0000 0xa000 0000 0x9fff ffff note2 note 2 notes 1. the v r 4102 uses 64-bit addresses within it. for 32-bit mode addressing, bit 31 is sign-extended to bits 32 to 63, and the resulting 32 bits are used for addressing. usually, a 64-bit instruction is used for the program in 32-bit mode. in an operation of base register + offset for addressing, however, a twos complement overflow may occur, causing an invalid address. note that the result becomes undefined. two factors that can cause a twos complement follow: ? when offset bit 15 is 0, base register bit 31 is 0, and bit 31 of the operation base register + offset is 1 ? when offset bit 15 is 1, base register bit 31 is 1, and bit 31 of the operation base register + offset is 0 2. the k0 field of the config register controls cacheability of kseg0 and ckseg0. chapter 5 memory management system 129 figure 5-7. xkphys area address space 0xbfff ffff ffff ffff 0xb000 0000 ffff ffff 0xb000 0001 0000 0000 0xb800 0001 0000 0000 0xb800 0000 ffff ffff 0xb800 0000 0000 0000 0xb7ff ffff ffff ffff 0xafff ffff ffff ffff 0xb000 0000 0000 0000 0xa800 0000 ffff ffff 0xa800 0001 0000 0000 address error address error address error 0x9fff ffff ffff ffff 0xa000 0000 0000 0000 0xa800 0000 0000 0000 0xa7ff ffff ffff ffff 0xa000 0001 0000 0000 0xa000 0000 ffff ffff 0x9800 0000 ffff ffff 0x9800 0001 0000 0000 0x9000 0001 0000 0000 0x97ff ffff ffff ffff 0x9800 0000 0000 0000 address error 4 gbytes without tlb mapping cacheable 4 gbytes without tlb mapping cacheable address error address error address error address error 4 gbytes without tlb mapping cacheable 4 gbytes without tlb mapping cacheable 4 gbytes without tlb mapping cacheable 4 gbytes without tlb mapping cacheable 4 gbytes without tlb mapping cacheable 4 gbytes without tlb mapping cacheable 0x8000 0000 0000 0000 0x8000 0000 ffff ffff 0x8000 0001 0000 0000 0x9000 0000 ffff ffff 0x9000 0000 0000 0000 0x8800 0000 ffff ffff 0x8800 0001 0000 0000 0x8fff ffff ffff ffff 0x87ff ffff ffff ffff 0x8800 0000 0000 0000 chapter 5 memory management system 130 table 5-3. 32-bit kernel mode segments address bit value status register bit value segment virtual address physical size ksu exl erl kx name address 32-bit a[31] = 0 0 kuseg 0x0000 0000 to 0x7fff ffff tlb map 2 gbytes (2 31 bytes) 32-bit a[31..29] = 100 0 kseg0 0x8000 0000 to 0x9fff ffff 0x0000 0000 to 0x1fff ffff 512 mbytes (2 29 bytes) 32-bit a[31..29] = 101 0 kseg1 0xa000 0000 to 0xbfff ffff 0x0000 0000 to 0x1fff ffff 512 mbytes (2 29 bytes) 32-bit a[31..29] = 110 0 ksseg 0xc 000 0000 to 0xdfff ffff tlb map 512 mbytes (2 29 bytes) 32-bit a[31..29] = 111 ksu = 00 or exl = 1 or erl = 1 0 kseg3 0xe000 0000 to 0xffff ffff tlb map 512 mbytes (2 29 bytes) (1) kuseg (32-bit kernel mode, user space) when kx = 0 in the status register, and the most-significant bit of the virtual address space is 0, the kuseg virtual address space is selected; it is the current 2-gbyte (2 31 -byte) user address space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. references to kuseg are mapped through tlb. whether cache can be used or not is determined by bit c of each pages tlb entry. if the erl bit of the status register is 1, the user address space is assigned 2 gbytes (2 31 bytes) without tlb mapping and becomes unmapped (with virtual addresses being used as physical addresses) and uncached so that the cache error handler can use it. this allows the cache error exception code to operate uncached using r0 as a base register. (2) kseg0 (32-bit kernel mode, kernel space 0) when kx = 0 in the status register and the most-significant three bits of the virtual address space are 100, the kseg0 virtual address space is selected; it is the current 512-mbyte (2 29 -byte) physical space. references to kseg0 are not mapped through tlb; the physical address selected is defined by subtracting 0x8000 0000 from the virtual address. the k0 field of the config register controls cacheability (see chapter 6 exception processing ). chapter 5 memory management system 131 (3) kseg1 (32-bit kernel mode, kernel space 1) when kx = 0 in the status register and the most-significant three bits of the virtual address space are 101, the kseg1 virtual address space is selected; it is the current 512-mbyte (2 29 -byte) physical space. references to kseg1 are not mapped through tlb; the physical address selected is defined by subtracting 0xa000 0000 from the virtual address. caches are disabled for accesses to these addresses, and main memory (or memory-mapped i/o device registers) is accessed directly. (4) ksseg (32-bit kernel mode, supervisor space) when kx = 0 in the status register and the most-significant three bits of the virtual address space are 110, the ksseg virtual address space is selected; it is the current 512-mbyte (2 29 -byte) virtual address space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. references to ksseg are mapped through tlb. whether cache can be used or not is determined by bit c of each pages tlb entry. (5) kseg3 (32-bit kernel mode, kernel space 3) when kx = 0 in the status register and the most-significant three bits of the virtual address space are 111, the kseg3 virtual address space is selected; it is the current 512-mbyte (2 29 -byte) kernel virtual space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. references to kseg3 are mapped through tlb. whether cache can be used or not is determined by bit c of each pages tlb entry. chapter 5 memory management system 132 table 5-4. 64-bit kernel mode segments address bit status register bit value segment virtual address physical size value ksu exl erl kx name address 64-bit a[63..62] = 00 1 xkuseg 0x0000 0000 0000 0000 to 0x0000 00ff ffff ffff tlb map 1 tbyte (2 40 bytes) 64-bit a[63..62] = 01 1 xksseg 0x 4000 0000 0000 0000 to 0x4000 00ff ffff ffff tlb map 1 tbyte (2 40 bytes) 64-bit a[63..62] = 10 1 xkphys 0x8000 0000 0000 0000 to 0xbfff ffff ffff ffff 0x0000 0000 to 0xffff ffff 4 gbytes (2 32 bytes) 64-bit a[63..62] = 11 1 xkseg 0xc 000 0000 0000 0000 to 0xc000 00ff 7fff ffff tlb map 2 40 - 2 31 bytes 64-bit a[63..62] = 11 a[63..31] = -1 1 ckseg0 0xffff ffff 8000 0000 to 0xffff ffff 9fff ffff 0x0000 0000 to 0x1fff ffff 512 mbytes (2 29 bytes) 64-bit a[63..62] = 11 a[63..31] = -1 1 ckseg1 0xffff ffff a000 0000 to 0xffff ffff bfff ffff 0x0000 0000 to 0x1fff ffff 512 mbytes (2 29 bytes) 64-bit a[63..62] = 11 a[63..31] = -1 1 cksseg 0xffff ffff c 000 0000 to 0xffff ffff dfff ffff tlb map 512 mbytes (2 29 bytes) 64-bit a[63..62] = 11 a[63..31] = -1 ksu = 00 or exl = 1 or erl = 1 1 ckseg3 0xffff ffff e000 0000 to 0xffff ffff ffff ffff tlb map 512 mbytes (2 29 bytes) (6) xkuseg (64-bit kernel mode, user space) when kx = 1 in the status register and bits 63 and 62 of the virtual address space are 00, the xkuseg virtual address space is selected; it is the 1-tbyte (2 40 bytes) current user address space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. references to xkuseg are mapped through tlb. whether cache can be used or not is determined by bit c of each pages tlb entry. if the erl bit of the status register is 1, the user address space is assigned 2 gbytes (2 31 bytes) without tlb mapping and becomes unmapped (with virtual addresses being used as physical addresses) and uncached so that the cache error handler can use it. this allows the cache error exception code to operate uncached using r0 as a base register. (7) xksseg (64-bit kernel mode, current supervisor space) when kx = 1 in the status register and bits 63 and 62 of the virtual address space are 01, the xksseg address space is selected; it is the 1-tbyte (2 40 bytes)current supervisor address space. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. references to xksseg are mapped through tlb. whether cache can be used or not is determined by bit c of each pages tlb entry. chapter 5 memory management system 133 (8) xkphys (64-bit kernel mode, physical spaces) when the kx = 1 in the status register and bits 63 and 62 of the virtual address space are 10, the virtual address space is called xkphys and selected as either cached or uncached. if any of bits 58 to 32 of the address is 1, an attempt to access that address results in an address error. whether cache can be used or not is determined by bits 59 to 61 of the virtual address. table 5-5 shows cacheability corresponding to 8 address spaces. table 5-5. cacheability and the xkphys address space bits 61-59 cacheability start address 0 cached 0x8000 0000 0000 0000 to 0x8000 0000 ffff ffff 1 cached 0x8800 0000 0000 0000 to 0x8800 0000 ffff ffff 2 uncached 0x9000 0000 0000 0000 to 0x9000 0000 ffff ffff 3 cached 0x9800 0000 0000 0000 to 0x9800 0000 ffff ffff 4 cached 0xa000 0000 0000 0000 to 0xa000 0000 ffff ffff 5 cached 0xa800 0000 0000 0000 to 0xa800 0000 ffff ffff 6 cached 0xb000 0000 0000 0000 to 0xb000 0000 ffff ffff 7 cached 0xb800 0000 0000 0000 to 0xb800 0000 ffff ffff (9) xkseg (64-bit kernel mode, physical spaces) when the kx = 1 in the status register and bits 63 and 62 of the virtual address space are 11, the virtual address space is called xkseg and selected as either of the following: ? kernel virtual space, xkseg, the current kernel virtual space; the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address references to xkseg are mapped through tlb. whether cache can be used or not is determined by bit c of each pages tlb entry. ? one of the four 32-bit kernel compatibility spaces, as described in the next section. chapter 5 memory management system 134 (10) 64-bit kernel mode compatible spaces (ckseg0, ckseg1, cksseg, and ckseg3) if the conditions listed below are satisfied in kernel mode, ckseg0, ckseg1, cksseg, or ckseg3 (each having 512 mbytes) is selected as a compatible space according to the state of the bits 30 and 29 (two low-order bits) of the address. ? the kx bit of the status register is 1. ? bits 63 and 62 of the 64-bit virtual address are 11. ? bits 61 to 31 of the virtual address are all 1. (i) ckseg0 this space is an unmapped region, compatible with the 32-bit mode kseg0 space. the k0 field of the config register controls cacheability and coherency. (ii) ckseg1 this space is an unmapped and uncached region, compatible with the 32-bit mode kseg1 space. (iii) cksseg this space is the current supervisor virtual space, compatible with the 32-bit mode ksseg space. references to cksseg are mapped through tlb. whether cache can be used or not is determined by bit c of each pages tlb entry. (iv) ckseg3 this space is the current supervisor virtual space, compatible with the 32-bit mode kseg3 space. references to ckseg3 are mapped through tlb. whether cache can be used or not is determined by bit c of each pages tlb entry. chapter 5 memory management system 135 5.3 physical address space using a 32-bit address, the processor physical address space encompasses 4 gbytes. the v r 4102 uses this 4- gbyte physical address space as shown in figure 5-8. figure 5-8. v r 4102 physical address space 0x1800 0000 0x1fff ffff 0x2000 0000 0xffff ffff 0x17ff ffff 0x1400 0000 0x0000 0000 0x09ff ffff 0x0a00 0000 0x1000 0000 0x13ff ffff 0x0b00 0000 0x0fff ffff 0x0aff ffff 0x0d00 0000 0x0cff ffff rfu dram area (mirror image of 0x0000 0000 to 0x1fff ffff a) rom area (include boot rom) s y stem bus i/o area ( isa-io ) system bus i/o area (isa-mem) rfu internal i/o area 1 internal i/o area 2 lcd/high-speed system bus area 0x0c00 0000 0x0bff ffff 0x03ff ffff 0x0400 0000 chapter 5 memory management system 136 table 5-6. v r 4102 physical address space physical address space capacity (bytes) 0xffff ffff to 0x2000 0000 mirror image of 0x1fff ffff to 0x0000 0000 3.5 g 0x1fff ffff to 0x1800 0000 rom space 128 m 0x17ff ffff to 0x1400 0000 system bus i/o space (isa-io) 64 m 0x13ff ffff to 0x1000 0000 system bus memory space (isa-mem) 64 m 0x0fff ffff to 0x0d00 0000 space reserved for future use 48 m 0x0cff ffff to 0x0c00 0000 internal i/o space 1 16 m 0x0bff ffff to 0x0b00 0000 internal i/o space 2 16 m 0x0aff ffff to 0x0a00 0000 lcd/high-speed system bus memory space 16 m 0x09ff ffff to 0x0400 0000 space reserved for future use 96 m 0x03ff ffff to 0x0000 0000 dram space 64 m chapter 5 memory management system 137 5.3.1 rom space the rom space differs depending on the data bus bit width and the capacity of the rom being used. ? the data bus bit width is set via the dbus32 pin. ? the rom capacity is set via the bcuntreg1s rom64 bit. the physical addresses of the rom space are listed below. table 5-7. rom addresses (when using 16-bit data bus) physical address add[25:0] pin when using 32-m rom when using 64-m rom 0x1fff ffff to 0x1fc0 0000 0x3ff ffff to 0x3c0 0000 bank 3 (romcs[3]#) bank 3 (romcs[3]#) 0x1fbf ffff to 0x1f80 0000 0x3bf ffff to 0x380 0000 bank 2 (romcs[2]#) 0x1f7f ffff to 0x1f40 0000 0x37f ffff to 0x340 0000 bank 1 (romcs[1]#) bank 2 (romcs[2]#) 0x1f3f ffff to 0x1f00 0000 0x33f ffff to 0x300 0000 bank 0 (romcs[0]#) 0x1eff ffff to 0x1e80 0000 0x2ff ffff to 0x280 0000 rom space reserved for future use bank 1 (romcs[1]#) 0x1e7f ffff to 0x1e00 0000 0x27f ffff to 0x200 0000 bank 0 (romcs[0]#) 0x1dff ffff to 0x1800 0000 0x1ff ffff to 0x000 0000 rom space reserved for future use table 5-8. rom addresses (when using 32-bit data bus) physical address add[25:0] pin when using 32-mbit rom when using 64-mbit rom 0x1fff ffff to 0x1f80 0000 0x3ff ffff to 0x380 0000 bank 1 (romcs[1]#) bank 1 (romcs[1]#) 0x1f7f ffff to 0x1f00 0000 0x37f ffff to 0x300 0000 bank 0 (romcs[0]#) 0x1eff ffff to 0x1e00 0000 0x2ff fff0 to 0x200 0000 rom space reserved for future use bank 0 (romcs[0]#) 0x1dff ffff to 0x1800 0000 0x1ff ffff to 0x000 0000 rom space reserved for future use chapter 5 memory management system 138 5.3.2 system bus space the following three types of system bus space are available. ? system bus i/o space this corresponds to the isas i/o space. ? system bus memory space this corresponds to the isas memory space. ? high-speed system bus memory space the access speed can be set independently of the system bus memory space. there are 16 mbytes of high-speed system bus memory space. therefore, the add[25:24] pin is fixed as 10. when system bus memory has been accessed from the high-speed system bus memory space, the lcdcs# pin becomes active. the high-speed system bus memory space is used exclusively from the lcd space. to switch between these two types of space, set the isam/lcd bit in bcucntreg1. chapter 5 memory management system 139 5.3.3 internal i/o space the v r 4102 has two internal i/o spaces. each of these spaces are described below. table 5-9. internal i/o space 1 physical address internal i/o 0x0cff ffff to 0x0c00 0060 reserved for future use 0x0c00 005f to 0x0c00 0040 fir 0x0c00 003f to 0x0c00 0020 hsp (software modem interface) 0x0c00 001f to 0x0c00 0000 siu (16550) table 5-10. internal i/o space 2 physical address internal i/o 0x0bff ffff to 0x0b00 02c0 reserved for future use 0x0b00 02bf to 0x0b00 02a0 piu2 0x0b00 029f to 0x0b00 0280 reserved for future use 0x0b00 027f to 0x0b00 0260 a/d test 0x0b00 025f to 0x0b00 0240 led 0x0b00 023f to 0x0b00 0220 reserved for future use 0x0b00 021f to 0x0b00 0200 icu2 0x0b00 01ff to 0x0b00 01e0 reserved for future use 0x0b00 01df to 0x0b00 01c0 rtc2 0x0b00 01bf to 0x0b00 01a0 dsiu 0x0b00 019f to 0x0b00 0180 kiu1 0x0b00 017f to 0x0b00 0160 aiu 0x0b00 015f to 0x0b00 0140 reserved for future use 0x0b00 013f to 0x0b00 0120 piu1 0x0b00 011f to 0x0b00 0100 giu1 0x0b00 00ff to 0x0b00 00e0 dsu 0x0b00 00df to 0x0b00 00c0 rtc1 0x0b00 00bf to 0x0b00 00a0 pmu 0x0b00 009f to 0x0b00 0080 icu1 0x0b00 007f to 0x0b00 0060 cmu 0x0b00 005f to 0x0b00 0040 dcu 0x0b00 003f to 0x0b00 0020 dmaau 0x0b00 001f to 0x0b00 0000 bcu chapter 5 memory management system 140 5.3.4 lcd space this space is used to access the external lcd controller. all data that is accessed via this space is inverted-bit data. the lcd space is used exclusively from the high-speed system bus memory space. to switch between these two types of space, set the isam/lcd bit in bcucntreg1. 5.3.5 dram space the dram space differs depending on the data bus bit width and the capacity of the dram being used. ? the data bus bit width is set via the dbus32 pin. ? the dram capacity is set via the bcucntreg1s dram64 bit. the physical addresses of the dram space are listed below. table 5-11. dram addresses (when using 16-bit data bus) physical address when using 16-mbit dram when using 64-mbit dram 0x03ff ffff to 0x0200 0000 dram space reserved for future use dram space reserved for future use 0x01ff ffff to 0x0180 0000 bank 3 (mras[3]#/uucas#) 0x017f ffff to 0x0100 0000 bank 2 (mras[2]#/ulcas#) 0x00ff ffff to 0x0080 0000 bank 1 (mras[1]#) 0x007f ffff to 0x0060 0000 bank 3 (mras[3]#/uucas#) bank 0 (mras[0]#) 0x005f ffff to 0x0040 0000 bank 2 (mras[2]#/ulcas#) 0x003f ffff to 0x0020 0000 bank 1 (mras[1]#) 0x001f ffff to 0x0000 0000 bank 0 (mras[0]#) table 5-12. dram addresses (when using 32-bit data bus) physical address when using 16-mbit dram when using 64-mbit dram 0x03ff ffff to 0x0200 0000 dram space reserved for future use dram space reserved for future use 0x01ff ffff to 0x0180 0000 bank 1 (mras[1]#) 0x017f ffff to 0x0100 0000 0x00ff ffff to 0x0080 0000 bank 0 (mras[0]#) 0x007f ffff to 0x0060 0000 bank 1 (mras[1]#) 0x005f ffff to 0x0040 0000 0x003f ffff to 0x0020 0000 bank 0 (mras[0]#) 0x001f ffff to 0x0000 0000 chapter 5 memory management system 141 5.4 system control coprocessor the system control coprocessor (cp0) is implemented as an integral part of the cpu, and supports memory management, address translation, exception handling, and other privileged operations. cp0 contains the registers shown in figure 5-9 plus a 32-entry tlb. the sections that follow describe how the processor uses each of the memory management-related registers. remark each cp0 register has a unique number that identifies it; this number is referred to as the register number. see chapter 1 for details. also see chapter 6 for the cp0 functions and the relationships between exception processing and registers. figure 5-9. cp0 registers and the tlb 31 0 remark tlb (safe entries) (see random register for the tlb wired boundary.) 127/255 0 entryhi 10* entrylo0 2* index 0* context 4* badvaddr 8* compare 11* count 9* random 1* entr y lo1 3* pagemask 5* status 12* cause 13* watchlo 18* epc 14* wired 6* prid 15* watchhi 19* xcontext 20* errorepc 30* cache error 27* parity error 26* lladdr 17* taglo 28* taghi 29* config 16* *: register number used for memory management used for exception processing caution when accessing the cp0 register, some instructions require consideration of the interval time until the next instruction is executed, because it takes a while from when the contents of the cp0 register change to when this change is reflected on the cpu operation. this time lag is called cp0 hazard. for details, see chapter 28. chapter 5 memory management system 142 5.4.1 format of a tlb entry figure 5-10 shows the tlb entry formats for both 32- and 64-bit modes. each field of an entry has a corresponding field in the entryhi, entrylo0, entrylo1, or pagemask registers. figure 5-10. format of a tlb entry 114 115 96 127 107 106 (a) 32-bit mode 0 mask 0 8 2 1 21 13 8 11 64 95 75 74 73 72 71 vpn2 g 0 asid 59 60 22 4 32 63 37 38 35 34 33 0 pfn c d v 0 1 3 1 1 27 28 22 4 0 31 5 6 3 2 1 0 pfn c d v 0 1 3 1 1 210 211 192 255 203 202 (b) 64-bit mode 0 mask 0 190 189 8 2 1 2 22 29 45 8 11 128 191 139 138 137 136 135 r 0 vpn2 g 0 asid 91 92 22 36 64 127 69 70 67 66 65 0 pfn c d v 0 1 3 1 1 27 28 22 36 0 63 5 6 3 2 1 0 pfn c d v 0 1 3 1 1 167 168 the format of the entryhi, entrylo0, entrylo1, and pagemask registers are nearly the same as the tlb entry. however, it is unknown what bit of the entryhi register corresponds to the tlb g bit. chapter 5 memory management system 143 figure 5-11. format of a tlb entry (1/2) (a) pagemask register 18 19 0 31 11 10 0 mask 0 13 8 11 mask : page comparison mask, which determines the virtual page size for the corresponding entry. 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. (b) entryhi register 39 40 (a) 32-bit mode 8 3 21 0 31 11 10 8 7 vpn2 0 asid (b) 64-bit mode 62 61 8 3 2 22 29 0 63 11 10 8 7 r fill vpn2 0 asid vpn2: virtual page number divided by two (mapping to two pages) asid : address space id. an 8-bit asid field that lets multiple processes share the tlb; each process has a distinct mapping of otherwise identical virtual page numbers. r : space type (00 o user, 01 o supervisor, 11 o kernel). matches bits 63 and 62 of the virtual address. fill : reserved. ignored on write. when read, returns zero. 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 5 memory management system 144 figure 5-11. format of a tlb entry (2/2) (c) entrylo0 and entrylo1 registers 27 28 entr y lo1 entr y lo0 entr y lo1 entr y lo0 22 4 0 31 5 6 3 2 1 0 pfn c d v g 1 3 1 1 27 28 22 4 0 31 5 6 3 2 1 0 pfn c d v g 1 3 1 1 (a) 32-bit mode (b) 64-bit mode 27 28 22 36 0 63 5 6 3 2 1 0 pfn c d v g 1 3 1 1 27 28 22 36 0 63 5 6 3 2 1 0 pfn c d v g 1 3 1 1 pfn : page frame number; high-order bits of the physical address. c : specifies the tlb page attribute. d : dirty. if this bit is set to 1, the page is marked as dirty and, therefore, writable. this bit is actually a write-protect bit that software can use to prevent alteration of data. v : valid. if this bit is set to 1, it indicates that the tlb entry is valid; otherwise, a tlb invalid exception (tlbl or tlbs) occurs. g : global. if this bit is set in both entrylo0 and entrylo1, then the processor ignores the asid during tlb lookup. 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the coherency attribute (c) bits are used to specify whether to use the cache in referencing a page. when the cache is used, whether the page attribute is cached or uncached is selected by algorithm. table 5-13 lists the page attributes selected according to the value in the c bits. chapter 5 memory management system 145 table 5-13. cache algorithm c bit value cache algorithm 0 cached 1 cached 2 uncached 3 cached 4 cached 5 cached 6 cached 7 cached chapter 5 memory management system 146 5.5 cp0 registers the cp0 registers explained below are accessed by the memory management system and software. a parenthesized number that follows each register name is a register number. 5.5.1 index register (0) the index register is a 32-bit, read/write register containing five bits to index an entry in the tlb. the most- significant bit of the register shows the success or failure of a tlb probe (tlbp) instruction. the index register also specifies the tlb entry affected by tlb read (tlbr) or tlb write index (tlbwi) instructions. figure 5-12. index register 4 5 30 0 31 p 0 index 1 26 5 p : indicates whether probing is successful or not. it is set to 1 if the latest tlbp instruction fails. it is cleared to 0 when the tlbp instruction is successful. index : specifies an index to a tlb entry that is a target of the tlbr or tlbwi instruction. 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. 5.5.2 random register (1) the random register is a read-only register. the low-order 5 bits are used in referencing a tlb entry. this register is decremented each time an instruction is executed. the values that can be set in the register are as follows: ? the lower bound is the content of the wired register. ? the upper bound is 31. the random register specifies the entry in the tlb that is affected by the tlbwr instruction. the register is readable to verify proper operation of the processor. the random register is set to the value of the upper bound upon cold reset. this register is also set to the upper bound when the wired register is written. figure 5-13 shows the format of the random register. figure 5-13. random register 4 5 0 31 0 random 27 5 random : tlb random index 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 5 memory management system 147 5.5.3 entryhi (10), entryl o 0 (2), entryl o 1 (3), and pagemask (5) registers these registers are used in address translation, to rewrite tlb or to find match of tlb entry. when a tlb exception occurs, the information of the address that causes the exception is loaded into these registers. for the formats of these registers, see figure 5-11. (1) entryhi register (10) the entryhi register is read/write-accessible. it is used to access the high-order bits of built-in tlb. the entryhi register holds the high-order bits of a tlb entry for tlb read and write operations. if a tlb mismatch, tlb invalid, or tlb modified exception occurs, the entryhi register sets the virtual page number (vpn2) for a virtual address where an exception occurred and the asid. see chapter 6 for details of the tlb exception. the asid is used to read from or write to the asid field of the tlb entry. it is also checked with the asid of the tlb entry as the asid of the virtual address during address translation. the entryhi register is accessed by the tlbp, tlbwr, tlbwi, and tlbr instructions. (2) entrylo0 (2) and entrylo1 (3) registers the entrylo register consists of two registers that have identical formats: entrylo0, used for even virtual pages and entrylo1, used for odd virtual pages. the entrylo0 and entrylo1 registers are both read-/write-accessible. they are used to access the low-order bits of the built-in tlb. when a tlb read/write operation is carried out, the entrylo0 and entrylo1 registers hold the contents of the low-order 32 bits of tlb entries at even and odd addresses, respectively. (3) pagemask register (5) the pagemask register is a read/write register used for reading from or writing to the tlb; it holds a comparison mask that sets the five types of page sizes for each tlb entry, as shown in table 5-14. page sizes must be from 1 kbyte to 256 kbytes. tlb read and write instructions use this register as either a source or a destination; bits 18 to 11 that are targets of comparison are masked during address translation. table 5-14 lists the mask pattern for each page size. if the mask pattern is one not listed below, the tlb behaves unexpectedly. table 5-14. mask values and page sizes page size bit 18 17 16 15 14 13 12 11 1 kbyte 00000000 4 kbytes 00000011 16 kbytes 00001111 64 kbytes 00111111 256 kbytes 1 1 1 11111 chapter 5 memory management system 148 5.5.4 wired register (6) the wired register is a read/write register that specifies the lower boundary of the random entry of the tlb as shown in figure 5-14. wired entries cannot be overwritten by a tlbwr instruction. they can, however, be overwritten by a tlbwi instruction. random entries can be overwritten by both instructions. figure 5-14. positions indicated by the wired register 0 31 value in the wired register range of wired entries range specified by the random register the wired register is set to 0 upon cold reset. writing this register also sets the random register to the value of its upper bound (see 5.5.2 random register (1)). figure 5-15 shows the format of the wired register. figure 5-15. wired register 4 5 0 31 0 wired 27 5 wired : tlb wired boundary 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 5 memory management system 149 5.5.5 processor revision identifier (prid) register (15) the 32-bit, read-only processor revision identifier (prid) register contains information identifying the implementation and revision level of the cpu and cp0. figure 5-16 shows the format of the prid register. figure 5-16. prid register 15 16 7 8 0 31 0 imp rev 16 8 8 imp : cpu core processor id number (0x0c for the v r 4102) rev : cpu core processor revision number 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the processor revision number is stored as a value in the form y.x, where y is a major revision number in bits 7 to 4 and x is a minor revision number in bits 3 to 0. the processor revision number can distinguish some cpu core revisions, however there is no guarantee that changes to the cpu core will necessarily be reflected in the prid register, or that changes to the revision number necessarily reflect real cpu core changes. therefore, create a program that does not depend on the processor revision number area. chapter 5 memory management system 150 5.5.6 config register (16) the config register indicates and specifies various configuration options selected on v r 4102 processors. some configuration options, as defined by the ec and be fields, are set by the hardware during cold reset and are included in the config register as read-only status bits for the software to access. other configuration options (ad, ep, and k0 fields) can be read/written and controlled by software; on cold reset these fields are undefined. since only a subset of the v r 4000 options are available in the v r 4102, some bits are set to constants (e.g., bits 14:13) that were variable in the v r 4000. the config register should be initialized by software before caches are used. figure 5-17 shows the format of the config register. figure 5-17. config register format 1 1 1 23 5 1 1 22 17 18 15 16 14 1 3 4 28 30 24 27 31 0 ec ep ad 0 1 0 be 1 1 13 0 1 12 cs 3 11 9 ic 3 8 6 dc 3 5 3 0 3 2 0 k0 ec : system interface clock ratio (read only) 000 o processor clock frequency divided by 2 others o reserved ep : transfer data pattern (cache write-back pattern) 0000 o dd: 1 word/1 cycle others o reserved ad : accelerate data mode setting 0 o v r 4000 series compatible mode 1 o reserved be : bigendianmem. indicates endian. 0 o little endian 1 o reserved cs : cache size mode indication 0 o reserved 1 o cache of small capacity ic : instruction cache size indication. the size is 2 (10+ic) bytes when cs bit is set to 1. 2 o 4 kbytes others o reserved dc : data cache size indication. the size is 2 (10+dc) bytes when cs bit is set to 1. 0 o 1 kbytes others o reserved k0 : kseg0 cache coherency algorithm 010 o uncached others o cached 1: 1 is returned when it is read. 0: 0 is returned when it is read. chapter 5 memory management system 151 caution the value that can be set is different from that of the v r 4100. be sure to set the ep field and the ad bit to 0. if they are set with any other values, the processor may behave unexpectedly. 5.5.7 load linked address (lladdr) register (17) the read/write load linked address (lladdr) register is a read/write register, and not used with the v r 4102 processor except for diagnostic purpose, and serves no function during normal operation. lladdr register is implemented just for compatibility between the v r 4102 and v r 4000/v r 4400. figure 5-18. lladdr register 0 31 paddr 32 paddr: 32-bit physical address chapter 5 memory management system 152 5.5.8 cache tag registers (taglo (28) and taghi (29)) the taglo and taghi registers are 32-bit read/write registers that hold the primary cache tag and parity during cache initialization, cache diagnostics, or cache error processing. the tag registers are written by the cache and mtc0 instructions. the p fields of these registers are ignored on index store tag operations by the cache instruction. parity is computed by the store operation. figure 5-19 shows the format of these registers. figure 5-19. taglo and taghi registers 22 0 31 10 9 8 7 1 2 6 ptaglo v d w 0 w p 1 1 1 1 1 5 22 0 31 10 9 8 1 ptaglo v 0 p 1 1 8 0 31 0 32 instruction cache data cache tag hi ptaglo: specifies physical address bits 31 to 10. v : valid bit d : dirty bit. however, this bit is defined only for the compatibility with the v r 4000 series processors, and does not indicate the status of cache memory in spite of its readability and writability. this bit cannot change the status of cache memory. w : write-back bit (set if cache line has been updated) w : even parity for the write-back bit p : even parity bit for primary cache tag 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 5 memory management system 153 5. 5 .9 virtual-to-physical address translation during virtual-to-physical address translation, the cpu compares the 8-bit asid (and while the global bit , g, is not set to 1) of the virtual address to the asid of the tlb entry to see if there i s a match . on e o f th e following comparisons are also made: ? in 32-bit mode, the high-order bits no t e of the 32-bit virtual address are compared to the contents of the vpn2 (virtual page number divided by two) of each tlb entry. ? in 64-bit mode, the high-order bits no t e of the 64-bit virtual address are compared to the content s o f th e r and the vpn2 (virtual page number divided by two) of each tlb entry. i f a tl b entr y matches , the physical address and access control bits (c, d, and v) are retrieved from the matching tlb entry. while the v bit of the entry must be set to 1 for a valid address translation to take place, it is not involved in the determination of a matching tlb entry. figure 5-20 illustrates the tlb address translation flow. not e the number of bits differs from page sizes. the table below shows the examples of high-order bits of the virtual address in page size of 256 kbytes and 1 kbytes. page s i z e mode 256 kb y tes 1 kb y tes 32-bit mode bits 31 to 19 bits 31 to 11 64-bit mode bits 63, 62, 39 to 19 bits 63, 62, 39 to 11 chapter 5 memory management system 154 figure 5-20. tlb address translation virtual address (input) vpn and asid exception exception exception exception exception exception physical address (output) address error no yes yes yes no yes yes no legal address? supervisor mode? user mode? legal address? address error legal address? address error no no yes yes yes mapped address? no vpn match? dirty valid global no g = 1? no v = 1? yes yes no d = 1? no yes uncached area? no asid match? no 32-bit address? yes yes tlb mismatch xtlb mismatch tlb invalid no no yes write? tlb modified access main memory access cache memory exception chapter 5 memory management system 155 5. 5 .10 tlb misses if there is no tlb entry that matches the virtual address, a tlb refil l (miss ) exceptio n occurs no t e . if the access control bits (d and v) indicate that the access is not valid, a tlb modified or tlb invalid exception occurs. if th e c bit is 010, the retrieved physical address directly accesses main memory, bypassing the cache. not e see chapter 6 for details of the tlb miss exception. 5. 5 .11 tlb instructions the instructions used for tlb control are described below. (1 ) t ranslation lookaside buffer probe (tlbp) the translation lookaside buffer probe (tlbp) instruction loads the index register with a tl b numbe r that matches the content of the entryhi register. if there i s n o tl b numbe r tha t matche s th e tl b entry , th e highest- order bit of the index register is set. (2 ) t ranslation lookaside buffer read (tlbr) th e translatio n lookasid e buffe r read (tlbr) instruction loads the entryhi, entrylo0, entrylo1, and pagemask registers with the content of the tlb entry indicated by the content of the index register. (3 ) t ranslation lookaside buffer write index (tlbwi) the translation lookaside buffer write index (tlbwi) instructio n write s th e content s o f th e entryhi , entrylo0, entrylo1, and pagemask registers to the tlb entry indicated by the content of the index register. (4 ) t ranslation lookaside buffer write random (tlbwr) th e translatio n lookaside buffer write random (tlbwr) instruction writes the contents of the entryhi, entrylo0, entrylo1, and pagemask registers to the tlb entry indicated by the content of the random register. 156 [memo] 157 chapter 6 exception processing this chapter describes cpu exception processing, including an explanation of hardware that processes exceptions, followed by the format and use of each cpu exception register. the chapter concludes with a description of each exceptions cause, together with the manner in which the cpu processes and services each exception. 6.1 how exception processing works the processor receives exceptions from a number of sources, including translation lookaside buffer (tlb) misses, arithmetic overflows, i/o interrupts, and system calls. when the cpu detects an exception, the normal sequence of instruction execution is suspended and the processor enters kernel mode (see chapter 5 for a description of system operating modes). the processor then disables interrupts and transfers control for execution to the exception handler (located at a specific address as an exception handling routine implemented by software). the handler saves the context of the processor, including the contents of the program counter, the current operating mode (user or supervisor), statuses, and interrupt enabling. this context is saved so it can be restored when the exception has been serviced. when an exception occurs, the cpu loads the exception program counter (epc) register with a location where execution can restart after the exception has been serviced. the restart location in the epc register is the address of the instruction that caused the exception or, if the instruction was executing in a branch delay slot, the address of the branch instruction immediately preceding the delay slot. the v r 4102 processor supports a supervisor mode and fast tlb refill for all address spaces. the v r 4102 also provides the following functions: ? interrupt enable (ie) bit ? operating mode (user, supervisor, or kernel) ? exception level (normal or exception is indicated by the exl bit in the status register) ? error level (normal or error is indicated by the erl bit in the status register). interrupts are enabled when the following conditions are satisfied: (1) interrupt enable an interrupt is enabled when the following conditions are satisfied. x interrupt enable bit (ie) = 1 x exl bit = 0, erl bit = 0 x corresponding im field bits in the status register = 1 chapter 6 exception proc essing 158 (2) operating mode the operating mode is specified by ksu bit in the status register when both the exception level and error level are normal (0). (3) exception/error levels the operation enters kernel mode when either exl bit or erl bit in the status register is set to 1. returning from an exception resets the exception level to normal (0) (for details, see chapter 27). the registers that retain address, cause, and status information during exception processing are described in 6.3 exception processing registers . for a description of the exception process, see 6.4 details of exceptions . 6.2 precision of exceptions v r 4102 exceptions are logically precise; the instruction that causes an exception and all those that follow it are aborted and can be re-executed after servicing the exception. when succeeding instructions are killed, exceptions associated with those instructions are also killed. exceptions are not taken in the order detected, but in instruction fetch order. there is a special case in which the v r 4102 processor may not be able to restart easily after servicing an exception. when a cache data parity error exception occurs on a load with a cache hit, the v r 4102 processor does not prevent the cache data (with erroneous parity) from being written back into the register file during the wb stage. the exception is still precise, since both the epc and cacheerror registers are updated with the correct virtual address pointing to the offending load instruction, and the exception handler can still determine the cause of exception and its origin. the program can be restarted by rewriting the destination register - not automatically, however, as in the case of all the other precise exceptions where no status change occurs. chapter 6 exception proc essing 159 6.3 exception processing registers this section describes the cp0 registers that are used in exception processing. table 6-1 lists these registers, along with their number-each register has a unique identification number that is referred to as its register number. the cp0 registers not listed in the table are used in memory management (see chapter 5 for details). the exception handler examines the cp0 registers during exception processing to determine the cause of the exception and the state of the cpu at the time the exception occurred. the registers in table 6-1 are used in exception processing, and are described in the sections that follow. table 6-1. cp0 exception processing registers register name register number context register 4 badvaddr register 8 count register 9 compare register 11 status register 12 cause register 13 epc register 14 watchlo register 18 watchhi register 19 xcontext register 20 parity error register 26 cache error register 27 errorepc register 30 chapter 6 exception proc essing 160 6.3.1 context register (4) the context register is a read/write register containing the pointer to an entry in the page table entry (pte) array on the memory; this array is a table that stores virtual-to-physical address translations. when there is a tlb miss, the operating system loads the unsuccessfully translated entry from the pte array to the tlb. the context register is used by the tlb refill exception handler for loading tlb entries. the context register duplicates some of the information provided in the badvaddr register, but the information is arranged in a form that is more useful for a software tlb exception handler. figure 6-1 shows the format of the context register. figure 6-1. context register format (a) 32-bit mode 4 21 7 0 24 24 25 31 4 3 ptebase badvpn2 0 (b) 64-bit mode 4 21 39 0 25 63 4 3 ptebase badvpn2 0 ptebase : the ptebase field is a read/write field. it is used by software as the pointer to the base address of the pte table in the current user address space. badvpn2 : the badvpn2 field is written by hardware if a tlb miss occurs. this field holds the value (vpn2) obtained by halving the virtual page number of the most recent virtual address for which translation failed. 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the 21-bit badvpn2 field contains bits 31-11 of the virtual address that caused the tlb miss; bit 10 is excluded because a single tlb entry maps to an even-odd page pair. for a 1-kbyte page size, this format can directly address the pair-table of 8-byte ptes. when the page size is 4 kbytes or more, shifting or masking this value produces the correct pte reference address. chapter 6 exception proc essing 161 6.3.2 badvaddr register (8) the bad virtual address (badvaddr) register is a read-only register that saves the most recent virtual address that failed to have a valid translation, or that had an addressing error. figure 6-2 shows the format of the badvaddr register. caution this register saves no information after a bus error exception, because it is not an address error exception. figure 6-2. badvaddr register format (a) 32-bit mode 32 0 31 badvaddr (b) 64-bit mode (b) 64-bit mode 64 0 63 badvaddr badvaddr: most recent virtual address for which an addressing error occurred, or for which address translation failed 6.3.3 count register (9) the read/write count register acts as a timer. it is incremented in synchronization with the masterout clock, regardless of whether instructions are being executed, retired, or any forward progress is actually made through the pipeline. this register is a free-running type. when the register reaches all ones, it rolls over to zero and continues counting. this register is used for self-diagnostic test, system initialization, or the establishment of inter-process synchronization. figure 6-3 shows the format of the count register. figure 6-3. count register format 32 0 31 count count: 32-bit up-date count value that is compared with the value of the compare register chapter 6 exception proc essing 162 6.3.4 compare register (11) the compare register causes a timer interrupt; it maintains a stable value that does not change on its own. when the value of the count register (see 6.3.3) equals the value of the compare register, the ip(7) bit in the cause register is set. this causes an interrupt as soon as the interrupt is enabled. writing a value to the compare register, as a side effect, clears the timer interrupt request. for diagnostic purposes, the compare register is a read/write register. normally, this register should be only used for a write. figure 6-4 shows the format of the compare register. figure 6-4. compare register format 32 0 31 compare compare: value that is compared with the count value of the count register 6.3.5 status register (12) the status register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. figure 5-5 shows the format of the status register. figure 5-6 shows the details of the diagnostic status (ds) field. all ds field bits other than the ts bit are writable. figure 6-5. status register format 29 28 27 26 25 24 16 15 8 7 6 5 4 3 2 1 0 31 0 cu0 0 re ds im (7:0) kx sx ux ksu erl 1 2 1 3 9 exl ie 8 1 1 1 2 1 1 1 cu0 : enables/disables the use of the coprocessor (1 o enabled, 0 o disabled). cp0 can be used by the kernel at all times. 0 : reserved for future use. write 0 in a write operation. when this bit is read, 0 is read. re : enables/disables reversing of the endian setting in user mode (0 o disabled, 1 o enabled). this bit must be set to 0 since the v r 4102 supports the little-endian order only. ds : diagnostic status field (see figure 6-6). im : interrupt mask field used to enable/disable interrupts (0 o disabled, 1 o enabled). this field consists of 8 bits that are used to control eight interrupts. the bits are assigned to interrupts as follows: im7 : masks a timer interrupt. im(6:2) : mask ordinary interrupts (int(4:0) note ). however, int4 note never occur in the v r 4102. im(1:0) : mask software interrupts or cause register ip(1:0). note int(4:0) are internal signals of the v r 4100 cpu core. for details about connection to the on- chip peripheral units, refer to chapter 14. chapter 6 exception proc essing 163 kx : enables 64-bit addressing in kernel mode (0 o 32-bit, 1 o 64-bit). if this bit is set, an xtlb refill exception occurs if a tlb miss occurs in the kernel mode address space. sx : enables 64-bit addressing and operation in supervisor mode (0 o 32-bit, 1 o 64-bit). if this bit is set, an xtlb refill exception occurs if a tlb miss occurs in the supervisor mode address space. ux: : enables 64-bit addressing and operation in user mode (0 o 32-bit, 1 o 64-bit). if this bit is set, an xtlb refill exception occurs if a tlb miss occurs in the user mode address space. ksu : sets and indicates the operating mode (10 o user, 01 o supervisor, 00 o kernel). erl : sets and indicates the error level (0 o normal, 1 o error). exl : sets and indicates the exception level (0 o normal, 1 o exception). ie : sets and indicates interrupt enabling/disabling (0 o disabled, 1 o enabled). figure 6-6. status register diagnostic status field 16 17 18 19 20 21 22 23 24 0 bev ts sr 0 ch ce de 1 1 1 1 1 1 1 2 bev : specifies the base address of a tlb refill exception vector and common exception vector (0 o normal, 1 o bootstrap). ts : occurs the tlb to be shut down (read-only) (0 o not shut down, 1 o shut down). this bit is used to avoid any problems that may occur when multiple tlb entries match the same virtual address. after the tlb has been shut down, reset the processor to enable restart. note that the tlb is shut down even if a tlb entry matching a virtual address is marked as being invalid (with the v bit cleared). sr : occurs a soft reset or nmi exception (0 o not occurred, 1 o occurred). ch : cp0 condition bit (0 o false, 1 o true). this bit can be read and written by software only; it cannot be accessed by hardware. ce : when ce = 1, the contents of the perr register are written to the check bits of the cache (see 6.3.10) de : specifies whether a cache parity error causes an exception (0 o enable parity check, 1 o disable parity check). 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the status register has the following fields where the modes and access status are set. chapter 6 exception proc essing 164 (1) interrupt enable interrupts are enabled when all of the following conditions are true: ? ie is set to 1. ? exl is cleared to 0. ? erl is cleared to 0. ? the appropriate bit of the im is set to 1. (2) operating modes the following status register bit settings are required for user, kernel, and supervisor modes. ? the processor is in user mode when ksu = 10, exl = 0, and erl = 0. ? the processor is in supervisor mode when ksu = 01, exl = 0, and erl = 0. ? the processor is in kernel mode when ksu = 00, exl = 1, or erl = 1. (3) 32- and 64-bit modes the following status register bit settings select 32- or 64-bit operation for user, kernel, and supervisor operating modes. enabling 64-bit operation permits the execution of 64-bit opcodes and translation of 64-bit addresses. 64-bit operation for user, kernel and supervisor modes can be set independently. ? 64-bit addressing for kernel mode is enabled when kx bit = 1. 64-bit operations are always valid in kernel mode. ? 64-bit addressing and operations are enabled for supervisor mode when sx bit = 1. ? 64-bit addressing and operations are enabled for user mode when ux bit = 1. (4) kernel address space accesses access to the kernel address space is allowed when the processor is in kernel mode. (5) supervisor address space accesses access to the supervisor address space is allowed when the processor is in supervisor or kernel mode. (6) user address space accesses access to the user address space is allowed in any of the three operating modes. (7) status after reset the contents of the status register are undefined after resets, except for the following bits. x ts and sr are cleared to 0. x erl and bev are set to 1. x sr is 0 after cold reset, and is 1 after soft reset or nmi interrupt. remark cold reset and soft reset are cpu core reset (see 7.4 reset of the cpu core ). for the reset of all the v r 4102 including peripheral units, refer to chapter 7 initialization interface and chapter 15 pmu . chapter 6 exception proc essing 165 6.3.6 cause register (13) the 32-bit read/write cause register holds the cause of the most recent exception. a 5-bit exception code indicates one of the causes (see table 6-2). other bits holds the detailed information of the specific exception. all bits in the cause register, with the exception of the ip1 and ip0 bits, are read-only; ip1 and ip0 are used for software interrupts. figure 6-7 shows the fields of this register; table 6-2 describes the cause register codes. figure 6-7. cause register format 8 27 16 15 6 7 2 1 0 12 8 1 5 2 31 30 29 28 bd 0 ce 2 1 1 0 ip(7..0) 0 exccode 0 bd : indicates whether the most recent exception occurred in the branch delay slot (1 ? in delay slot, 0 ? normal). ce : indicates the coprocessor number in which a coprocessor unusable exception occurred. this field will remain undefined for as long as no exception occurs. ip : indicates whether an interrupt is pending (1 ? interrupt pending, 0 ? no interrupt pending). im7 : a timer interrupt. im(6:2) : ordinary interrupts (int(4:0) note ). however, int4 note never occurs in the v r 4102. im(1:0) : software interrupts. only these bits cause an interrupt exception, when they are set to 1 by means of software. note int(4:0) are internal signals of the v r 4100 cpu core. for details about connection to the on- chip peripheral units, refer to chapter 14. exccode : exception code field (refer to table 6-2 for details) 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 6 exception proc essing 166 table 6-2. cause register exception code field exception code mnemonic description 0 int interrupt exception 1 mod tlb modified exception 2 tlbl tlb refill exception (load or fetch) 3 tlbs tlb refill exception (store) 4 adel address error exception (load or fetch) 5 ades address error exception (store) 6 ibe bus error exception (instruction fetch) 7 dbe bus error exception (data load or store) 8 sys system call exception 9 bp breakpoint exception 10 ri reserved instruction exception 11 cpu coprocessor unusable exception 12 ov integer overflow exception 13 tr trap exception 14 to 22 reserved for future use 23 watch watch exception 24 to 31 reserved for future use the v r 4102 has eight interrupt request sources, ip7 to ip0. for the detailed description of interrupts, refer to chapter 9. (1) ip7 this bit indicates whether there is a timer interrupt request. it is set when the values of count register and compare register match. (2) ip6 to ip2 ip6 to ip2 reflect the state of the interrupt request signal of the cpu core. (3) ip1 and ip0 these bits are used to set/clear a software interrupt request. chapter 6 exception proc essing 167 6.3.7 exception program counter (epc) register (14) the exception program counter (epc) is a read/write register that contains the address at which processing resumes after an exception has been serviced. the epc register contains either: ? virtual address of the instruction that was the direct cause of the exception ? virtual address of the immediately preceding branch or jump instruction (when the instruction associated with the exception is in a branch delay slot, and the bd bit in the cause register is set to 1). the exl bit in the status register is set to 1 to keep the processor from overwriting the address of the exception- causing instruction contained in the epc register in the event of another exception. figure 6-8 shows the format of the epc register. figure 6-8. epc register format (a) 32-bit mode 32 0 31 epc (b) 64-bit mode 64 0 63 epc epc: restart address after exception processing chapter 6 exception proc essing 168 6.3.8 watchlo (18) and watchhi (19) registers the v r 4102 processor provides a debugging feature to detect references to a selected physical address; load and store instructions to the location specified by the watchlo and watchhi registers cause a watch exception. figures 5-9 and 5-10 show the format of the watchlo and watchhi registers. figure 5-9. watchlo and watchhi register format 29 3 2 1 0 31 paddr0 0 r w 1 1 1 32 0 31 0 watchlo register watchhi register paddr0 : specifies physical address bits 31 to 3. r : if this bit is set to 1, an exception will occur when a load instruction is executed. w : if this bit is set to 1, an exception will occur when a store instruction is executed. 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 6 exception proc essing 169 6.3.9 xcontext register (20) the read/write xcontext register contains a pointer to an entry in the page table entry (pte) array, an operating system data structure that stores virtual-to-physical address translations. if a tlb miss occurs, the operating system loads the untranslated data from the pte into the tlb to handle the software error. the xcontext register is used by the xtlb refill exception handler to load tlb entries in 64-bit addressing mode. the xcontext register duplicates some of the information provided in the badvaddr register, and puts it in a form useful for the xtlb exception handler. this register is included solely for operating system use. the operating system sets the ptebase field in the register, as needed. figure 6-10 shows the format of the xcontext register. figure 6-10. xcontext register format 32 4 2 29 29 0 35 34 33 63 4 3 ptebase r badvpn2 0 ptebase : the ptebase field is a read/write field, and is used by software as the pointer to the base address of the pte table in the current user address space. badvpn2 : the badvpn2 field is written by hardware if a tlb miss occurs. this field holds the value (vpn2) obtained by halving the virtual page number of the most recent virtual address for which translation failed. r : space type (00 o user, 01 o supervisor, 11 o kernel). the setting of this field matches virtual address bits 63 and 62. 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the 29-bit badvpn2 field has bits 39 to 11 of the virtual address that caused the tlb miss; bit 10 is excluded because a single tlb entry maps to an even-odd page pair. for a 1-kbyte page size, this format may be used directly to address the pair-table of 8-byte ptes. for 4-kbyte-or-more page and pte sizes, shifting or masking this value produces the appropriate address. chapter 6 exception proc essing 170 6.3.10 parity error register (26) the read/write parity error (perr) register contains the cache data parity bits for cache initialization, cache diagnostics, or cache error processing. the perr register is loaded by the index_load_tag cache instruction. all bits of the parity field are valid on the data cache operation because data cache employs byte parity (1-bit parity for 1 byte). but a lsb of the parity field is valid on the instruction cache operation because instruction cache employs word parity (1-bit parity for 1 word). the contents of the perr register are: ? written into the on-chip data cache on store instructions (instead of the computed parity) when the ce bit of the status register is set to 1 ? substituted for the computed parity for the cache fill instruction in the v r 4102, parity check is performed only for cache memory. it is not performed for main memory or peripheral units. figure 6-11 shows the format of the perr register. figure 6-11. parity error register format 8 24 0 31 8 7 0 parity parity : specifies the 8-bit parity data to be read from or written to the on-chip cache. 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 6 exception proc essing 171 6.3.11 cache error register (27) the 32-bit read/write cache error (cacheerr) register processes parity errors in the on-chip cache. parity errors cannot be corrected by on-chip hardware. the cacheerr register holds cache index and status bits that indicate the cause of the error. in the v r 4102, parity check is performed only for cache memory. it is not performed for main memory or peripheral units. figure 6-12 shows the format of the cacheerr register. figure 6-12. cacheerr register format 31 30 29 28 27 26 25 24 11 10 0 14 11 er 0 ed et 0 ee eb 0 pidx 1 1 1 1 1 1 1 er : reference type (0 o instruction, 1 o data) ed : indicates whether an error occurred in the data field (0 o normal, 1 o error). et : indicates whether an error occurred in the tag field (0 o normal, 1 o error). ee : this bit is set if an error occurs on the sysad bus. eb : this bit is set if a data error occurs subsequent to an instruction error. (the error status is indicated by the remaining bit positions.) in this case, the data cache must be flushed upon the completion of instruction error processing. pidx: cache index 0 : reserved for future use. write 0 in a write operation. when this field is read, 0 is read. 6.3.12 errorepc register (30) the error exception program counter (errorepc) register is similar to the epc register. it is used to store the program counter value at which the cache error, cold reset, soft reset, or nmi exception has been serviced. the read/write errorepc register contains the virtual address at which instruction processing can resume after servicing an error. this address can be: ? the virtual address of the instruction that caused the error exception ? the virtual address of the immediately preceding branch or jump instruction, when the instruction associated with the error exception is in a branch delay slot. the contents of the errorepc register do not change when the erl bit of the status register is set to 1. this prevents the processor when other exceptions occur from overwriting the address of the instruction in this register which causes an error exception. there is no branch delay slot indication for the errorepc register. figure 6-13 shows the format of the errorepc register. chapter 6 exception proc essing 172 figure 6-13. the errorepc register format (a) 32-bit mode 32 0 31 errorepc (b) 64-bit mode 64 0 63 errorepc errorepc: restart address after parity error exception processing. also indicates the value of the program counter when cold reset, soft reset, or nmi exceptions occurred. chapter 6 exception proc essing 173 6.4 details of exceptions this section describes causes, processes, and services of the v r 4102s exceptions. 6.4.1 exception types this section gives sample exception handler operations for the following exception types: ? cold reset ? soft reset ? nmi ? cache error ? remaining processor exceptions when the exl and erl bits in the status register are 0, either user, supervisor, or kernel operating mode is specified by the ksu bits in the status register. when either the exl or erl bit is set to 1, the processor is in kernel mode. when the processor takes an exception, the exl bit is set to 1, meaning the system is in kernel mode. after saving the appropriate state, the exception handler typically resets the exl bit back to 0. the exception handler sets the exl bit to 1 so that the saved state is not lost upon the occurrence of another exception while the saved state is being restored. returning from an exception also resets the exl bit to 0. for details, see chapter 27. 6.4.2 exception vector locations the cold reset, soft reset, and nmi exceptions are always branched to the following reset exception vector address (virtual). this address is in an uncached, unmapped space. ? 0xbfc0 0000 in 32-bit mode ? 0xffff ffff bfc0 0000 in 64-bit mode addresses for the remaining exceptions are a combination of a vector offset and a base address. 64-/32-bit mode exception vectors and their offsets are shown below. chapter 6 exception proc essing 174 table 6-3. 64-bit mode exception vector base addresses vector base address (virtual) vector offset cold reset soft reset nmi 0xffff ffff bfc0 0000 (bev is automatically set to 1) 0x0000 cache error 0xffff ffff a000 0000 (bev = 0) 0xffff ffff bfc0 0200 (bev = 1) 0x0100 tlb refill (exl = 0) 0xffff ffff 8000 0000 (bev = 0) 0x0000 xtlb refill (exl = 1) 0xffff ffff bfc0 0200 (bev = 1) 0x0080 other exceptions 0x0180 table 6-4. 32-bit mode exception vector base addresses vector base address (virtual) vector offset cold reset soft reset nmi 0xbfc0 0000 (bev is automatically set to 1) 0x0000 cache error 0xa000 0000 (bev = 0) 0xbfc0 0200 (bev = 1) 0x0100 tlb refill (exl = 0) 0x8000 0000 (bev = 0) 0x0000 xtlb refill (exl = 1) 0xbfc0 0200 (bev = 1) 0x0080 other exceptions 0x0180 examples 1. tlb refill exception vector when bev bit = 0, the vector base address (virtual) for the tlb refill exception is in kseg0 (unmapped) space. ? 0x8000 0000 in 32-bit mode ? 0xffff ffff 8000 0000 in 64-bit mode when bev bit = 1, the vector base address (virtual) for the tlb refill exception is in kseg1 (uncached, unmapped) space. ? 0xbfc0 0200 in 32-bit mode ? 0xffff ffff bfc0 0200 in 64-bit mode this is an uncached, non-tlb-mapped space, allowing the exception handler to bypass the cache and tlb. chapter 6 exception proc essing 175 example 2. cache error exception vector when bev bit = 0, the vector base address (virtual) for the cache error exception is in kseg1 (uncached, unmapped) space. ? 0xa000 0000 in 32-bit mode ? 0xffff ffff a000 0000 in 64-bit mode when bev bit = 1, the vector base address (virtual) for the cache error exception is in kseg1 (uncached, unmapped) space. ? 0xbfc0 0200 in 32-bit mode ? 0xffff ffff bfc0 0200 in 64-bit mode this is an uncached, non-tlb-mapped space, allowing the exception handler to bypass the cache and tlb. chapter 6 exception proc essing 176 6.4.3 priority of exceptions while more than one exception can occur for a single instruction, only the exception with the highest priority is reported. table 6-5 lists the priorities. table 6-5. exception priority order priority exceptions high n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ p low cold reset soft reset nmi address error (instruction fetch) tlb/xtlb refill (instruction fetch) tlb invalid (instruction fetch) cache error (instruction fetch) bus error (instruction fetch) system call breakpoint coprocessor unusable reserved instruction trap integer overflow address error (data access) tlb/xtlb refill (data access) tlb invalid (data access) tlb modified (data write) cache error (data access) watch bus error (data access) interrupt (other than nmi) hereafter, handling exceptions by hardware is referred to as process, and handling exception by software is referred to as service. chapter 6 exception proc essing 177 6.4.4 cold reset exception cause the cold reset exception occurs when the coldreset# signal (internal) is asserted and then deasserted. this exception is not maskable. the reset# signal (internal) must be asserted along with the coldreset# signal (for details, see chapter 7). processing the cpu provides a special interrupt vector for this exception: 0xbfc0 0000 (virtual) in 32-bit mode 0xffff ffff bfc0 0000 (virtual) in 64-bit mode the cold reset vector resides in unmapped and uncached cpu address space, so the hardware need not initialize the tlb or the cache to process this exception. it also means the processor can fetch and execute instructions while the caches and virtual memory are in an undefined state. the contents of all registers in the cpu are undefined when this exception occurs, except for the following register fields: when erl bit of the status register is 0, the program counters value at the exception occurrence is saved to the epc register. ts and sr of the status register are cleared to 0. erl and bev of the status register are set to 1. the random register is initialized to the value of its upper bound (31) (refer to 5.4.2 random register (1) ). the wired register is initialized to 0. bits 31 to 28 of the config register are set to 0, and bits 22 to 3 to 0x04800. all other bits are undefined. servicing the cold reset exception is serviced by: initializing all processor registers, coprocessor registers, tlb, caches, and the memory system performing diagnostic tests bootstrapping the operating system chapter 6 exception proc essing 178 6.4.5 soft reset exception cause a soft reset (sometimes called warm reset) occurs when the coldreset# signal remains deasserted while the reset# signal goes from assertion to deassertion (for details, see chapter 7). a soft reset immediately resets all state machines, and sets the sr bit of the status register. execution begins at the reset vector when the reset is deasserted. this exception is not maskable. caution in the v r 4102, a soft reset never occurs. processing the cpu provides a special interrupt vector for this exception (same location as cold reset): g 0xbfc0 0000 (virtual) in 32-bit mode g 0xffff ffff bfc0 0000 (virtual) in 64-bit mode this vector is located within unmapped and uncached address space, so that the cache and tlb need not be initialized to process this exception. the sr bit of the status register is set to 1 to distinguish this exception from a cold reset exception. when this exception occurs, the contents of all registers are preserved except for the following registers: g when erl bit of the status register is 0, the program counters value at the exception occurrence is saved to the epc register. g ts bit of the status register is cleared to 0. g erl, sr, and bev bits of the status register are set to 1. during a soft reset, access to the operating cache or system interface is aborted. this means that the contents of the cache and memory will be undefined if a soft reset occurs. servicing the soft reset exception is serviced by: g preserving the current processor states for diagnostic tests g reinitializing the system in the same way as for a cold reset exception chapter 6 exception proc essing 179 6.4.6 nmi exception cause the nonmaskable interrupt (nmi) exception occurs in response to the input of the nmi signal (internal). this interrupt is not maskable; it occurs regardless of the settings of the exl, erl, and the ie bits in the status register (for details, see chapters 9 and 14). processing the cpu provides a special interrupt vector for this exception: g 0xbfc0 0000 (virtual) in 32-bit mode g 0xffff ffff bfc0 0000 (virtual) in 64-bit mode this vector is located within unmapped and uncached address space so that the cache and tlb need not be initialized to process an nmi interrupt. the sr bit of the status register is set to 1 to distinguish this exception from a cold reset exception. unlike cold reset and soft reset, but like other exceptions, nmi is taken only at instruction boundaries. the states of the caches and memory system are preserved by this exception. when this exception occurs, the contents of all registers are preserved except for the following registers: g when erl bit of the status register is 0, the program counters value at the exception occurrence is saved to the epc register. g the ts bit of the status register is cleared to 0. g the erl, sr, and bev bits of the status register are set to 1. servicing the nmi exception is serviced by: g preserving the current processor states for diagnostic tests g reinitializing the system in the same way as for a cold reset exception chapter 6 exception proc essing 180 6.4.7 address error exception cause the address error exception occurs when an attempt is made to execute one of the following. this exception is not maskable. execution of the lw, lwu, sw, or cache instruction for word data that is not located on a word boundary execution of the lh, lhu, or sh instruction for half-word data that is not located on a half-word boundary execution the ld or sd instruction for double-word data that is not located on a double-word boundary referencing the kernel address space in user or supervisor mode referencing the supervisor space in user mode referencing an address that does not exist in the kernel, user, or supervisor address space in 64-bit kernel, user, or supervisor mode branching to an address that is not located on a word boundary processing the common exception vector is used for this exception. the adel or ades code in the cause register is set. if this exception has been caused by an instruction reference or load operation, adel is set. if it has been caused by a store operation, ades is set. when this exception occurs, the badvaddr register stores the virtual address that was not properly aligned or was referenced in protected address space. the contents of the vpn field of the context and entryhi registers are undefined, as are the contents of the entrylo register. the epc register contains the address of the instruction that caused the exception, unless this instruction is in a branch delay slot. if it is in a branch delay slot, the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing the kernel reports the unix tm sigsegv (segmentation violation) signal to the current process, and this exception is usually fatal. chapter 6 exception proc essing 181 6.4.8 tlb exceptions three types of tlb exceptions can occur: tlb refill exception occurs when there is no tlb entry that matches a referenced address. a tlb invalid exception occurs when a tlb entry that matches a referenced virtual address is marked as being invalid (with the v bit set to 0). the tlb modified exception occurs when a tlb entry that matches a virtual address referenced by the store instruction is marked as being valid (with the v bit set to 1). the following three sections describe these tlb exceptions. (1) tlb refill exception (32-bit space mode)/xtlb refill exception (64-bit space mode) cause the tlb refill exception occurs when there is no tlb entry to match a reference to a mapped address space. this exception is not maskable. processing there are two special exception vectors for this exception; one for references to 32-bit address spaces, and one for references to 64-bit address spaces. the ux, sx, and kx bits of the status register determine whether the user, supervisor or kernel address spaces referenced are 32-bit or 64-bit spaces. when the exl bit of the status register is set to 0, either of these two special vectors is referenced. when the exl bit is set to 1, the common exception vector is referenced. this exception sets the tlbl or tlbs code in the exccode field of the cause register. if this exception has been caused by an instruction reference or load operation, tlbl is set. if it has been caused by a store operation, tlbs is set. when this exception occurs, the badvaddr, context, xcontext and entryhi registers hold the virtual address that failed address translation. the entryhi register also contains the asid from which the translation fault occurred. the random register normally contains a valid location in which to place the replacement tlb entry. the contents of the entrylo register are undefined. the epc register contains the address of the instruction that caused the exception, unless this instruction is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing to service this exception, the contents of the context or xcontext register are used as a virtual address to fetch memory words containing the physical page frame and access control bits for a pair of tlb entries. the memory word is written into the tlb entry by using the entrylo0, entrylo1, or entryhi register. it is possible that the physical page frame and access control bits are placed in a page where the virtual address is not resident in the tlb. this condition is processed by allowing a tlb refill exception in the tlb refill exception handler. in this case, the common exception vector is used because the exl bit of the status register is set to 1. chapter 6 exception proc essing 182 (2) tlb invalid exception cause the tlb invalid exception occurs when the tlb entry that matches with the virtual address to be referenced is invalid (the v bit is set to 0). this exception is not maskable. processing the common exception vector is used for this exception. the tlbl or tlbs code in the exccode field of the cause register is set. if this exception has been caused by an instruction reference or load operation, tlbl is set. if it has been caused by a store operation, tlbs is set. when this exception occurs, the badvaddr, context, xcontext, and entryhi registers contain the virtual address that failed address translation. the entryhi register also contains the asid from which the translation fault occurred. the random register normally stores a valid location in which to place the replacement tlb entry. the contents of the entrylo register are undefined. the epc register contains the address of the instruction that caused the exception unless this instruction is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing usually, the v bit of a tlb entry is cleared in the following cases: when a virtual address does not exist when the virtual address exists, but is not in main memory (a page fault) when a trap is required on any reference to the page (for example, to maintain a reference bit) after servicing the cause of a tlb invalid exception, the tlb entry is located with a tlbp (tlb probe) instruction, and replaced by an entry with its valid bit set to 1. chapter 6 exception proc essing 183 (3) tlb modified exception cause the tlb modified exception occurs when the tlb entry that matches with the virtual address referenced by the store instruction is valid (bit v is 1) but is not writable (bit d is 0). this exception is not maskable. processing the common exception vector is used for this exception, and the mod code in the exccode field of the cause register is set. when this exception occurs, the badvaddr, context, xcontext, and entryhi registers contain the virtual address that failed address translation. the entryhi register also contains the asid from which the translation fault occurred. the contents of the entrylo register are undefined. the epc register contains the address of the instruction that caused the exception unless that instruction is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing the kernel uses the failed virtual address or virtual page number to identify the corresponding access control bits. the page identified may or may not permit write accesses; if writes are not permitted, a write protection violation occurs. if write accesses are permitted, the page frame is marked dirty (/writable) by the kernel in its own data structures. the tlbp instruction places the index of the tlb entry that must be altered into the index register. the word data containing the physical page frame and access control bits (with the d bit set to 1) is loaded to the entrylo register, and the contents of the entryhi and entrylo registers are written into the tlb. chapter 6 exception proc essing 184 6.4.9 cache error exception cause the cache error exception occurs when a cache parity error is detected. this exception is not maskable, but error detection can be disabled by setting the de bit of the status register. if a parity error is detected when the de bit of status register is not set, a cache error exception is taken during one of the following operations: an instruction fetch from instruction cache a load from the data cache tag parity check on a store main memory read by the processor most of the cache instructions (no exception is taken for the index_load_tag and index_store_tag cache instructions) in the v r 4102, the parity error from the external bus and on-chip peripheral buses is not checked. processing the processor sets the erl bit in the status register, saves the address to recover from the exception to the errorepc register, and then transfers to a special vector in uncached space. if the bev bit = 0, the vector is one of the following: ? 0xa000 0100 (virtual) in 32-bit mode ? 0xffff ffff a000 0100 (virtual) in 64-bit mode if the bev bit = 1, the vector is one of the following: ? 0xbfc0 0300 (virtual) in 32-bit mode ? 0xffff ffff bfc0 0300 (virtual) in 64-bit mode servicing all errors should be logged. to correct cache parity errors, the system uses the cache instruction to invalidate the cache block, overwrites the old data through a cache miss, and resumes execution with an eret instruction. other errors are not correctable and are likely to be fatal to the current process. chapter 6 exception proc essing 185 6.4.10 bus error exception cause a bus error exception is raised by board-level circuitry for events such as bus time-out, local bus parity errors, and invalid physical memory addresses or access types. this exception is not maskable. a bus error exception occurs only when a cache miss refill, uncached reference, or unbuffered write occurs synchronously. in other words, it occurs when an illegal access is detected during bcu read. for details of illegal accesses, refer to 10.4.6 illegal access notification . processing the common interrupt vector is used for a bus error exception. the ibe or dbe code in the exccode field of the cause register is set, signifying whether the instruction caused the exception by an instruction reference, load operation, or store operation. the epc register contains the address of the instruction that caused the exception, unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing the physical address at which the fault occurred can be computed from information available in the system control coprocessor (cp0) registers. if the ibe code in the cause register is set (indicating an instruction fetch), the virtual address is contained in the epc register (or 4 + the contents of the epc register if the bd bit of the cause register is set to 1). if the dbe code is set (indicating a load or store), the virtual address of the instruction that caused the exception (the address of the preceding branch instruction if the bd bit of the cause register is set to 1) is saved to the epc register (or 4 + the contents of the epc register if the bd bit of the cause register is set to 1). the virtual address of the load and store instruction can then be obtained by interpreting the instruction. the physical address can be obtained by using the tlbp instruction and reading the entrylo register to compute the physical page number. at the time of this exception, the kernel reports the unix sigbus (bus error) signal to the current process, but the exception is usually fatal. chapter 6 exception proc essing 186 6.4.11 system call exception cause a system call exception occurs during an attempt to execute the syscall instruction. this exception is not maskable. processing the common exception vector is used for this exception, and the sys code in the exccode field of the cause register is set. the epc register contains the address of the syscall instruction unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction. if the syscall instruction is in a branch delay slot, the bd bit of the status register is set to 1; otherwise this bit is cleared. servicing when this exception occurs, control is transferred to the applicable system routine. to resume execution, the epc register must be altered so that the syscall instruction does not re-execute; this is accomplished by adding a value of 4 to the epc register before returning. if a syscall instruction is in a branch delay slot, interpretation of the branch instruction is required to resume execution. 6.4.12 breakpoint exception cause a breakpoint exception occurs when an attempt is made to execute the break instruction. this exception is not maskable. processing the common exception vector is used for this exception, and the bp code in the exccode field of the cause register is set. the epc register contains the address of the break instruction unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction. if the break instruction is in a branch delay slot, the bd bit of the status register is set to 1; otherwise this bit is cleared. servicing when the breakpoint exception occurs, control is transferred to the applicable system routine. additional distinctions can be made by analyzing the unused bits of the break instruction (bits 25 to 6), and loading the contents of the instruction whose address the epc register contains. a value of 4 must be added to the contents of the epc register to locate the instruction if it resides in a branch delay slot. to resume execution, the epc register must be altered so that the break instruction does not re-execute; this is accomplished by adding a value of 4 to the epc register before returning. if a break instruction is in a branch delay slot, interpretation (decoding) of the branch instruction is required to resume execution. chapter 6 exception proc essing 187 6.4.13 coprocessor unusable exception cause the coprocessor unusable exception occurs when an attempt is made to execute a coprocessor instruction for either: a corresponding coprocessor unit that has not been marked usable (status register bit, cu[0] = 0), or cp0 instructions, when the unit has not been marked usable (status register bit, cu[0] = 0) and the process executes in user or supervisor mode. this exception is not maskable. processing the common exception vector is used for this exception, and the cpu code in the exccode field of the cause register is set. the ce bit of the cause register indicates which of the four coprocessors was referenced. the epc register contains the address of the coprocessor instruction that causes an exception unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing the coprocessor unit to which an attempted reference was made is identified by the ce bit of the cause register. one of the following processing is performed by the handler: if the process is entitled access to the coprocessor, the coprocessor is marked usable and the corresponding state is restored to the coprocessor. if the process is entitled access to the coprocessor, but the coprocessor does not exist or has failed, interpretation of the coprocessor instruction is possible. if the bd bit in the cause register is set to 1, the branch instruction must be interpreted; then the coprocessor instruction can be emulated and execution resumed with the epc register advanced past the coprocessor instruction. if the process is not entitled access to the coprocessor, the kernel reports unix sigill/ill_privin_fault (illegal instruction/privileged instruction fault) signal to the current process, and this exception is fatal. chapter 6 exception proc essing 188 6.4.14 reserved instruction exception cause the reserved instruction exception occurs when an attempt is made to execute one of the following instructions: ? instruction with an undefined major opcode (bits 31 to 26) ? special instruction with an undefined minor opcode (bits 5 to 0) ? regimm instruction with an undefined minor opcode (bits 20 to 16) ? 64-bit instructions in 32-bit user or supervisor mode 64-bit operations are always valid in kernel mode regardless of the value of the kx bit in the status register. this exception is not maskable. processing the common exception vector is used for this exception, and the ri code in the exccode field of the cause register is set. the epc register contains the address of the reserved instruction unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing all currently defined mips isa instructions can be executed. the process executing at the time of this exception is handled by a unix sigill/ill_resop_fault (illegal instruction/reserved operand fault) signal. this error is usually fatal. 6.4.15 trap exception cause the trap exception occurs when a tge, tgeu, tlt, tltu, teq, tne, tgei, tgeui, tlti, tltui, teqi, or tnei instruction results in a true condition. this exception is not maskable. processing the common exception vector is used for this exception, and the tr code in the exccode field of the cause register is set. the epc register contains the address of the trap instruction causing the exception unless the instruction is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing at the time of a trap exception, the kernel reports the unix sigfpe/fpe_intovf_trap (floating-point exception/integer overflow) signal to the current process, but the exception is usually fatal. chapter 6 exception proc essing 189 6.4.16 integer overflow exception cause an integer overflow exception occurs when an add, addi, sub, dadd, daddi or dsub instruction results in a 2s complement overflow. this exception is not maskable. processing the common exception vector is used for this exception, and the ov code in the exccode field of the cause register is set. the epc register contains the address of the instruction that caused the exception unless the instruction is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing at the time of the exception, the kernel reports the unix sigfpe/fpe_intovf_trap (floating-point exception/integer overflow) signal to the current process, and this exception is usually fatal. 6.4.17 watch exception cause a watch exception occurs when a load or store instruction references the physical address specified by the watchlo/watchhi registers. the watchlo/watchhi registers specify whether a load or store or both could have initiated this exception. when the r bit of the watchlo register is set to 1: load instruction when the w bit of the watchlo register is set to 1: store instruction when both the r bit and w bit of the watchlo register are set to 1: load instruction or store instruction the cache instruction never causes a watch exception. the watch exception is postponed while the exl bit in the status register is set to 1, and watch exception is only maskable by setting the exl bit in the status register to 1. processing the common exception vector is used for this exception, and the watch code in the exccode field of the cause register is set. the epc register contains the address of the load or store instruction that caused the exception unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. chapter 6 exception proc essing 190 servicing the watch exception is a debugging aid; typically the exception handler transfers control to a debugger, allowing the user to examine the situation. to continue, once the watch exception must be disabled to execute the faulting instruction. the watch exception must then be reenabled. the faulting instruction can be executed either by the debugger or by setting breakpoints. 6.4.18 interrupt exception cause the interrupt exception occurs when one of the eight interrupt conditions note is asserted. in the v r 4102, interrupt requests from internal peripheral units first enter the icu and are then notified to the cpu core via one of four interrupt sources (int [3:0]) or nmi. each of the eight interrupts can be masked by clearing the corresponding bit in the im field of the status register, and all of the eight interrupts can be masked at once by clearing the ie bit of the status register or setting the exl/erl bit. note: they are 1 timer interrupt, 5 ordinary interrupts, and 2 software interrupts. of the five ordinary interrupts, int4 is never asserted active. processing the common exception vector is used for this exception, and the int code in the exccode field of the cause register is set. the ip field of the cause register indicates current interrupt requests. it is possible that more than one of the bits can be simultaneously set (or cleared) if the interrupt request signal is asserted and then deasserted before this register is read. the epc register contains the address of the instruction that caused the exception unless it is in a branch delay slot, in which case the epc register contains the address of the preceding branch instruction and the bd bit of the cause register is set to 1. servicing if the interrupt is caused by one of the two software-generated exceptions (sw0 or sw1), the interrupt condition is cleared by setting the corresponding cause register bit to 0. if the interrupt is caused by hardware, the interrupt condition is cleared by deactivating the corresponding interrupt request signal. chapter 6 exception proc essing 191 6.5 exception processing and servicing flowcharts the remainder of this chapter contains flowcharts for the following exceptions and guidelines for their handlers: ? common exceptions and a guideline to their exception handler ? tlb/xtlb refill exception and a guideline to their exception handler ? cache error exception ? cold reset, soft reset and nmi exceptions, and a guideline to their handler. generally speaking, the exceptions are "processed by hardware (hw); the exceptions are then serviced by software (sw). chapter 6 exception proc essing 192 figure 6-14. common exception handler (1/2) (a) processing exceptions other than cold reset, soft reset, nmi, tlb/xtlb mismatch, and cache error exceptions (hardware) instruction in branch delay slot? bd bit ? 0 epc ? pc exl ? 1 bev entryhi ? vpn2, asid x/context ? vpn2 set cause register (exccode, ce) bd bit ? 1 epc ? pc C 4 no yes ; kernel mode is set, and interrupts are disabled. pc ? 0xffff ffff bfc0 0200 + 180 (unmapped, uncached space) pc ? 0xffff ffff 8000 0000 + 180 (unmapped, cacheable space) to guideline of general exception handler = 0 (normal) = 1 (bootstrap) exl = 1? (sr1) yes no start ; check for multiple exceptions ; badvaddr is set only when a tlb mismatch, tlb invalid, or tlb modified exception occurs. (badvaddr is not set when a bus error exception occurs. ; the entryhi and x/context registers are set only when a tlb mismatch, tlb invalid, or tlb modified exception occurs. remark the exceptions can be masked by the ie or im bit. the watch exception can be set to pending status by setting the exl bit. chapter 6 exception proc essing 193 figure 6-14. common exception handler (2/2) (b) guideline of general exception handler (software) ts bit = 0? (sr21) execute mfc0 instruction x/context register epc register status register cause register execute mtc0 instruction (status bit setting) ksu bit ? 00 exl bit ? 0 ie bit = 1 servicing by each exception routine exl = 1 execute mtc0 instruction epc register status register eret no yes the processor is reset (in kernel mode, interrupts are enabled.) ; the register files are saved. check the cause register, and jump to each routine guideline of general exception handler ; the occurance of tlb mismatch, tlb invalid, and tlb modified exceptions is disabled by using an unmapped space. ; the occurance of the watch and interrupt exceptions is disabled by setting exl = 1. ; other exceptions are avoided in the os programs ; however, the cache error, cold reset, soft reset, and nmi exceptions are enabled. ; after exl = 0 is set, all exceptions are enabled (except for the interrupt exception masked by ie or im and the cache error exception masked by de. ; the execution of the eret instruction is disabled in the branch delay slots of the other jump instructions. ; the processor does not execute an instruction in the branch delay slot of the eret instruction. : pc ? epc, exl ? 0 chapter 6 exception proc essing 194 figure 6-15. tlb/xtlb refill exception handler (1/2) (a) hardware instruction in branch delay slot? exl ? 1 bev (sr22) exl = 0? (sr1) exl = 0? (sr1) no yes ; check for multiple exceptions. xtlb exception? xtlb mismatch vector offset = 0x080 tlb mismatch vector offset = 0x000 general exception vector offset = 0x180 ; kernel mode is set and interrpts are disabled. = 0 (normal) = 1 (bootstrap) yes no no yes no yes start entryhi ? vpn2, asid x/context ? vpn2 set cause register (exccode) entryhi ? vpn2, asid x/context ? vpn2 set cause register (exccode) bd bit ? 1 epc ? pc C 4 bd bit ? 0 epc ? pc pc ? 0xffff ffff 8000 0000 + vector offset (unmapped, cacheable space) pc ? 0xffff ffff bfc0 0200 + vector offset (unmapped, uncached space) to guideline of tlb/xtlb exception hadler chapter 6 exception proc essing 195 figure 6-15. tlb/xtlb refill exception handler (2/2) (b) guideline of tlb/xtlb exception handler (software) execute mfc0 instruction x/context register eret servicing by each exceoption routine guideline of tlb/xtlb exception handler ; the occurence of tlb mismatch, tlb invalid, and tlb modified exception is disabled by using an unmapped space. ; the occurence of the watch and interrupt exceptions is disabled by setting exl = 1. ; other exceptions are avoided in the os programs. ; however, the cache error, cold reset, soft reset, and nmi exceptions are enabled. ; the physical address for a virtual address loaded into the x/context register is loaded into the entrylo register and written to the tlb. ; as long as a data/instruction address exists in the mapping space, another tlb mismatch exception may occur. in such a case, exl = 1 is set, causing a jump to the common exception vector. (in this case, the common exception handler handles the tlb miss or the eret instruction returns control to the user program, then a tlb mismatch exception is generated again.) ; the execution of the eret instruction is disabled in the branch delay slots of other jump instructions. ; the processor does not execute an instruction in the branch delay slot of the eret instruction. ; pc ? epc, exl ? 0 chapter 6 exception proc essing 196 figure 6-16. cache error exception handler the cache error exception can be masked by setting the de (sr16) bit to 1. when erl = 1, cache error exceptions are masked. instruction in branch delay slot? set cache error register no yes bd bit ? 1 error epc ? pc C 4 bd bit ? 0 error epc ? pc bev (sr22) pc ? 0xffff ffff a000 0000 + 100 (unmapped, uncached space) = 0 (normal) = 1 (bootstrap) erl ? 1 servicing by exception routine eret remark pc ? 0xffff ffff bfc0 0200 + 100 (unmapped, uncached space) start hardware software no yes erl = 1? (sr2) ; check for multple exceptions ; the execution of the eret instruction is disabled in the branch delay slots of other jump instructions. ; the processor does not execute an instruction in the branch delay slot of the eret instruction. ; pc ? error epc, erl ? 0 ; the cache error and tlb-related error exceptions do not occur because of unmapped/uncache vector. ; the occurence of the watch and interrupt exceptions is disabled by setting erl = 1. ; other exceptions are avoided in the os programs. ; however, the cold reset, soft reset, and nmi exceptions are enabled. chapter 6 exception proc essing 197 figure 6-17. cold reset, soft reset, and nmi exception handler set status register bev bit ? 1 ts bit ? 0 sr bit ? 1 erl bit ? 1 random register ? 31 wired register ? 0 update config register bits 31:28 22:6 set status register bev bit ? 1 ts bit ? 0 sr bit ? 0 erl bit ? 1 soft reset or nmi exception pc ? 0xffff ffff bfc0 0000 nmi? yes sr = 1? (sr20) no yes servicing by soft reset exception routine servicing by cold reset exception routine servicing by nmi exception routine eret no ; the processor provides no means of distinguishing between an nmi exception and soft reset exception, such that this must be determined at the system level. software hardware no yes erl = 1? (sr2) no yes no yes no yes instruction in branch delay slot? bd bit ? 1 error epc ? pc C 4 bd bit ? 0 error epc ? pc cold reset exception erl = 1? (sr2) instruction in branch delay slot? bd bit ? 1 error epc ? pc C 4 bd bit ? 0 error epc ? pc 198 [memo] 199 chapter 7 initialization interface this chapter describes the initialization interface and processor modes. it also explains the reset signal descriptions and types, signal- and timing-related dependence, and the initialization sequence during each mode that can be selected by the user. remark # that follows signal names indicates active low. 7.1 reset function there are five ways to reset the v r 4102. each is summarized below. 7.1.1 rtc reset during power-on, set the rtcrst# pin as active. after waiting (about 600 ms) for the 32.768-khz oscillator to begin oscillating when the power supply is stable at 3.0 v or above, setting the rtcrst# pin as inactive causes the rtc unit to begin counting. next, when the power pin, dcd# pin, or gpio[3] pin becomes inactive, the v r 4102 asserts the poweron pin and uses the battinh/battint# signal to perform a battery level check. if the battery checks result is ok, the v r 4102 asserts the mpower pin and waits for the stabilization time period (about 350 ms) for the external agents dc/dc converter, then begins pll oscillation and starts all clocks (a period of about 16 ms following the start of pll oscillation is required for stabilization of pll oscillation). an rtc reset does not save any of the status information and it completely initializes the processors internal state. since the dram is not switched to self refresh mode, the contents of dram after an rtc reset are not at all guaranteed. after a reset, the processor becomes the system bus master and it begins the cold reset exception sequence to access the reset vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4102, the processor should be completely initialized by software. chapter 7 initialization interface 200 figure 7-1. rtc reset reset#(internal) coldreset#(internal) mpower(o) power(i) rtcrst#(i) rtc (internal , 32khz) stable oscillation 16ms 350ms >600ms undefined pll(internal) 16masterclock note >32ms poweron(o) undefined stable oscillation note masterclock is the basic clock used in the cpu core. chapter 7 initialization interface 201 7.1.2 rstsw after the rstsw# pin becomes active and then becomes inactive 100 p s later, the v r 4102 starts pll oscillation and starts all clocks (a period of about 16 ms following the start of pll oscillation is required for stabilization of pll oscillation). a reset by rstsw initializes the entire internal state except for the rtc timer and the pmu. since the dram is not switched to self refresh mode, the contents of dram after an rtc reset are not at all guaranteed. after a reset, the processor becomes the system bus master and it begins the cold reset exception sequence to access the reset vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4102, the processor should be completely initialized by software. figure 7-2. rstsw h l reset#(internal) coldreset#(internal mpower(o) power(i) rtc (internal, 32khz) stable oscillation 16masterclock note 16ms >3rtc pll(internal) undefined rstsw#(i) mras(0:3)#(o) ucas#/lcas#(o) stable oscillation stable oscillation note masterclock is the basic clock used in the cpu core. chapter 7 initialization interface 202 7.1.3 deadmans switch after the deadmans switch unit is enabled, if the deadmans switch is not cleared within the specified time period, the v r 4102 is immediately returned to reset status. setting and clearing of the deadmans switch is performed by software. a reset by the deadmans switch initializes the entire internal state except for the rtc timer and the pmu. since the dram is not switched to self refresh mode, the contents of dram after a deadmans switch reset are not at all guaranteed. after a reset, the processor becomes the system bus master and it begins the cold reset exception sequence to access the reset vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4102, the processor should be completely initialized by software. figure 7-3. deadmans switch l h h reset#(internal) coldreset#(internal) mpower(o) power(i) rstsw#(i) rtc (internal, 32khz) 16masterclock note 16ms pll(internal) undefined stable oscillation stable oscillation stable oscillation note masterclock is the basic clock used in the cpu core. chapter 7 initialization interface 203 7.1.4 software shutdown when the software executes the hibernate instruction, the v r 4102 sets the dram to self refresh mode and sets the mpower pin as inactive, then enters reset status. recovery from reset status occurs when the power pin is asserted, when a wakeuptimer interrupt occurs, or when the dcd# pin is asserted. a reset by software shutdown initializes the entire internal state except for the rtc timer and the pmu. after a reset, the processor becomes the system bus master and it begins the cold reset exception sequence to access the reset vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4102, the processor should be completely initialized by software. figure 7-4. software shutdown reset#(internal) coldreset#(internal) mpower(o) power(i) mras(0:3)#/ ucas#/lcas# (o) rtc (internal, 32khz) stable oscillation 16masterclock note 16ms 350ms undefined pll(internal) >32ms poweron(o) stopped stable oscillation note masterclock is the basic clock used in the cpu core. chapter 7 initialization interface 204 7.1.5 haltimer shutdown after an rtc reset is canceled, if the hal timer is not canceled by software within about four seconds (the haltimerrst bit of the pmucntreg register is not set to 1), the v r 4102 enters reset status. recovery from reset status occurs when the power pin is asserted or when a wakeuptimer interrupt occurs. a reset by hal timer initializes the entire internal state except for the rtc timer and the pmu. after a reset, the processor becomes the system bus master and it begins the cold reset exception sequence to access the reset vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4102, the processor should be completely initialized by software. figure 7-5. haltimer shutdown reset#(internal) coldreset#(internal mpower(o) power(i) mras(0:3)#/ ucas#/lcas# (o) rtc (internal, 32khz) 16masterclock note 16ms 350ms 4s undefined pll(internal) >32ms stable oscillation poweron(o) stopped stable oscillation note masterclock is the basic clock used in the cpu core. chapter 7 initialization interface 205 7.2 poweron sequence the factors that cause the v r 4102 to switch from hibernate mode or shutdown mode to full speed mode are called power-on factors. there are four power-on factors: assertion of the poweron pin, assertion of the dcd# pin, activation of the wakeup timer, and assertion of the gpio pins (gpio[3..0], gpio[12..9]). when an activation factor occurs, the v r 4102 asserts the poweron pin, then provides notification to external agents that the v r 4102 is ready for power-on. three rtc clocks after the poweron pin is asserted, the v r 4102 checks the state of the battinh/battint# pin. if the battinh/battint# pins state is low, the poweron pin is deasserted one rtc clock after the battinh/battint# pin check is completed, then the v r 4102 is not activated. if the battinh/battint# pins state is high, the poweron pin is deasserted three rtc clocks after the battinh/battint# pin check is completed, then the mpower pin is asserted and the v r 4102 is activated. figure 7-6 shows a timing chart of v r 4102 activation and figure 7-7 shows a timing chart of when activation fails due to the battinh/battint# pins low state. for details of poweron sequence according to each power-on factor, refer to chapter 15. chapter 7 initialization interface 206 figure 7-6. v r 4102 activation sequence (when battery check is ok) reset#(internal) coldreset#(internal) mpower(o) activation of cpu check battinh/ battint# pin detection of activation factor rtc (internal, 32khz) pll(internal) poweron(o) battinh/battint#(i) stopped undefined stable oscillation figure 7-7. v r 4102 activation sequence (when battery check is ng) reset#(internal) coldreset#(internal) mpower(o) cpu not activated check battinh/ battint# pin detection of activation rtc (internal, 32khz) pll(internal) poweron(o) battinh/battint#(i) l l l h chapter 7 initialization interface 207 7.3 reset of the cpu core this section describes the reset sequence of the v r 4100 cpu core. for details about factors of reset or reset of the whole v r 4102, refer to 7.1 and chapter 15. 7.3.1 cold reset in the v r 4102, a cold reset sequence is executed in the cpu core in the following cases: x rtc reset x rstsw reset x deadmans sw shutdown x software shutdown x hal timer shutdown x battery low shutdown x battery lock release shutdown a cold reset completely initializes the cpu core, except for the following register bits. x the ts and sr bits of the status register are cleared to 0. x the erl and bev bits of the status register are set to 1. x the upper limit value (31) is set in the random register. x the wired register is initialized to 0. x bits 31 to 28 of the config register are set to 0 and bits 22 to 3 to 0x04800; the other bits are undefined. x the values of the other registers are undefined. once power to the processor is established, the coldreset# (internal) and the reset# (internal) signals are asserted and a cold reset is started. after approximately 2 ms assertion, the coldreset# signal is deasserted synchronously with masterout. then the reset# signal is deasserted synchronously with masterout, and the cold reset is completed. upon reset, the cpu core becomes bus master and drives the sysad bus (internal). after reset# is deasserted, the cpu core branches to the reset exception vector and begins executing the reset exception code. chapter 7 initialization interface 208 7.3.2 soft reset caution soft reset is not supported in the present v r 4102. a soft reset initializes the cpu core without affecting the clocks; in other words, a soft reset is a logic reset. in a soft reset, the cpu core retains as much state information as possible; all state information except for the following is retained: x the ts bit of the status register is cleared to 0. x the sr, erl and bev bits of the status register are set to 1. x the count register is initialized to 0. x the ip7 bit of the cause register is cleared to 0. x any interrupts generated on the sysad bus are cleared. x nmi is cleared. x the config register is initialized. a soft reset is started by assertion of the reset# signal, and is completed at the deassertion of the reset# signal synchronized with masterout. in general, data in the cpu core is preserved for debugging purpose. upon reset, the cpu core becomes bus master and drives the sysad bus (internal). after reset# is deasserted, the cpu core branches to the reset exception vector and begins executing the reset exception code. chapter 7 initialization interface 209 figure 7-8. cold reset reset# (internal) coldreset# (internal) tclock (internal) masterout (internal) v dd masterclock n ote (internal) undefined undefined note masterclock is the basic clock used in the cpu core. figure 7-9. soft reset reset# (internal) tclock (internal) masterout (internal) v dd masterclock n ote (internal) h note masterclock is the basic clock used in the cpu core. chapter 7 initialization interface 210 7.4 v r 4102 processor modes the v r 4102 supports various modes, which can be selected by the user. the cpu core mode is set each time a write occurs in the status register and config register. the on-chip peripheral unit mode is set by writing to the i/o register. this section describes the cpu cores operation modes. for operation modes of on-chip peripheral units, see the chapters describing the various units. 7.4.1 power modes the v r 4102 supports four power modes: fullspeed mode, standby mode, suspend mode, and hibernate mode. (1) fullspeed mode this is the normal operation mode. the v r 4102s default status sets operation under fullspeed mode. after the processor is reset, the v r 4102 returns to fullspeed mode. (2) standby mode when a standby instruction has been executed, the processor can be set to standby mode. during standby mode, all of the internal clocks in the cpu core except for the timer and interrupt clocks are held at high level. the peripheral units all operate as they do during fullspeed mode. this means that dma operations are enabled during standby mode. when the standby instruction completes the wb stage, the v r 4102 remains idle until the sysad internal bus enters the idle state. next, the clocks in the cpu core are shut down and pipeline operation is stopped. however, the pll, timer, and interrupt clocks continue to operate, as do the internal bus clocks (tclock and masterout). during standby mode, the processor is returned to fullspeed mode if any interrupt occurs, including a timer interrupt that occurs internally. (3) suspend mode when the suspend instruction has been executed, the processor can be set to suspend mode. during suspend mode, the processor stalls the pipeline and supplying all of the internal clocks in the cpu core except for pll timer and interrupt clocks are stopped. the v r 4102 stops supplying tclock to peripheral units. accordingly, during suspend mode peripheral units can only be activated by a special interrupt unit (dcd# control, etc.). while in this mode, the register and cache contents are retained. when the suspend instruction completes the wb stage, the v r 4102 switches the dram to self refresh mode and then waits for the sysad internal bus to enter the idle state. next, the clocks in the cpu core are shut down and pipeline operation is stopped. the v r 4102 then stops supplying tclock to peripheral units. however, the pll, timer, and interrupt clocks continue to operate, as do the masterout. the processor remains in suspend mode until an interrupt is received, at which time it returns to fullspeed mode. chapter 7 initialization interface 211 (4) hibernate mode when the hibernate instruction has been executed, the processor can be set to hibernate mode. during hibernate mode, the processor stops supplying clocks to all units. the register and cache contents are retained and output of tclock and masterout is stopped. the processor remains in hibernate mode until the power pin is asserted, a wakeuptimer interrupt occurs, dcd# pin is asserted, or gpio[3] is asserted, at which the processor returns to fullspeed mode. power consumption during hibernate mode is about 0 w (it does not go completely to 0 w due to the existence of a 32.768-khz oscillator, on-chip peripheral units that operate at 32.768 khz, or dram self refresh). 7.4.2 privilege mode the v r 4102 supports three system modes: kernel expanded addressing mode, supervisor expanded addressing mode, and user expanded addressing mode. these three modes are described below. (1) kernel expanded addressing mode when the status registers kx bit has been set, an expanded tlb miss exception vector is used when a tlb miss occurs for the kernel address. while in kernel mode, the mips iii operation code can always be used, regardless of the kx bit. (2) supervisor expanded addressing mode when the status registers sx bit has been set, the mips iii operation code can be used when in supervisor mode and an expanded tlb miss exception vector is used when a tlb miss occurs for the supervisor address. (3) user expanded addressing mode when the status registers ux bit has been set, the mips iii operation code can be used when in user mode, and an expanded tlb miss exception vector is used when a tlb miss occurs for the user address. when this bit is cleared, the mips i and ii operation codes can be used, as can 32-bit virtual addresses. 7.4.3 reverse endian when the status registers re bit has been set, the endian ordering is reversed to adopt the user softwares perspective. however, the re bit of the status register must be set to 0 since the v r 4102 supports the little-endian order only. 7.4.4 bootstrap exception vector (bev) the bev bit is used to generate an exception during operation testing (diagnostic testing) of the cache and main memory system. this bit is automatically set to 1 after reset or nmi exception. when the status registers bev bit has been set, the address of the tlb miss exception vector is changed to the virtual address 0xffff ffff bfc0 0200 and the ordinary execution vector is changed to address 0xffff ffff bfc0 0380. when the bev bit is cleared, the tlb miss exception vectors address is changed to 0xffff ffff 8000 0000 and the ordinary execution vector is changed to address 0xffff ffff 8000 0180. chapter 7 initialization interface 212 7.4.5 cache error check when the status registers ce bit has been set, the contents of the perr register can be written to the data caches parity bit instead of the parity generated by the store instruction. if the cache instructions fill option is executed, the contents of the perr register can be written to the instruction caches parity bit instead of the instruction parity. 7.4.6 parity error prohibit when the status registers de bit has been set, the processor does not issue any cache parity error exceptions. 7.4.7 interrupt enable (ie) when the status registers ie bit has been cleared, no interrupts can be received except for reset interrupts and nonmaskable interrupts. 213 chapter 8 cache memory this chapter describes in detail the cache memory: its place in the v r 4100 cpu core memory organization, and individual organization of the caches. this chapter uses the following terminology: ? the data cache may also be referred to as the d-cache. ? the instruction cache may also be referred to as the i-cache. these terms are used interchangeably throughout this book. 8.1 memory organization figure 8-1 shows the v r 4100 cpu core system memory hierarchy. in the logical memory hierarchy, the caches lie between the cpu and main memory. they are designed to make the speedup of memory accesses transparent to the user. each functional block in figure 8-1 has the capacity to hold more data than the block above it. for instance, physical main memory has a larger capacity than the caches. at the same time, each functional block takes longer to access than any block above it. for instance, it takes longer to access data in main memory than in the cpu on- chip registers. figure 8-1. logical hierarchy of memory v r 4100 cpu core register register i-cache d-cache cache main memory disc, cd-rom, tape, etc. register cache memory memory media faster access time increasing data capacity chapter 8 cache memory 214 the v r 4100 cpu core has two on-chip caches: one holds instructions (the instruction cache), the other holds data (the data cache). the instruction and data caches can be read in one pclock cycle. data writes are pipelined and can complete at a rate of one per pclock cycle. in the first stage of the cycle, the store address is translated and the tag is checked; in the second stage, the data is written into the data ram. 8.2 cache organization this section describes the organization of the on-chip data and instruction caches. figure 8-2 provides a block diagram of the v r 4100 cpu core cache and memory model. figure 8-2. cache support v r 4100 cpu core cache controller i-cache d-cache caches main memory i-cache: instruction cache d-cache: data cache (1) cache line lengths a cache line is the smallest unit of information that can be fetched from main memory for the cache, and that is represented by a single tag. the line size for the instruction/data cache is 4 words (16 bytes). for cache tag, refer to 8.2.1 and 8.2.1 . (2) cache sizes the instruction cache in the v r 4100 cpu core is 4 kbytes; the data cache is 1 kbytes. 8.2.1 organization of the instruction cache (i-cache) each line of i-cache data (although it is actually an instruction, it is referred to as data to distinguish it from its tag) has an associated 24-bit tag that contains a 22-bit physical address, a single valid bit, and a single parity bit. word parity is used on i-cache data (1 bit of parity per word). the v r 4100 cpu core i-cache has the following characteristics: ? direct-mapped ? indexed with a virtual address ? checked with a physical tag ? organized with a 4-word (16-byte) cache line. figure 8-3 shows the format of a 4-word (16-byte) i-cache line. chapter 8 cache memory 215 figure 8-3. cache line format p v ptag datap data datap data datap data datap data 23 22 21 0 22 11 32 31 0 ptag physical tag (bits 31 to 10 of the physical address) when a tag is specified by the cache instruction, however, the high-order 20 bits are used. v valid bit p even parity for the ptag and v bit data i-cache data datap even parity for the data (1-bit parity for 4-byte data) 8.2.2 organization of the data cache (d-cache) each line of d-cache data has an associated 26-bit tag that contains a 22-bit physical address, a valid bit, a parity bit, a write-back bit, and a parity bit for write-back. the v r 4100 cpu core d-cache has the following characteristics : ? write-back ? direct-mapped ? indexed with a virtual address ? checked with a physical tag ? organized with a 4-word (16-byte) cache line. figure 8-4 shows the format of a 4-word (16-byte) d-cache line. figure 8-4. data cache line format w w datap data datap data 23 22 21 0 22 11 71 63 0 ptag physical tag (bits 31 to 10 of the physical address) v valid bit p even parity for the ptag and v bit w write-back bit (set if cache line has been written) w even parity for the write-back bit data d-cache data datap even parity for the data (1-bit parity for 4-byte data) p v ptag 25 24 11 64 chapter 8 cache memory 216 8.2.3 accessing the caches figure 8-5 shows the virtual address (va) index into the caches. the number of virtual address bits used to index the instruction and data caches depends on the cache size. (1) data cache addressing this addressing uses bits va [9:4]. the most significant bit is va9 because the cache size is 1 kbyte. the least significant bit is va4 because the line size is 4 words (16 bytes). (2) instruction cache addressing this addressing uses bits va [11:4]. the most significant bit is va11 because the cache size is 4 kbytes. the least significant bit is va4 because the line size is 4 words (16 bytes). figure 8-5. cache data and tag organization tags tag line tags tags tags data tag line data line p v tag w data 64 va (9:4) for 1-kbyte d-cache and va (11:4) for 4-kbyte i-cache chapter 8 cache memory 217 8.3 cache operations as described earlier, caches provide fast temporary data storage, and they make the speedup of memory accesses transparent to the user. in general, the cpu core accesses cache-resident instructions or data through the following procedure: 1. the cpu core, through the on-chip cache controller, attempts to access the next instruction or data in the appropriate cache. 2. the cache controller checks to see if this instruction or data is present in the cache. ? if the instruction/data is present, the cpu core retrieves it. this is called a cache hit. ? if the instruction/data is not present in the cache, the cache controller must retrieve it from memory. this is called a cache miss. 3. the cpu core retrieves the instruction/data from the cache and operation continues. it is possible for the same data to be in two places (main memory and cache) simultaneously. this data is kept consistent through the use of a write-back methodology; that is, modified data is not written back to memory until the cache line is to be replaced. instruction and data cache line replacement operations are described in the following sections. 8.3.1 cache write policy the v r 4100 cpu core manages its data cache by using a write-back policy; that is, it stores write data into the cache, instead of writing it directly to memory note . some time later this data is independently written into memory. in the v r 4102 implementation, a modified cache line is not written back to the main memory until the cache line is to be replaced either in the course of satisfying a cache miss, or during the execution of a write-back cache instruction. when the cpu core writes a cache line back to the main memory, it does not ordinarily retain a copy of the cache line, and the state of the cache line is changed to invalid. note write-through cache policy performs the function contrary to the write-back policy. data written into memory is also written into cache simultaneously. chapter 8 cache memory 218 8.4 cache states (1) cache line the three terms below are used to describe the state of a cache line: ? dirty: a cache line containing data that has changed since it was loaded from memory. ? clean: a cache line that contains data that has not changed since it was loaded from memory. ? invalid: a cache line that does not contain valid information must be marked invalid, and cannot be used. for example, after a soft reset, software sets all cache lines to invalid. a cache line in any other state than invalid is assumed to contain valid information. neither cold reset nor soft reset sets caches invalid. software can invalidate caches. (2) data cache the data cache supports three cache states: ? invalid ? valid clean ? valid dirty (3) instruction cache the instruction cache supports two cache states: ? invalid ? valid the state of a valid cache line may be modified when the processor executes a cache operation. cache operations are described in chapter 27. chapter 8 cache memory 219 8.5 cache state transition diagrams the following section describes the cache state diagrams for the data and instruction caches. these state diagrams do not cover the initial state of the system, since the initial state is system-dependent. 8.5.1 data cache state transition the following diagram illustrates the data cache state transition sequence. a load or store operation may include one or more of the atomic read and/or write operations shown in the state diagram below, which may cause cache state transitions. ? read (1) indicates a read operation from memory to cache, inducing a cache state transition. ? write (1) indicates a write operation from cpu core to cache, inducing a cache state transition. ? read (2) indicates a read operation from cache to the cpu core, which induces no cache state transition. ? write (2) indicates a write operation from cpu core to cache, which induces no cache state transition. figure 8-6. data cache state diagram cache op cache op write (1) write (1) cache op write-back read (2) read (2) write (2) read (1) invalid valid dirty valid clean 8.5.2 instruction cache state transition the following diagram illustrates the instruction cache state transition sequence. ? read (1) indicates a read operation from memory to cache, inducing a cache state transition. ? read (2) indicates a read operation from cache to the cpu core, which induces no cache state transition. figure 8-7. instruction cache state diagram read (1) cache op read (2) valid invalid chapter 8 cache memory 220 8.6 cache data integrity the d- and i-cache data ram arrays are protected by parity (byte parity for d-cache, word parity for i-cache). d- and i-cache tag ram arrays are also protected by parity. these parity bits are checked for errors on every cache read access. cache error exception occurs if the cpu core encounters a parity error during an instruction cache access, a data cache access, or memory read access. the cacheerr register indicates the source of the error. figure 8-8 to figure 8-22 shows the parity generation and checking operations for various cache accesses. figure 8-8. data flow on instruction fetch ok, de = 1 or erl = 1 start error tagparity cache error exception tagcheck refill desigerd data parity miss or invalid (see figure 8-21) ok, de = 1 or erl = 1 tagcheck data fetch end cache error exception hit error chapter 8 cache memory 221 figure 8-9. data integrity on load operations ok, de = 1 or erl = 1 start error tagparity tagcheck writeback & refill desigerd data parity miss or invalid (see figure 8-22) ok, de = 1 or erl = 1 tagcheck data load to re g ister end cache error exception hit error valid bit & wbit wbit parity error cache error exception error cache error exception refill (see figure 8-21) ok, de = 1 or erl = 1 v = 1 (valid) and w = 1 (dirty) v = 0 (invalid) or w = 0 (clean) chapter 8 cache memory 222 figure 8-10. data integrity on store operations ok, de = 1 or erl = 1 start error tagparity tagcheck writeback & refill cebit of sr miss (see figure 8-22) = 0 tagcheck data write to d-cache end hit = 1 valid bit & wbit wbit parity error cache error exception error cache error exception refill (see figure 8-21) ok, de = 1 or erl = 1 v = 1 (valid) and w = 1 (dirty) v = 0 (invalid) or w = 0 (clean) data parity generate data parity from perr re g . chapter 8 cache memory 223 figure 8-11. data integrity on index_invalidate operations ok, de = 1 or erl = 1 start error tagparity cache error exception valid bit clear end figure 8-12. data integrity on index_writeback_invalidate operations ok, de = 1 or erl = 1 start error tag parity, wbit parity cache error exception valid bit writeback data parity (see figure 8-20) wbit valid bit and wbit clear end cache error exception = 0 error = 1 (valid) = 1 (dirty) ok, de = 1 or erl = 1 = 0 (clean) chapter 8 cache memory 224 figure 8-13. data integrity on index_load_tag operations start d-cache only end tag and tag parity read to taglo wbit and wbit parity read to taglo figure 8-14. data integrity on index_store_tag operations d-cache only start = 1 cebit of sr tag parity generate end wbit parity generate tag write from taglo tag parity from taglo wbit parity from taglo = 0 chapter 8 cache memory 225 figure 8-15. data integrity on create_dirty operations ok, de = 1 or erl = 1 start error tag parity, wbit parity cache error exception tagcheck writeback data parity (see figure 8-20) valid bit & wbit valid bit and wbit set. tag write. wbit parity and tag parity generate. end cache error exception miss or invalid error hit = 1 (dirty) ok, de = 1 or erl = 1 = 0 (clean) figure 8-16. data integrity on hit_invalidate operations hit start error tagparity cache error exception valid bit clear. tag parity generate. end tagcheck ok, de = 1 or erl = 1 miss or invalid chapter 8 cache memory 226 figure 8-17. data integrity on hit_writeback_invalidate operations ok, de = 1 or erl = 1 start error tag parity, wbit parity cache error exception tagcheck writeback data (see figure 8-20) wbit valid bit clear. tag parity generate. end cache error exception miss or invalid error hit = 1 (dirty) ok, de = 1 or erl = 1 = 0 (clean) data cache error exception error ok, de = 1 or erl = 1 figure 8-18. data integrity on fill operations start refill (see figure 8-21) end chapter 8 cache memory 227 figure 8-19. data integrity on hit_writeback operations ok, de = 1 or erl = 1 ok, de = 1 or erl = 1 start error tag parity, wbit parity cache error exception tagcheck writeback data parity (see figure 8-20) wbit wbit clear end cache error exception miss or invalid error hit = 1 (dirty) = 0 (clean) wbit parity check is d-cache only d-cache only d-cache only chapter 8 cache memory 228 figure 8-20. data integrity on writeback flow ok, de = 1 or erl = 1 error writeback data parity eod? yes erroneous b it = 0 ok, de = 1 or erl = 1 error existed in writeback data writeback data parity cache error exception erroneous b it = 1 writeback to memory no figure 8-21. data integrity on refill flow ok erroneous bit eod? yes write data to cache no bus error exception cache line invalidate error existed in refill data chapter 8 cache memory 229 figure 8-22. data integrity on writeback & refill flow ok erroneous bit eod? writeback data parity ok, de = 1 or erl = 1 ok, de = 1 or erl = 1 error writeback data parity eod? yes writeback to memory no bus error exception cache line invalidate error existed in refill data erroneous bit = 0 erroneous bit = 1 refill start writeback data parity write data to cache yes error existed in writeback data ok, de = 1 or erl = 1 cache error exception error existed in writeback data no remark write-back procedure: on a store miss write-back, data tag and tag parity are checked and data parity is transferred to the write buffer. byte parity is generated for the physical address and transferred to write buffer. if an error is detected on the data field, the write back is not terminated; the erroneous data is still written out. if an error is detected in the tag field, the write-back bus cycle is not issued. in both cases a cache error exception is taken. during a cache operation, cache data may not be checked in some cases, but tag parity is always checked. at that time, if a tag parity error occurs, the cache error exception is taken and the operation is not permitted to complete. chapter 8 cache memory 230 8.7 manipulation of the caches by an external agent the v r 4102 does not provide any mechanisms for an external agent to examine and manipulate the state and contents of the caches. 231 chapter 9 cpu core interrupts four types of interrupt are available on the cpu core. these are: ? one non-maskable interrupt, nmi ? five ordinary interrupts ? two software interrupts ? one timer interrupt these are described in this chapter. 9.1 non-maskable interrupt (nmi) the non-maskable interrupt request signal is acknowledged by asserting the nmi signal (internal), forcing the processor to branch to the reset exception vector. this nmi signal is latched into an internal register at the rising edge of masterout, as shown in figure 9-1. nmi only takes effect when the processor pipeline is running. this interrupt cannot be masked. figure 9-1 shows the internal derivation of the nmi signal. the nmi signal is latched into an internal register at the rising edge of masterout. the latched nmi signal is inverted and then transmitted as an nmi request. figure 9-1. non-maskable interrupt signal nmi re q uest nmi si g nal masterout ( internal re g ister ) 9.2 ordinary interrupts ordinary interrupts are set by asserting the int(4:0) signals (internal). however, int4 never occur on the v r 4102. these interrupts can be masked with the im(6..2), ie, and exl fields of the status register. chapter 9 cpu core interrupts 232 9.3 software interrupts generated in cpu core software interrupts generated in the cpu core are acknowledged by setting bits 1 and 0 of the ip (interrupt pending) field in the cause register. these may be written by software, but there is no hardware mechanism to set or clear these bits. after the processing of a software interrupt exception, corresponding bit of the ip field in the cause register must be cleared before returning to ordinary routine or enabling multiple interrupts. these interrupts are maskable through the im(1:0), ie, and exl fields of the status register. 9.4 timer interrupt the timer interrupt uses bit 15 of the cause register, which is bit 7 of the ip (interrupt pending) field. this bit is automatically set whenever the value of the count register equals the value of the compare register, to acknowledge an interrupt request. this interrupt is maskable by setting im7 of the status register. 9.5 asserting interrupts 9.5.1 detecting hardware interrupts figure 9-2 shows how the hardware interrupt request is detected through the cause register. ? the timer interrupt signal, ip7, is directly readable as bit 15 of the cause register. ? bits 4:0 of the interrupt register are bit-wise ored with the current value of the int(4:0) signals and the result is directly readable as bits 14:10 of the cause register. ip(1:0 ) of the cause register, which are described in chapter 6, are software interrupts. there is no hardware mechanism for setting or clearing the software interrupts. chapter 9 cpu core interrupts 233 figure 9-2. hardware interrupt signals ip2 ip3 ip4 ip5 ip6 ip7 10 11 12 13 14 15 0 1 2 3 4 0 1 2 3 4 cause register (15:10) (internal register) interrupt register (4:0) masterout timer interrupt int4 int3 int2 int1 int0 see figure 9-3 remark int4 never occurs in the v r 4102. chapter 9 cpu core interrupts 234 9.5.2 masking interrupt signals figure 9-3 shows the masking of the cpu core interrupt signals. ? cause register bits 15 to 8 (ip7 to ip0) are and-ored with status register interrupt mask bits 15 to 8 (im7 to im0) to mask individual interrupts. ? status register bit 0 is a global interrupt enable bit (ie). it is anded with the output of the and-or logic to produce the cpu core interrupt signal. the exl bit in the status register also enables these interrupts. figure 9-3. masking of the cpu core interrupts ie im0 im1 im2 im3 im4 im5 im6 im7 ip0 ip1 ip2 ip3 ip4 ip5 ip6 ip7 status register sr (0) status register sr (15:8) cause register (15:8) software interrupts generated in cpu core ordinary interrupts timer interrupt and-or logic and logic cpu core interrupt 8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15 8 8 1 1 bit function setting ie interrupt enable for all interrupts 1: enable 0: disable im (7:0) interrupt mask 1: enable for individual bits 0: disable for individual bits ip (7:0) interrupt request 1: pending request for individual bits 0: no pending for individual bits 235 chapter 10 bcu (bus control unit) this chapter describes the bcus operations and register settings. 10.1 general in the v r 4102, the bcu receives data that has passed via the v r 4100 cpu core and the sysad bus. the bcu also controls external agents via the system bus, such as an lcd controller, dram, rom (flash memory or masked rom), or pcmcia controller, and it transmits and receives data with these external agents via the add bus and data bus. 10.2 register set the bcu registers are listed below. table 10-1. bcu registers address r/w register symbols function 0x0b00 0000 r/w bcucntreg 1 bcu control register 1 0x0b00 0002 r/w bcucntreg 2 bcu control register 2 0x0b00 000a r/w bcuspeedreg bcu access cycle change register 0x0b00 000c r/w bcuerrstreg bcu bus error status register 0x0b00 000e r/w bcurfcntreg bcu refresh control register 0x0b00 0010 r revidreg revision id register 0x0b00 0012 r/w bcurfcountreg bcu refresh count register 0x0b00 0014 r/w clkspeedreg clock speed register each register is described in detail as follows. chapter 10 bcu (bus control unit) 236 10.2.1 bcucntreg 1 (0x0b00 0000) (1/2) bit d15 d14 d13 d12 d11 d10 d9 d8 name rom64 dram64 isam/lcd page128 reserved pagerom2 reserved pagerom0 r/w r/w r/w r/w r/w r r/w r r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved romwen2 reserved romwen0 reserved reserved busherren rstout r/w r r/w r r/w r r r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15] rom64 sets the capacity of the rom to be used 1: 64m-bit rom 0: 32m-bit rom d[14] dram64 sets the capacity of the dram to be used 1 : 64m-bit dram 0 : 16m-bit dram d[13] isam/lcd assigns space from 0x0a00 0000 to 0x0aff ffff as the physical address space. 1 : as isa high-speed memory space 0 : as lcd space d[12] page128 sets the maximum burst acceleration size for page rom. 1 : 128-bit (16 byte) 0 : 64-bit (8 byte) d[11] reserved write 0 when writing. 0 is returned after a read. d[10] pagerom2 this is the page rom access enable bit for the rom space in banks 3 and 2 (16-bit mode) or in bank 1 (32-bit mode). 1 : page rom 0 : ordinary rom d[9] reserved write 0 when writing. 0 is returned after a read. d[8] pagerom0 this is the page rom access enable bit for the rom space in banks 1 and 0 (16-bit mode) or in bank 0 (32-bit mode). 1 : page rom 0 : ordinary rom chapter 10 bcu (bus control unit) 237 (2/2) bit name function d[7] reserved write 0 when writing. 0 is returned after a read. d[6] romwen2 this enables flash memory write and issues a flash memory register read-only bus cycle for the rom space in banks 3 and 2 (16-bit mode) or in bank 1 (32-bit mode). 1 : enable (not affected by pagerom2) 0 : prohibit d[5] reserved write 0 when writing. 0 is returned after a read. d[4] romwen0 this enables flash memory write and issues a flash memory register read-only bus cycle for the rom space in banks 1 and 0 (16-bit mode) or in bank 0 (32-bit mode). 1 : enable (not affected by pagerom0) 0 : prohibit d[3..2] reserved write 0 when writing. 0 is returned after a read. d[1] busherren this is the bus timeout detection enable bit, which is used when a bus hold has been received. 1 : performs timeout detection when a bus hold has been received. 0 : does not perform timeout detection when a bus hold has been received. d[0] rstout rstout control bit 1 : high level 0 : low level this register is used to set parameters such as the bus interfaces bus cycle. for the setting of the pagerom2 and romwen2 bits, the target rom area differs depending on a data bus mode. the access target rom area is banks 3 and 2 in 16-bit data bus mode, and bank 1 in 32-bit data bus mode. for the setting of the pagerom0 and romwen0 bits, the target rom area differs depending on the data bus mode. the access target rom area is banks 1 and 0 in 16-bit data bus mode, and bank 0 in 32-bit data bus mode. when a timeout is detected while the busherren bit is set to 1, the berrst bit of the bcuerrstreg register is set to 1 and an interrupt request is sent to the cpu. the rstout pin is set to high to request bus release from the external bus master. chapter 10 bcu (bus control unit) 238 10.2.2 bcucntreg 2 (0x0b00 0002) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved gmode r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] gmode this is the access data control bit for lcd space. 1 : do not invert the access data for lcd space 0 : invert the access data for lcd space this register is used to specify whether data is inverted (translated to 2s complement) or not when accessing the lcd space. the lcd space is accessed when the isam/lcd bit of bcucntreg1 is 0. when it is 1, this address space is used as the isa high-speed memory space. in this case, the contents of the bcucntreg2 register are invalid, and inversion of access data is not performed. chapter 10 bcu (bus control unit) 239 10.2.3 bcuspeedreg (0x0b00 000a) (1/2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved wprom[1] wprom[0] reserved wlcd/m[2] wlcd/m[1] wlcd/m[0] r/w r r r/w r/w r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved wisaa [2] wisaa [1] wisaa [0] reserved wroma[2] wroma[1] wroma[0] r/w r r/w r/w r/w r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..14] reserved write 0 when writing. 0 is returned after a read. d[13..12] wprom[1..0] page rom access speed 11 : rfu 10 : 1tclock 01 : 2tclock 00 : 3tclock d[11] reserved write 0 when writing. 0 is returned after a read. d[10..8] wlcd/m[2..0] access speed to physical address space from 0x0a00 0000 to 0x0aff ffff lcd(isam/lcd=0) isa-mem(isam/lcd=1) 111 : rfu 1tclock 110 : rfu 2tclock 101 : rfu 3tclock 100 : rfu 4tclock 011 : 2tclock 5tclock 010 : 4tclock 6tclock 001 : 6tclock 7tclock 000 : 8tclock 8tclock d[7] reserved write 0 when writing. 0 is returned after a read. chapter 10 bcu (bus control unit) 240 (2/2) bit name function d[6..4] wisaa[2..0] system bus access speed 111 : rfu. operation is not guaranteed when this value has been set. 110 : rfu. operation is not guaranteed when this value has been set. 101 : 3tclock note 100 : 4tclock note 011 : 5tclock 010 : 6tclock 001 : 7tclock 000 : 8tclock d[3] reserved write 0 when writing. 0 is returned after a read. d[2..0] wroma[2..0] rom access speed 111 : 2tclock 110 : 3tclock 101 : 4tclock 100 : 5tclock 011 : 6tclock 010 : 7tclock 001 : 8tclock 000 : 9tclock note when the wisaa [2:0] bits are set to 101 or 100, the ac characteristics between busclk and the system bus interface signals (add [25:0], shb#, memr#, memw#, ior#, and iow#) are not guaranteed. this register is used to set the access speed for the lcd, system bus, page rom, and rom. the lowest speed is set when 0 is set to all of the following bits: wlcd/m[2..0], wprom[1..0], wisaa[2..0], and wroma[2..0]. setting 1 to all of these bits sets the highest speed. the value set to wprom[1..0] is valid only when 1 has been set to the pagerom bit in bcucntreg. chapter 10 bcu (bus control unit) 241 10.2.4 bcuerrstreg (0x0b00 000c) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved berrst r/w rrrrrrrr/w1c rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] berrst bus error status. clear to 0 when 1 is written. 1 : bus error 0 : normal this register is used to indicate when a bus error interrupt request has occurred. chapter 10 bcu (bus control unit) 242 10.2.5 bcurfcntreg (0x0b00 000e) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved brf[13] brf[12] brf[11] brf[10] brf[9] brf[8] r/w r r r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 1 0 other resets 0 0 undefined undefined undefined undefined undefined undefined bitd7d6d5d4d3d2d1d0 name brf[7] brf[6] brf[5] brf[4] brf[3] brf[2] brf[1] brf[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function d[15..14] reserved write 0 when writing. 0 is returned after a read. d[13..0] brf[13..0] use this bit to set the number of refresh cycles (with tclock cycle). this register is used to specify the number of refresh cycles (with tclock cycle). chapter 10 bcu (bus control unit) 243 10.2.6 revidreg (0x0b00 0010) bit d15 d14 d13 d12 d11 d10 d9 d8 name rid[3] rid[2] rid[1] rid[0] mjrev[3] mjrev[2] mjrev[1] mjrev[0] r/w rrrrrrrr rtcrst 0 0 0 1 undefined undefined undefined undefined other resets 0 0 0 1 undefined undefined undefined undefined bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved mnrev[(3] mnrev[2] mnrev[1] mnrev[0] r/w rrrrrrrr rtcrst 0 0 0 0 undefined undefined undefined undefined other resets 0 0 0 0 undefined undefined undefined undefined bit name function d[15..12] rid[3:0] this is the processor revision id. 0x01 indicates the v r 4102. d[11..8] mjrev[3..0] major revision number d[7..4] reserved write 0 when writing. 0 is returned after a read. d[3..0] mnrev[3..0] minor revision number this register is used to indicate revisions of the v r 4102s peripheral units. the revision number is stored as a value in the form y.x , where y is a major revision number and x is a minor revision number. major revision number and minor revision number can distinguish the revision of the cpu and the peripheral units, however there is no guarantee that changes to the cpu and the peripheral units will necessarily be reflected in this register, or that changes to the revision number necessarily reflect real cpus and units changes. for this reason, these values are not listed and software should not rely on the revision number in previdreg to characterize the units. chapter 10 bcu (bus control unit) 244 10.2.7 bcurfcountreg (0x0b00 0012) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved brfc[13] brfc[12] brfc[11] brfc[10] brfc[9] brfc[8] r/w r r r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name brfc[7] brfc[6] brfc[5] brfc[4] brfc[3] brfc[2] brfc[1] brfc[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..14] reserved write 0 when writing. 0 is returned after a read. d[13..0] brfc[13..0] this is the down counter that counts the number of refresh cycles (with tclock cycle). this register is used to indicate the current refresh cycle count value. chapter 10 bcu (bus control unit) 245 10.2.8 clkspeedreg (0x0b00 0014) bit d15 d14 d13 d12 d11 d10 d9 d8 name div2b reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved clksp[4] clksp[3] clksp[2] clksp[1] clksp[0] r/w rrrrrrrr rtcrst 0 0 0 undefined undefined undefined undefined undefined other resets 0 0 0 undefined undefined undefined undefined undefined bit name function d[15] div2b the multiplier of tclock frequency. this bit always indicates 0 in the current v r 4102. 1: reserved 0: multiplied by 16 d[14..5] reserved write 0 when writing. 0 is returned after a read. d[4..0] clksp[4..0] these bits indicate the value used to calculate the frequency of pclock and tclock. this register is used to indicate the value to calculate the frequencies of the peripheral units operating clock (tclock) and cpu cores operating clock (pclock). the pclock frequency obtained from this registers setting is the same as the frequency selected by setting clksel[2:0] pins. the following method is used to calculate tclock frequency. tclock = (18.432 mhz/clksp[4..0])*16 the following method is used to calculate pclock frequency. pclock = (18.432 mhz/clksp[4..0])*32 chapter 10 bcu (bus control unit) 246 10.3 connection of address pins physical address output from the cpu core is provided to external devices through add bus. the correspondence between the address output to add bus and the address bits of external devices differs depending on the external devices as shown in table 10-2. therefore, connect add bus and address pin of the external device as shown in table 10-3. table 10-2. address bit correspondence between add bus and external devices add bus devices connected 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 rom, lcd, isa, dram (row) 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 dram (column), data [15:0] 01234567812345678192019202122232425 dram (column), data [31:0] 012345678212345678192019202122232425 table 10-3. address connection table with external devices address bits of external devices v r 4102 pin 16m-bit dram 64m-bit dram, data[15..0] 64m-bit dram, data[31..0] add[9] a0 a0 a0 add[10] a1 a1 a1 add[11] a2 a2 a2 add[12] a3 a3 a3 add[13] a4 a4 a4 add[14] a5 a5 a5 add[15] a6 a6 a6 add[16] a7 a7 a7 add[17] a8 a8 a8 add[18] a9 a9 a9 add[19] a10/nc note 1 -- add[20] a11/nc note 1 a12/nc note 2 a12/nc note 3 add[21] - a10 - add[22] - a11 a10 add[23] - - a11 notes 1. a10, a11 : p pd42s16165, nc : p pd42s18165 2. a12 : p pd42s64165, nc : p pd42s65165 3. a12 : p pd42s64165, nc : p pd42s65165 chapter 10 bcu (bus control unit) 247 10.4 notes on using bcu 10.4.1 cpu core bus modes the v r 4102 is designed on the assumption that the cpu core is set to the following mode. ? writeback data rate : d ? accelerate data ratio : v r 4x00 compatible mode therefore, set the config register as below: ? ep : 0000 ?ad : 0 10.4.2 access data size in the v r 4102, access size is restricted for each address space. access sizes for the following address spaces are listed below. table 10-4. access size restrictions for address spaces address space r/w access size (bytes) remark 1684321 rom/pagerom r {{{{{{ flash memory w uu u u note 1 system bus i/o space r/w {{{ u {{ system bus memory space r/w {{{ u {{ on-chip i/o space 1 r/w {{{ u {{ on-chip i/o space 2 r/w u {{ u { u lcd space r/w u {{ u {{ notes 2, 3 high-speed system bus memory space r/w u {{ u {{ note 3 dram r/w {{{{{{ notes 1. the access size when writing to flash memory must be the same as the data bus width such as below; in 32-bit mode: 4 bytes in 16-bit mode: 2 bytes 2. use as uncached. 3. the lcd space and high-speed system bus memory space are mapped to the same physical address. use bcucntreg1s isam/lcd bit to switch between the two. remark { , : accessible, u : not accessible chapter 10 bcu (bus control unit) 248 10.4.3 rom interface (1) switching among rom, pagerom, and flash memory modes the v r 4102 supports three modes (rom, pagerom and flash memory). the mode setting in rom bank 3/2 is set via bcucntreg1s romwen2 and pagerom2 bits, and the mode setting in rom bank 1/0 is set via the romwen0 and pagerom0 bits. in ordinary rom mode or flash memory mode, the v r 4102 can access to memories regardless of its mode name. table 10-5 shows accessible memory types and methods of access in each mode. table 10-5. summary of rom modes mode setting access-enabled devices romwen2/0 pagerom2/0 memory read flash memory register read flash memory write ordinary rom 0 0 ordinary rom pagerom flash memory n/a n/a pagerom 0 1 pagerom n/a n/a flash memory 1 dont care ordinary rom pagerom flash memory flash memory flash memory remark the initial setting is ordinary rom mode. (2) access speed setting the v r 4102 enables the access speed to be changed when operating in ordinary rom mode or pagerom mode. for details, see 10.5.1. chapter 10 bcu (bus control unit) 249 10.4.4 flash memory interface (1) notes for specific modes the following two modes are available for flash memory. ? ordinary rom mode (memory read only) ? flash memory mode (supports memory write and register read) the following notes apply to these modes. (a) notes for ordinary rom mode ? write is prohibited the wr# pin is not asserted even when a write operation is attempted. ? flash memory register read is prohibited the ordinary rom mode is the mode in which bus cycles suite for memory read operations are issued. since the ac characteristics of flash memory are different for register read and memory read operations, accurate data cannot be obtained by reading the flash memory register while in this mode. (b) notes for flash memory mode ? be sure to access in double-byte units when writing to flash memory. (2) example of write sequence for flash memory an example of a write sequence for flash memory is shown below. caution this examples operations have not been confirmed using an actual system. 1 using gpio as an output port, apply the flash memory write voltage (v pp ). if the v r 4102s on-chip gpios cannot be used, set up an external output port and then control the write voltage. 2 set the v r 4102 to flash memory mode (set 1 to the bcucntregs romwen bit). 3 wait until the flash memory write voltage become stable. 4 issue the flash memory write command from the v r 4102. 5 write data from the v r 4102 to flash memory. 6 wait until the flash memory write completion signal (ry/by) becomes stable. 7 wait until the flash memory write completion signal gives notification of write completion. after write to flash memory is completed, notification can be obtained by receiving an interrupt from the flash memory write completion signal (ry/by) or by polling the flash memory register. 8 read the flash memory register. ? if write succeeded, start processing from 9. ? if write failed, start processing from 12. 9 if writing new data to flash memory, start processing from 4. if write to flash memory is completed, start processing from 10. chapter 10 bcu (bus control unit) 250 10 compare the data written to flash memory with the original data. ? if the data matches, perform processing at 11. ? if the data does not match start processing from 1 when rewriting. if processing is interrupted, start processing from 11. 11 reduce the flash memory write voltage (v pp ) and end processing after flash memory mode has been canceled. 12 clear any error data in the flash memory register. ? if writing again if the write voltage is too low, start processing from 1. in all other cases, start processing from 4. ? if processing is completed, perform processing at 11. 10.4.5 lcd control interface (1) access size available access sizes for accessing the lcd controller interface are 1 byte, 2 bytes, 4 bytes, and 8 bytes. (2) data inversion when 0 has been set to the bcucntreg1s isam/lcd bit and to bcucntreg2s gmode bit, the v r 4102 inverts the bits in the data being read or written via the lcd controller interface. table 10-6. example of bit inversion in data in v r 4102 and at data [15:0] pins data in v r 4102 data at data [15:0] pins 0x0000 0xffff 0xa5a5 0x5a5a 0x1234 0xedcb chapter 10 bcu (bus control unit) 251 10.4.6 illegal access notification (1) types of illegal access under the following circumstances, the v r 4102 provides notification concerning illegal access of the cpu core. ? bus deadlock if cbr refresh does not occur at least twice, a deadlock is judged as having occurred due to the non-return of a ready signal via the system bus or lcd controller interface, in which case notification of illegal access is given. ? address space reserved for future use notification of illegal access is given when the processor has accessed any of the following addresses. 0x0fff ffff to 0x0c00 0000 0x09ff ffff to 0x0400 0000 (2) notification method for illegal access the methods used to notify the cpu core are listed below. table 10-7. illegal access notification methods access type illegal access notification method processor read request notification by bus error caused by syscmd processor write request notification by interrupt exception (int0) remark to clear the interrupt source caused by a processor write request, write 1 to bcuerrstregs bit1. chapter 10 bcu (bus control unit) 252 10.5 bus operations the bus operations of buses controlled by the bcu are described below. the bcus operating clock (tclock) appears in the timing chart for each bus operation. remark # that follows signal names indicates active low. 10.5.1 rom access the v r 4102 supports the following three modes for rom access. use bcucntreg1s pagerom2/0 bits and romwen2/0 bits to set the mode. x ordinary rom read mode (romwen, pagerom = 00) x pagerom read mode (romwen, pagerom = 01) x flash memory mode (romwen = 1) (1) ordinary rom read mode set romwen = 0 and pagerom = 0. wroma[2:0] (bcuspeedreg [2:0]) can be used to set the access time. figures 10-1 and 10-2 show 4-byte read timing chart data for when wroma [2:0] is set to 110. if access uses a data size larger than 4 bytes, the trom cycle is continued until the required access size is reached. table 10-8. access times during ordinary rom read mode wroma [2:0] trom (tclock) 000 9 001 8 010 7 011 6 100 5 101 4 110 3 111 2 chapter 10 bcu (bus control unit) 253 figure 10-1. rom 4-byte read, 16-bit mode (wroma[2:0] = 110) trom trom rd# romcs[3:0]# add[25:0] tclock(internal) data[15:0] remark the dotted lines indicate high impedance. figure 10-2. rom 4-byte read, 32-bit mode (wroma[2:0] = 110) trom rd# romcs[3:0]# add[25:0] tclock(internal) data[31:0] remark the dotted lines indicate high impedance. data is sampled at the rising edge of the tclock following the last trom-state tclock. the bus operation types for ordinary rom are as follows. 1-byte read, 2-byte read, 3-byte read, 1-word read, 2-word read, and 4-word read (1 word = 4 bytes) chapter 10 bcu (bus control unit) 254 (2) pagerom read mode set romwen = 0 and pagerom = 1. wroma[2:0] (bcuspeedreg [2:0]) and wprom[1:0] (bcuspeedreg [13:12]) can be used to set the access time. figures 10-3 and 10-4 show 16-byte read timing charts for when wroma [2:0] is set to 111 and wprom [1:0] is set to 10. the romcs[3:0]# and rd# pins are held at low level during trom cycles. table 10-9. pagerom read mode access time wroma [2:0] trom (tclock) wprom [1:0] tprom (tclock) 000 9 00 3 001 8 01 2 010 7 10 1 011 6 11 rfu 100 5 101 4 110 3 111 2 figure 10-3. pagerom 4-word read, 16-bit mode (wroma[2:0] = 111, wprom[1:0] = 10) trom rd# romcs[3:0]# add[25:0] tclock(internal) data[15:0] t prom t prom t prom t prom t prom t prom t prom remark the dotted lines indicate high impedance. chapter 10 bcu (bus control unit) 255 figure 10-4. pagerom 4-word read, 32-bit mode (wroma[2:0] = 111, wprom[1:0] = 10) rd# romcs[3:0]# add[25:0] tclock(internal) data[31:0] trom t prom t prom t prom remark the dotted lines indicate high impedance. (3) flash memory mode set romwen = 1. this mode is used to meet the electrical characteristics required for writing to flash memory and for accessing the flash register. this mode can also be used to read to flash memory. note that the access time is constant when in this mode. figure 10-5. flash memory mode, 2-byte access rd#/wr# romcs[3:0] # add[25:0] tclock(internal) flash memory mode access cycle chapter 10 bcu (bus control unit) 256 10.5.2 system bus access (1) bus operations in system bus wisaa[2:0] (bcuspeedreg [6:4]) can be used to set the access time. table 10-10. system bus access times wisaa [2:0] tisa (tclock) 000 8 001 7 010 6 011 5 100 4 101 3 110 rfu 111 rfu figure 10-6. 1-byte access to even address using 16-bit bus (wisaa[2:0] = 101) shb# tisa add[25:0] tclock(internal) zws# ior#/iow# memr#/memw# iochrdy tisa tisa data[15:0](write) data[15:0](read) iocs16# memcs16# h remark the dotted lines indicate high impedance. chapter 10 bcu (bus control unit) 257 figure 10-7 illustrates 2-byte access when sampling iochrdy at high level. if the system bus access time has been set as three tclocks (wisaa[2:0] = 101), the bus cycle will end after waiting for at least 3 tclocks (tisa periods) after the ready signal is sampled using iochrdy. sampling of the iochrdy signal occurs at the rising edge of the tclock that follows the second or subsequent tisa period. figure 10-7. 2-byte access when sampling iochrdy at high level using 16-bit bus (wisaa[2:0] = 101) tisa tisa tisa tclock(internal) add[25:0] shb# iocs16# memcs16# ior#/iow# memr#/memw# iochrdy zws# data[15:0] (write) data[15:0] (read) l remark the dotted lines indicate high impedance. chapter 10 bcu (bus control unit) 258 figures 10-8 and 10-9 show timing charts for 1-byte access. figure 10-8. 1-byte access to odd address using 16-bit bus (wisaa[2:0] = 101) tisa tisa tisa tclock(internal) add[25:0] shb# iocs16# memcs16# ior#/iow# memr#/memw# iochrdy zws# data[15:0] (write) data[15:0] (read) l remark the dotted lines indicate high impedance. figure 10-9. 1-byte access to odd address using 8-bit bus (wisaa[2:0] = 101) tisa tisa tisa tclock(internal) add[25:0] shb# iocs16# memcs16# ior#/iow# memr#/memw# iochrdy zws# data[15:0] ( write ) data[15:0] (read) l remark the dotted lines indicate high impedance. chapter 10 bcu (bus control unit) 259 figures 10-10 and 10-11 illustrate 2-byte access when sampling zws# at low level. the bus cycle will end after waiting for at least 1 tclock (tisa period) after the ready signal is sampled using zws#. sampling of the zws# signal occurs at the rising edge of the tclock that follows the second or subsequent tisa period. figure 10-10. 2-byte access when sampling zws# at low level on 16-bit bus (wisaa[2:0] = 101) tisa tisa tclock(internal) add[25:0] shb# iocs16# memcs16# ior#/iow# memr#/memw# iochrdy zws# data[15:0] (write) data[15:0] (read) l remark the dotted lines indicate high impedance. chapter 10 bcu (bus control unit) 260 figure 10-11. 2-byte access when sampling zws# at low level on 8-bit bus (wisaa[2:0] = 101) tisa tisa tisa tisa tclock(internal) add[25:0] iocs16 # memcs16 # ior#/iow# memr#/memw # iochrd y zws # data[15:0] (write) data[15:0] (read) remark the dotted lines indicate high impedance. (2) bus operations in high-speed system bus the space of physical address from 0x0a00 0000 to 0x0aff ffff can be used as the high-speed system bus memory space by setting the isam/lcd bit of bcucntreg1. wlcd/m [2:0] (bcuspeedreg [10:8]) can be used to set the access time for access to this space, as shown in the table below. table 10-11. high-speed system bus access times wlcd/w [2:0] tisa (tclock) 000 8 001 7 010 6 011 5 100 4 101 3 110 2 111 1 chapter 10 bcu (bus control unit) 261 figure 10-12. 2-byte access on 16-bit bus (wlcd/m[2:0] = 101) tclock (internal) add (25:0) shb# lcdcs# memcs16# memr#/memw# iochrdy zws# data (15:0) (write) data (15:0) (read) l hi-z tisa tisa tisa figure 10-13. 1-byte access on 8-bit bus (wlcd/m[2:0] = 101) tclock (internal) add (25:0) shb# lcdcs# memcs16# memr#/memw# iochrdy zws# data (15:0) (write) data (15:0) (read) h hi-z tisa tisa tisa chapter 10 bcu (bus control unit) 262 figure 10-14. 2-byte access when sampling zws# at low level on 16-bit bus (wlcd/m[2:0] = 101) tisa tisa tclock (internal) add (25:0) shb# l lcdcs# memcs16# memr#/memw# iochrdy zws# data (15:0) (write) data (15:0) (read) hi-z figure 10-15. 1-byte access when sampling zws# at low level on 8-bit bus (wlcd/m[2:0] = 101) tisa tisa tclock (internal) add (25:0) shb# h lcdcs# memcs16# memr#/memw# iochrdy zws# data (15:0) (write) data (15:0) (read) hi-z chapter 10 bcu (bus control unit) 263 10.5.3 lcd interface the space of the physical address, from 0x0a00 0000 to 0x0aff ffff can be used as the lcd space by setting the ism/lcd bit of the bcucntreg1. wlcd/m[2:0] (bcuspeedreg [10:8]) can be used to set the access time. table 10-12. access times for lcd interface wlcd/m [2:0] tlcd (tclock) 000 8 001 6 010 4 011 2 100 - 111 rfu figure 10-16. 2-byte access to lcd controller (wlcd/m[2:0] = 010) tlcd rd#/wr# lcdrd y lcdcs # add[25:0] tclock(internal) figure 10-17. 2-byte access to lcd controller (wlcd/m[2:0] = 011) tlcd wait cycle insertion via lcdrdy signal tclock(internal) add[25:0] shb# lcdcs# rd#/wr# lcdrdy data[15:0] (write) data[15:0] (read) l remark the dotted lines indicate high impedance. chapter 10 bcu (bus control unit) 264 10.5.4 dram access (edo type) the access time is constant for dram. figure 10-18. 4-byte access to dram (16-bit mode) tclock(internal) mras[3:0]# ucas#/lcas# add[18:9] rd#/wr# data[15:0] ( read ) row col. col. data0 data[15:0] ( write ) data0 data1 data1 add[25:19]/ add[8:0] row remark the dotted lines indicate high impedance. figure 10-19. 8-byte access to dram (32-bit mode) tclock(internal) mras[1:0]# uucas # /ulcas # / ucas # /lcas # add[18:9] rd#/wr# data[31:0] ( read ) row col. col. data0 data[31:0] ( write ) data0 data1 data1 add[25:19]/ add[8:0] row remark the dotted lines indicate high impedance. chapter 10 bcu (bus control unit) 265 figure 10-20. byte read of odd address in dram (16-bit mode) tclock(internal) mras[3:0]# ucas# lcas# add[20:19] add[18:9] rd# data[15:0] h row row col. col. data remark the dotted lines indicate high impedance. figure 10-21. byte read of even address in dram (16-bit mode) tclock(internal) mras[3:0]# ucas# lcas# add[20:19] add[18:9] rd# data[15:0] h row row col. col. data remark the dotted lines indicate high impedance. chapter 10 bcu (bus control unit) 266 figure 10-22. byte write to odd address in dram (16-bit mode) tclock(internal) mras[3:0]# ucas# lcas# add[20:19] add[18:9] wr# data[15:0] h row row col. col. data figure 10-23. byte write to even address in dram (16-bit mode) tclock(internal) mras[3:0]# ucas# lcas# add[20:19] add[18:9] wr# data[15:0] h row row col. col. data chapter 10 bcu (bus control unit) 267 10.5.5 refresh the v r 4102 supports cbr refresh and self refresh. (1) cbr refresh figure 10-24. cbr refresh (16-bit mode) ucas#/lcas# mras# tclock(internal) wr# (2) self refresh figure 10-25. self refresh (16-bit mode) ucas#/lcas# mras# tclock(internal) wr# chapter 10 bcu (bus control unit) 268 10.5.6 bus hold caution the busclk signal is fixed at low level during execution of the suspend instruction. consequently, while the suspend instruction is being executed, the bus is being used by an external master device and cannot be used for busclk. figure 10-26. bus hold in fullspeed mode (a) transition to bus hold from ordinary operation tclock(internal) masterout(internal) hldrq# hldack# note 1 note 2 busclk (b)transition to ordinary operation from bus hold tclock(internal) masterout(internal) hldrq# hldack# note 1 note 2 busclk notes 1. uucas#/mras[3]#, ulcas#/mras[2]#, mras[1..0]#, ucas#, lcas# 2. shb#, ior#, iow#, memr#, memw#, rd#, wr#, add[25..0], data[15..0], data[31..16]/gpio[31..16] (in 32-bit data bus mode) remark the dotted lines indicate high impedance. chapter 10 bcu (bus control unit) 269 figure 10-27. bus hold in suspend mode (a) transition to bus hold from ordinary operation l masterout(internal) hldrq# hldack# note 1 note 2 note 3 busclk (b) transition to ordinary operation from bus hold l masterout(internal) hldrq# hldack# note 1 note 2 note 3 busclk notes 1. uucas#/mras[3]#, ulcas#/mras[2]#, mras[1..0]# (in 16-bit data bus mode) mras[1..0]# (in 32-bit data bus mode) 2. ucas#, lcas# (in 16-bit data bus mode) uucas#/mras#[3], ulcas#/mras[2]#, ucas#, lcas# (in 32-bit data bus mode) 3. shb#, ior#, iow#, memr#, memw#, rd#, wr#, add[25..0], data[15..0], data[31..16]/gpio[31..16] (in 32-bit data bus mode) remark the dotted lines indicate high impedance. 270 [memo] 271 chapter 11 dmaau (dma address unit) this chapter describes the dmaau registers operations and settings. 11.1 general the dmaau register controls the dma addresses for the aiu and irda 4-mbps communication module (fir). the dma channel used for each unit can set a dma start address as any half-word address in the space from 0x0000 0000 to 0x01ff fffe, and is retained in dram as a 2-kbyte block that starts at the address which is generated by masking the low-order 10 bits of the dma start address. after a dma start address is set to the dma base address register, the v r 4102 performs dma transfer using the registers of dmaau as below. (1) when the dma start address is included in the first page of the dma space 1. the v r 4102 starts a dma transfer after writing the start address to the dma address register. 2. when the dma transfer reaches the first page boundary, the v r 4102 adds 1 kbyte to the contents of the dma base address register, writes the value to the dma address register, and continues the dma transfer. 3. when the dma transfer reaches the second page boundary, the v r 4102 writes the contents of the dma base address register to the dma address register and continues the dma transfer. 4. the v r 4102 repeats 2. and 3. until all the data is transferred. (2) when the dma start address is included in the second page of the dma space 1. the v r 4102 starts a dma transfer after writing the start address to the dma address register. 2. when the dma transfer reaches the second page boundary, the v r 4102 subtracts 1 kbyte from the contents of the dma base address register, writes the value to the dma address register, and continues the dma transfer. 3. when the dma transfer reaches the first page boundary, the v r 4102 writes the contents of the dma base address register to the dma address register and continues the dma transfer. 4. the v r 4102 repeats 2. and 3. until all the data is transferred. figure 11-1. dma space used in dma transfers second page first page boundary base address o dma space address second page first page boundary base address o dma space address (a) when the dma start address is included in the first page of the dma space (b) when the dma start address is included in the second page of the dma space 1357 2468 2468 1357 caution dma operations are not guaranteed if an address overlaps with another dma buffer. chapter 11 dmaau (dma addr ess unit) 272 11.2 register set the dmaau registers are listed below. table 11-1. dmaau registers address r/w register symbols function 0x0b00 0020 r/w aiuibalreg aiu in dma base address register low 0x0b00 0022 r/w aiuibahreg aiu in dma base address register high 0x0b00 0024 r/w aiuialreg aiu in dma address register low 0x0b00 0026 r/w aiuiahreg aiu in dma address register high 0x0b00 0028 r/w aiuobalreg aiu out dma base address register low 0x0b00 002a r/w aiuobahreg aiu out dma base address register high 0x0b00 002c r/w aiuoalreg aiu out dma address register low 0x0b00 002e r/w aiuoahreg aiu out dma address register high 0x0b00 0030 r/w firbalreg fir dma base address register low 0x0b00 0032 r/w firbahreg fir dma base address register high 0x0b00 0034 r/w firalreg fir dma address register low 0x0b00 0036 r/w firahreg fir dma address register high these registers are described in detail below. chapter 11 dmaau (dma addr ess unit) 273 11.2.1 aiu in dma base address registers (1) aiuibalreg (0x0b00 0020) bit d15 d14 d13 d12 d11 d10 d9 d8 name aiuiba[15] aiuiba[14] aiuiba[13] aiuiba[12] aiuiba[11] aiuiba[10] aiuiba[9] aiuiba[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 0 0 0 other resets 1 1 1 1 1 0 0 0 bitd7d6d5d4d3d2d1d0 name aiuiba[7] aiuiba[6] aiuiba[5] aiuiba[4] aiuiba[3] aiuiba[2] aiuiba[1] aiuiba[0] r/w r/w r/w r/w r/w r/w r/w r/w r rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:1] aiuiba[15:1] dma base address [15:1] for aiu input d[0] aiuiba[0] dma base address [0] for aiu input write 0 when writing. 0 is returned after a read. (2) aiuibahreg (0x0b00 0022) bit d15 d14 d13 d12 d11 d10 d9 d8 name aiuiba[31] aiuiba[30] aiuiba[29] aiuiba[28] aiuiba[27] aiuiba[26] aiuiba[25] aiuiba[24] r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bitd7d6d5d4d3d2d1d0 name aiuiba[23] aiuiba[22] aiuiba[21] aiuiba[20] aiuiba[19] aiuiba[18] aiuiba[17] aiuiba[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15:9] aiuiba[31:25] dma base address [31:25] for aiu input write 0 when writing. 0 is returned after a read. d[8:0] aiuiba[24:16] dma base address [24:16] for aiu input chapter 11 dmaau (dma addr ess unit) 274 aiuibalreg and aiuibahreg are used to set the base addresses for the dma channel used for audio input (recording). the addresses set to this register become dma start addresses. the dma channel used for audio input is retained in dram as a 2-kbyte buffer that starts at the address which is generated by masking the low-order 10 bits of the dma start address. chapter 11 dmaau (dma addr ess unit) 275 11.2.2 aiu in dma address registers (1) aiuialreg (0x0b00 0024) bit d15 d14 d13 d12 d11 d10 d9 d8 name aiuia[15] aiuia[14] aiuia[13] aiuia[12] aiuia[11] aiuia[10] aiuia[9] aiuia[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 0 0 0 other resets 1 1 1 1 1 0 0 0 bitd7d6d5d4d3d2d1d0 name aiuia[7] aiuia[6] aiuia[5] aiuia[4] aiuia[3] aiuia[2] aiuia[1] aiuia[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:0] aiuia[15:0] next dma address [15:0] to be accessed for aiu input channel (2) aiuiahreg (0x0b00 0026) bit d15 d14 d13 d12 d11 d10 d9 d8 name aiuia[31] aiuia[30] aiuia[29] aiuia[28] aiuia[27] aiuia[26] aiuia[25] aiuia[24] r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bitd7d6d5d4d3d2d1d0 name aiuia[23] aiuia[22] aiuia[21] aiuia[20] aiuia[19] aiuia[18] aiuia[17] aiuia[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15:0] aiuia[31:16] next dma address [31:16] to be accessed for aiu input channel chapter 11 dmaau (dma addr ess unit) 276 11.2.3 aiu out dma base address registers (1) aiuobalreg (0x0b00 0028) bit d15 d14 d13 d12 d11 d10 d9 d8 name aiuoba[15] aiuoba[14] aiuoba[13] aiuoba[12] aiuoba[11] aiuoba[10] aiuoba[9] aiuoba[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 0 0 0 other resets 1 1 1 1 1 0 0 0 bitd7d6d5d4d3d2d1d0 name aiuoba[7] aiuoba[6] aiuoba[5] aiuoba[4] aiuoba[3] aiuoba[2] aiuoba[1] aiuoba[0] r/w r/w r/w r/w r/w r/w r/w r/w r rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:1] aiuoba[15:1] dma base address [15:1] for aiu output d[0] aiuoba[0] dma base address [0] for aiu output write 0 when writing. 0 is returned after a read. (2) aiuobahreg (0x0b00 002a) bit d15 d14 d13 d12 d11 d10 d9 d8 name aiuoba[31] aiuoba[30] aiuoba[29] aiuoba[28] aiuoba[27] aiuoba[26] aiuoba[25] aiuoba[24] r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bitd7d6d5d4d3d2d1d0 name aiuoba[23] aiuoba[22] aiuoba[21] aiuoba[20] aiuoba[19] aiuoba[18] aiuoba[17] aiuoba[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15:9] aiuoba[31:25] dma base address [31:25] for aiu output write 0 when writing. 0 is returned after a read. d[8:0] aiuoba[24:16] dma base address [24:16] for aiu output chapter 11 dmaau (dma addr ess unit) 277 aiuobalreg and aiuobahreg are used to set the base addresses for the dma channel used for audio output (playback). the addresses set to this register become dma start addresses. the dma channel used for audio output is retained in dram as a 2-kbyte buffer that starts at the address which is generated by masking the low-order 10 bits of the dma start address. chapter 11 dmaau (dma addr ess unit) 278 11.2.4 aiu out dma address registers (1) aiuoalreg (0x0b00 002c) bit d15 d14 d13 d12 d11 d10 d9 d8 name aiuoa[15] aiuoa[14] aiuoa[13] aiuoa[12] aiuoa[11] aiuoa[10] aiuoa[9] aiuoa[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 0 0 0 other resets 1 1 1 1 1 0 0 0 bitd7d6d5d4d3d2d1d0 name aiuoa[7] aiuoa[6] aiuoa[5] aiuoa[4] aiuoa[3] aiuoa[2] aiuoa[1] aiuoa[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:0] aiuoa[15:0] next dma address [15:0] to be accessed for aiu output channel (2) aiuoahreg (0x0b00 002e) bit d15 d14 d13 d12 d11 d10 d9 d8 name aiuoa[31] aiuoa[30] aiuoa[29] aiuoa[28] aiuoa[27] aiuoa[26] aiuoa[25] aiuoa[24] r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bitd7d6d5d4d3d2d1d0 name aiuoa[23] aiuoa[22] aiuoa[21] aiuoa[20] aiuoa[19] aiuoa[18] aiuoa[17] aiuoa[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15:0] aiuoa[31:16] next dma address [31:16] to be accessed for aiu output channel chapter 11 dmaau (dma addr ess unit) 279 11.2.5 fir dma base address registers (1) firbalreg (0x0b00 0030) bit d15 d14 d13 d12 d11 d10 d9 d8 name firba[15] firba[14] firba[13] firba[12] firba[11] firba[10] firba[9] firba[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 0 0 0 other resets 1 1 1 1 1 0 0 0 bitd7d6d5d4d3d2d1d0 name firba[7] firba[6] firba[5] firba[4] firba[3] firba[2] firba[1] firba[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:0] firba[15:0] fir dma base address [15:0] (2) firbahreg (0x0b00 0032) bit d15 d14 d13 d12 d11 d10 d9 d8 name firba[31] firba[30] firba[29] firba[28] firba[27] firba[26] firba[25] firba[24] r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bitd7d6d5d4d3d2d1d0 name firba[23] firba[22] firba[21] firba[20] firba[19] firba[18] firba[17] firba[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15:9] firba[31:25] fir dma base address [31:25] write 0 when writing. 0 is returned after a read. d[8:0] firba[24:16] fir dma base address [24:16] firbalreg and firbahreg are used to set the base addresses for the fir dma channel. the addresses set to this register become dma start addresses. the fir dma channel is retained in dram as a 2-kbyte buffer that starts at the address that is generated by masking the low-order 10 bits of the dma start address. chapter 11 dmaau (dma addr ess unit) 280 11.2.6 fir dma address registers (1) firalreg (0x0b00 0034) bit d15 d14 d13 d12 d11 d10 d9 d8 name fira[15] fira[14] fira[13] fira[12] fira[11] fira[10] fira[9] fira[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 0 0 0 other resets 1 1 1 1 1 0 0 0 bitd7d6d5d4d3d2d1d0 name fira[7] fira[6] fira[5] fira[4] fira[3] fira[2] fira[1] fira[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:0] fira[15:0] next dma address [15:0] to be accessed by fir channel (2) firahreg (0x0b00 0036) bit d15 d14 d13 d12 d11 d10 d9 d8 name fira[31] fira[30] fira[29] fira[28] fira[27] fira[26] fira[25] fira[24] r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bitd7d6d5d4d3d2d1d0 name fira[23] fira[22] fira[21] fira[20] fira[19] fira[18] fira[17] fira[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15:0] fira[31:16] next dma address [31:16] to be accessed by fir channel 281 chapter 12 dcu (dma control unit) this chapter describes the dcu registers operations and settings. 12.1 general the dcu register is used for dma control. specifically, it controls acknowledgment from the bcu that handles bus arbitration and dma requests from the on-chip peripheral i/o units (aiu and fir). it also controls dma enable/prohibit settings. 12.2 dma priority control when a conflict occurs between dma requests sent from on-chip peripheral i/o units, the following priority levels are used to resolve the conflict. these priority levels cannot be changed. table 12-1. dma priority levels priority level type of dma operation high audio input (recording) n audio output (playback) low fir transmission/reception 12.3 register set the dcu register set is described below. table 12-2. dcu registers address r/w register symbols function 0x0b00 0040 r/w dmarstreg dma reset register 0x0b00 0042 r dmaidlereg dma idle register 0x0b00 0044 r/w dmasenreg dma sequencer enable register 0x0b00 0046 r/w dmamskreg dma mask register 0x0b00 0048 r/w dmareqreg dma request register 0x0b00 004a r/w tdreg transfer direction register these registers are described in detail below. chapter 12 dcu (dma control unit) 282 12.3.1 dmarstreg (0x0b00 0040) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved dmarst r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] dmarst reset dma controller 0 : reset 1 : normal this register is used to reset the dma controller. chapter 12 dcu (dma control unit) 283 12.3.2 dmaidlereg (0x0b00 0042) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved dmaistat r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] dmaistat display dma sequencer status 1 : d_idle status 0 : dma busy this register is used to display the dma sequencer status. chapter 12 dcu (dma control unit) 284 12.3.3 dmasenreg (0x0b00 0044) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved dmasen r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] dmasen enable dma sequencer 1 : enable 0 : prohibit this register is used to enable/prohibit the dma sequencer. chapter 12 dcu (dma control unit) 285 12.3.4 dmamskreg (0x0b00 0046) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved dmamskain dmamsk aout reserved dmamsk fout r/w r r r r r/w r/w r r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..4] reserved write 0 when writing. 0 is returned after a read. d[3] dmamskain audio input dma transfer enable/prohibit 1 : enable 0 : prohibit d[2] dmamskaout audio output dma transfer enable/prohibit 1 : enable 0 : prohibit d[1] reserved write 0 when writing. 0 is returned after a read. d[0] dmamskfout fir transmission dma transfer enable/prohibit 1 : enable 0 : prohibit this register is used to enable/prohibit various types of dma transfers. the dma transfer enable bits should be set when the units that receive dma service have been stopped or when there are no pending dma requests. if any of the above bits are set to a unit while a dma request is pending for that unit, the cpus operation will be undefined. chapter 12 dcu (dma control unit) 286 12.3.5 dmareqreg (0x0b00 0048) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved drqain drqaout reserved drqfout r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..4] reserved write 0 when writing. 0 is returned after a read. d[3] drqain audio input dma transfer request 1 : request pending 0 : no request d[2] drqaout audio output dma transfer request 1 : request pending 0 : no request d[1] reserved write 0 when writing. 0 is returned after a read. d[0] drqfout fir transmission dma transfer request 1 : request pending 0 : no request this register is used to indicate whether or not there are any dma transfer requests. chapter 12 dcu (dma control unit) 287 12.3.6 tdreg (0x0b00 004a) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved fir r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] fir transfer direction of dma channel for fir transmission 1 : i/o o mem 0 : mem o i/o this register is used to set the transfer direction of dma channel for fir transmission. 288 [memo] 289 chapter 13 cmu (clock mask unit) this chapter describes the cmu registers operations and settings. 13.1 general as various input clocks (ctclock, i_seclk, firclock) are supplied from the cpu to each unit, a masking method enables power consumption to be curtailed in units that are not used. the units for which this masking method are used are the kiu, piu, aiu, siu, dsiu, fir, and hsp (software modem interface) units. the basic functions are described below. 1. control of tclock supplied to piu, aiu, siu, kiu, dsiu, and fir 2. control of internal clock (18.432 mhz) supplied to siu and hsp 3. control of internal clock (48 mhz) supplied to fir the initial value is 0, which specifies masking. no clock is supplied unless the cpu writes 1 to cmuclkmsk register. figure 13-1. block diagram of cmu and peripheral blocks cscmub piad(3:0) piastbb rst_gab bcu pmu ctclock i_seclk cmuout(15:0) tclk_siu tclk_kiu tclk_piu tclk_aiu tclk_dsiu i_tclk tclk_fir seclk_siu fclk seclk_hsp cmu firclock 13.2 register set the cmu register is listed below. table 13-1. cmu register address r/w register symbol function 0x0b00 0060 r/w cmuclkmsk cmu clock mask register this register is described in detail below. chapter 13 cmu (clock mask unit) 290 13.2.1 cmuclkmsk (0x0b00 0060) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved mskffir mskshsp mskssiu r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved mskdsiu mskfir mskkiu mskaiu msksiu mskpiu r/w r r r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:11] reserved write 0 when writing. 0 is returned after a read. d[10] mskffir supply/mask 48-mhz clock to fir unit 1 : supply 0 : mask d[9] mskshsp supply/mask 18.432-mhz clock to hsp unit 1 : supply 0 : mask d[8] mskssiu supply/mask 18.432-mhz clock to siu unit 1 : supply 0 : mask d[7:6] reserved write 0 when writing. 0 is returned after a read. d[5] mskdsiu supply/mask tclock to dsiu unit 1 : supply 0 : mask d[4] mskfir supply/mask tclock to fir unit 1 : supply 0 : mask d[3] mskkiu supply/mask tclock to kiu unit 1 : supply 0 : mask d[2] mskaiu supply/mask tclock to aiu unit 1 : supply 0 : mask d[1] msksiu supply/mask tclock to siu unit 1 : supply 0 : mask d[0] mskpiu supply/mask tclock to piu unit 1 : supply 0 : mask this register is used to mask the clocks that are supplied to the kiu, piu, aiu, siu, dsiu, fir, and hsp units. 291 chapter 14 icu (interrupt control unit) this chapter describes the icu registers operations and settings. 14.1 general the icu collects interrupt signals from the various on-chip peripheral units and transfers these interrupt signals (int0, int1, int2, int3, and nmi) to the cpu core. the functions of the icus internal blocks are briefly described below. ? addecicu decodes read/write addresses from the cpu that are used for icu registers. ? regicu this includes a register for interrupt masking. the initial value is 0, which specifies masking. no interrupt signal is supplied to cpu core unless the cpu writes 1 to this register. ? outicu this is the general icu output that follows masking of interrupts (all output is at the rising edge of i_mclkin). it also controls the interrupt masking signal (doze_mskint) used for settings during suspend mode, assertion of the general interrupt source signal (int_all), and the memdrv assertion timing signal (doze_memdrv) that is used when resetting from suspend mode. the signals used to notice interrupt request to the cpu are as below. nmi : battint_intr only switching between nmi and int0 is enabled according to this registers settings. because nmis interrupt masking cannot be controlled by means of software, switch to int0 to mask battint_intr. int3 : hsp_intr only int2 : rtc_long2_intr only int1 : rtc_long1_intr only the it (interval timer) and hsp interrupts require more responsiveness than do other interrupt sources. int0 : all other interrupts for details of the interrupt sources, see the register set. chapter 14 icu (interrupt control unit) 292 how an interrupt request is notified to the cpu core is shown below. if an interrupt request occurs in the peripheral units, the corresponding bit in the interrupt indication register of level 2 (xxxintreg) is set to 1. the interrupt indication register is anded bit-wise with the corresponding interrupt mask register of level 2 (mxxxintreg). if the occurred interrupt request is enabled (set to 1) in the mask register, the interrupt request is notified to the interrupt indication register of level 1 (sysintreg) and the corresponding bit is set to 1. at this time, the interrupt requests from the same register of level 2 are notified to the sysintreg as a single interrupt request. interrupt requests from some units directly set their corresponding bits in the sysintreg. the sysintreg is anded bit-wise with the interrupt mask register of level 1 (msysintreg). if the interrupt request is enabled by msysintreg (set to 1), a corresponding interrupt request signal is output from the icu to the cpu core. battint is connected to the nmi or int0 signal of the cpu core (selected by setting of nmireg). rtc_long signals are connected to the int3 signal of the cpu core. the other interrupt requests are connected to the int0 signal of the cpu core as a one interrupt request. the following figure shows an outline of interrupt control in the icu. chapter 14 icu (interrupt control unit) 293 figure 14-1. interrupt control outline mdsiuintreg msysint1reg msysint2reg sysint1reg sysint2reg dsiuintreg buserrint softintreg dozepiuint int0 int1 (battint n ote ) (all interrupts except for battint note and rtclongint) (rtclong1int) ledint mgiuintlreg giuintlreg and/or and/or nmi 17 17 int2 (rtclong2int) int3 (hspint) hspint siuint mfirintreg firintreg and/or and/or interrupt indication registers interrupt mask registers and/or logic (checking masks bit by bit and summarizing interrupt requests from the registers) 7 6 5 5 4 4 16 16 mkiuintreg kiuintreg maiuintreg aiuintreg tclkint battint powerint rtclong2int rtclong1int etimerint mpiuintreg piuintreg and/or and/or and/or 3 3 7 7 6 6 level 2 level 1 mg iuinthreg giuinthreg and/or 16 16 note which of nmi or int0 is used for battint is selected by setting of nmireg. chapter 14 icu (interrupt control unit) 294 14.2 register set the icu registers are listed below. table 14-1. icu registers address r/w register symbols function 0x0b00 0080 r sysint1reg level 1 system interrupt register 1 0x0b00 0082 r piuintreg level 2 piu interrupt register 0x0b00 0084 r aiuintreg level 2 aiu interrupt register 0x0b00 0086 r kiuintreg level 2 kiu interrupt register 0x0b00 0088 r giuintlreg level 2 giu interrupt register low 0x0b00 008a r dsiuintreg level 2 dsiu interrupt register 0x0b00 008c r/w msysint1reg level 1 mask system interrupt register 1 0x0b00 008e r/w mpiuintreg level 2 mask piu interrupt register 0x0b00 0090 r/w maiuintreg level 2 mask aiu interrupt register 0x0b00 0092 r/w mkiuintreg level 2 mask kiu interrupt register 0x0b00 0094 r/w mgiuintlreg level 2 mask giu interrupt register low 0x0b00 0096 r/w mdsiuintreg level 2 mask dsiu interrupt register 0x0b00 0098 r/w nmireg nmi register 0x0b00 009a r/w softintreg software interrupt register 0x0b00 0200 r sysint2reg level 1 system interrupt register 2 0x0b00 0202 r giuinthreg level 2 giu interrupt register high 0x0b00 0204 r firintreg level 2 fir interrupt register 0x0b00 0206 r/w msysint2reg level 1 mask system interrupt register 2 0x0b00 0208 r/w mgiuinthreg level 2 mask giu interrupt register high 0x0b00 020a r/w mfirintreg level 2 mask fir interrupt register these registers are described in detail below. chapter 14 icu (interrupt control unit) 295 14.2.1 sysint1reg (0x0b00 0080) (1/2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved doze piuintr reserved softintr wrber rintr siuintr giuintr r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name kiuintr aiuintr piuintr reserved etimer intr rtcl1intr power intr batintr r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..14] reserved write 0 when writing. 0 is returned after a read. d[13] dozepiuintr piu interrupt during suspend mode 1 : occurred 0 : normal d[12] reserved write 0 when writing. 0 is returned after a read. d[11] softintr software interrupt (occurs by setting the softintreg) 1 : occurred 0 : normal d[10] wrberrintr bus error interrupt 1 : occurred 0 : normal d[9] siuintr siu interrupt 1 : occurred 0 : normal d[8] giuintr giu interrupt 1 : occurred 0 : normal d[7] kiuintr kiu interrupt 1 : occurred 0 : normal d[6] aiuintr aiu interrupt 1 : occurred 0 : normal chapter 14 icu (interrupt control unit) 296 (2/2) bit name function d[5] piuintr piu interrupt 1 : occurred 0 : normal d[4] reserved write 0 when writing. 0 is returned after a read. d[3] etimerintr etimer interrupt 1 : occurred 0 : normal d[2] rtcl1intr rtclong1 interrupt 1 : occurred 0 : normal d[1] powerintr powersw interrupt 1 : occurred 0 : normal d[0] batintr battery interrupt 1 : occurred 0 : normal this register indicates when various interrupts occur in the v r 4102 system. chapter 14 icu (interrupt control unit) 297 14.2.2 piuintreg (0x0b00 0082) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved padcmd intr padadp intr padpage1 intr padpage0 intr paddlost intr reserved penchg intr r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..7] reserved write 0 when writing. 0 is returned after a read. d[6] padcmdintr piu command scan interrupt. this interrupt occurs when command scan found valid data. 1 : occurred 0 : normal d[5] padadpintr piu ad port scan interrupt. this interrupt occurs when ad port scan found a set of valid data. 1 : occurred 0 : normal d[4] padpage1intr piu data buffer page 1 interrupt. this interrupt occurs when a set of valid data is stored in page 1 of data buffer. 1 : occurred 0 : normal d[3] padpage0intr piu data buffer page 0 interrupt. this interrupt occurs when a set of valid data is stored in page 0 of data buffer. 1 : occurred 0 : normal d[2] paddlostintr a/d data timeout interrupt. this interrupt occurs when a set of data did not found within specified time. 1 : occurred 0 : normal d[1] reserved write 0 when writing. 0 is returned after a read. d[0] penchgintr touch panel contact status change interrupt 1: change has occurred 0: no change this register indicates when various piu-related interrupts occur. chapter 14 icu (interrupt control unit) 298 14.2.3 aiuintreg (0x0b00 0084) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved intmend intm intmidle intmst r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved intsend ints intsidle reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:12] reserved write 0 when writing. 0 is returned after a read. d[11] intmend audio input (mic) dma buffer 2 page interrupt 1 : occurred 0 : normal d[10] intm audio input (mic) dma buffer 1 page interrupt 1 : occurred 0 : normal d[9] intmidle audio input (mic) idle interrupt (received data is lost). this interrupt occurs if valid data exists in midatreg when data was received from a/d converter. 1 : occurred 0 : normal d[8] intmst audio input (mic) receive completion interrupt. this interrupt occurs when 10-bit converted data was received from the a/d converter. 1 : occurred 0 : normal d[7:4] reserved write 0 when writing. 0 is returned after a read d[3] intsend audio output (speaker) dma buffer 2 page interrupt 1 : occurred 0 : normal d[2] ints audio output (speaker) dma buffer 1 page interrupt 1 : occurred 0 : normal d[1] intsidle audio output (speaker) idle interrupt (mute). this interrupt occurs if there is no valid data in sodatreg when data was transferred to d/a. 1 : occurred 0 : normal d[0] reserved write 0 when writing. 0 is returned after a read this register indicates when various aiu-related interrupts occur. chapter 14 icu (interrupt control unit) 299 14.2.4 kiuintreg (0x0b00 0086) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved kdatlost kdatrdy scanint r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..3] reserved write 0 when writing. 0 is returned after a read. d[2] kdatlost key scan data lost interrupt 1 : occurred 0 : normal d[1] kdatrdy key scan data complete interrupt 1 : occurred 0 : normal d[0] scanint key input detect interrupt 1 : occurred 0 : normal this register indicates when various kiu-related interrupts occur. chapter 14 icu (interrupt control unit) 300 14.2.5 giuintlreg (0x0b00 0088) bit d15 d14 d13 d12 d11 d10 d9 d8 name ints[15] ints[14] ints[13] ints[12] ints[11] ints[10] ints[9] ints[8] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name ints[7] ints[6] ints[5] ints[4] ints[3] ints[2] ints[1] ints[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] ints[15..0] interrupt to gpio[15..0] pin 1 : occurred 0 : normal this register indicates when various giu-related interrupts occur. chapter 14 icu (interrupt control unit) 301 14.2.6 dsiuintreg (0x0b00 008a) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved intdcts intser0 intsr0 intst0 r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bit name function d[15..12] reserved write 0 when writing. 0 is returned after a read. d[11] intdcts dcts# change interrupt 1 : occurred 0 : normal d[10] intser0 debug serial receive error interrupt 1 : occurred 0 : normal d[9] intsr0 debug serial receive complete interrupt 1 : occurred 0 : normal d[8] intst0 debug serial transmit complete interrupt 1 : occurred 0 : normal d[7..1] reserved write 0 when writing. 0 is returned after a read. d[0] reserved write 1 when writing. 1 is returned after a read. this register indicates when various dsiu-related interrupts occur. chapter 14 icu (interrupt control unit) 302 14.2.7 msysint1reg (0x0b00 008c) (1/2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved doze piuintr reserved softintr wrberr intr siuintr giuintr r/w r r r/w r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name kiuintr aiuintr piuintr reserved etimer intr rtcl1intr power intr batintr r/w r/w r/w r/w r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..14] reserved write 0 when writing. 0 is returned after a read. d[13] dozepiuintr piu interrupt enable during suspend mode 1 : enable 0 : prohibit d[12] reserved write 0 when writing. 0 is returned after a read. d[11] softintr software interrupt (occurs by setting the softintreg) enable 1 : enable 0 : prohibit d[10] wrberrintr bus error interrupt enable 1 : enable 0 : prohibit d[9] siuintr siu interrupt enable 1 : enable 0 : prohibit d[8] giuintr giu interrupt enable 1 : enable 0 : prohibit d[7] kiuintr kiu interrupt enable 1 : enable 0 : prohibit d[6] aiuintr aiu interrupt enable 1 : enable 0 : prohibit chapter 14 icu (interrupt control unit) 303 (2/2) bit name function d[5] piuintr piu interrupt enable 1 : enable 0 : prohibit d[4] reserved write 0 when writing. 0 is returned after a read. d[3] etimerintr etimer interrupt enable 1 : enable 0 : prohibit d[2] rtcl1intr rtclong1 timer interrupt enable 1 : enable 0 : prohibit d[1] powerintr powersw interrupt enable 1 : enable 0 : prohibit d[0] batintr battery interrupt enable 1 : enable 0 : prohibit this register is used to mask various interrupts that occur in the v r 4102 system. chapter 14 icu (interrupt control unit) 304 14.2.8 mpiuintreg (0x0b00 008e) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved padcmd intr padadp intr padpage1 intr padpage0 intr paddlost intr reserved penchg intr r/w r r/w r/w r/w r/w r/w r r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..7] reserved write 0 when writing. 0 is returned after a read. d[6] padcmdintr piu command scan interrupt enable 1 : enable 0 : prohibit d[5] padadpintr piu a/d port scan interrupt enable 1 : enable 0 : prohibit d[4] padpage1intr piu data buffer page 1 interrupt enable 1 : enable 0 : prohibit d[3] padpage0intr piu data buffer page 0 interrupt enable 1 : enable 0 : prohibit d[2] paddlostintr a/d data timeout interrupt enable 1 : enable 0 : prohibit d[1] reserved write 0 when writing. 0 is returned after a read. d[0] penchgintr touch panel contact status change interrupt enable 1 : enable 0 : prohibit this register is used to mask various piu-related interrupts. chapter 14 icu (interrupt control unit) 305 14.2.9 maiuintreg (0x0b00 0090) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved intmend intm intmidle intmst r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved intsend ints intsidle reserved r/w r r r r r/w r/w r/w r rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:12] reserved write 0 when writing. 0 is returned after a read. d[11] intmend audio input (mic) dma buffer 2 page interrupt enable 1 : enable 0 : prohibit d[10] intm audio input (mic) dma buffer 1 page interrupt enable 1 : enable 0 : prohibit d[9] intmidle audio input (mic) idle interrupt (received data is lost) enable 1 : enable 0 : prohibit d[8] intmst audio input (mic) receive complete interrupt 1 : enable 0 : prohibit d[7:4] reserved write 0 when writing. 0 is returned after a read. d[3] intsend audio output (speaker) dma buffer 2 page interrupt enable 1 : enable 0 : prohibit d[2] ints audio output (speaker) dma buffer 1 page interrupt enable 1 : enable 0 : prohibit d[1] intsidle audio output (speaker) idle interrupt (mute) enable 1 : enable 0 : prohibit d[0] reserved write 0 when writing. 0 is returned after a read. this register is used to mask various aiu-related interrupts. chapter 14 icu (interrupt control unit) 306 14.2.10 mkiuintreg (0x0b00 0092) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved kdatlost kdatrdy scanint r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..3] reserved write 0 when writing. 0 is returned after a read. d[2] kdatlost key data scan lost interrupt enable 1 : enable 0 : prohibit d[1] kdatrdy key scan data complete interrupt enable 1 : enable 0 : prohibit d[0] scanint key input detect interrupt enable 1 : enable 0 : prohibit this register is used to mask various kiu-related interrupts. chapter 14 icu (interrupt control unit) 307 14.2.11 mgiuintlreg (0x0b00 0094) bit d15 d14 d13 d12 d11 d10 d9 d8 name ints[15] ints[14] ints[13] ints[12] ints[11] ints[10] ints[9] ints[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name ints[7] ints[6] ints[5] ints[4] ints[3] ints[2] ints[1] ints[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] ints[15..0] gpio[15..0] pin interrupt enable 1 : enable 0 : prohibit this register is used to mask various giu-related interrupts. chapter 14 icu (interrupt control unit) 308 14.2.12 mdsiuintreg (0x0b00 0096) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved intdcts intser0 intsr0 intst0 r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..12] reserved write 0 when writing. 0 is returned after a read. d[11] intdcts dcts# change interrupt enable 1 : enable 0 : prohibit d[10] intser0 debug serial data receive error interrupt enable 1 : enable 0 : prohibit d[9] intsr0 debug serial data receive complete interrupt enable 1 : enable 0 : prohibit d[8] intst0 debug serial data transmit complete interrupt enable 1 : enable 0 : prohibit d[7..0] reserved write 0 when writing. 0 is returned after a read. this register is used to mask various dsiu-related interrupts. chapter 14 icu (interrupt control unit) 309 14.2.13 nmireg (0x0b00 0098) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved nmiorint r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] nmiorint low battery detect interrupt type setting 1 : int0 0 : nmi this register is used to set the type of interrupt used to notify the v r 4100 cpu core when a low battery detect interrupt has occurred. chapter 14 icu (interrupt control unit) 310 14.2.14 softintreg (0x0b00 009a) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved softintr[3] softintr[2] softintr[1] softintr[0] r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..4] reserved write 0 when writing. 0 is returned after a read. d[3..0] softintr[3..0] set/clear software interrupt 1 : set 0 : clear this register is used to set software interrupts. each bit can be set separately, and can cause four types of interrupts. chapter 14 icu (interrupt control unit) 311 14.2.15 sysint2reg (0x0b00 0200) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved dsiuintr firintr tclkintr hspintr ledintr rtcl2intr r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..6] reserved write 0 when writing. 0 is returned after a read. d[5] dsiuintr dsiu interrupt 1 : occurred 0 : normal d[4] firintr fir interrupt 1 : occurred 0 : normal d[3] tclkintr tclock counter interrupt 1 : occurred 0 : normal d[2] hspintr hsp interrupt 1 : occurred 0 : normal d[1] ledintr led interrupt 1 : occurred 0 : normal d[0] rtcl2intr rtclong2 timer interrupt 1 : occurred 0 : normal this register indicates when various interrupts occur in the v r 4102 system. chapter 14 icu (interrupt control unit) 312 14.2.16 giuinthreg (0x0b00 0202) bit d15 d14 d13 d12 d11 d10 d9 d8 name ints[31] ints[30] ints[29] ints[28] ints[27] ints[26] ints[25] ints[24] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name ints[23] ints[22] ints[21] ints[20] ints[19] ints[18] ints[17] ints[16] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] ints[31..16] gpio[31..16] pin interrupt 1 : occurred 0 : normal this register indicates when various giu-related interrupts occur. chapter 14 icu (interrupt control unit) 313 14.2.17 firintreg (0x0b00 0204) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved firint fdpint[4] fdpint[3] fdpint[2] fdpint[1] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..5] reserved write 0 when writing. 0 is returned after a read. d[4] firint interrupt from fir unit 1 : occurred 0 : normal d[3] fdpint[4] fir dma buffer (receive side) 2 page interrupt 1 : occurred 0 : normal d[2] fdpint[3] fir dma buffer (transmit side) 2 page interrupt 1 : occurred 0 : normal d[1] fdpint[2] fir dma buffer (receive side) 1 page interrupt 1 : occurred 0 : normal d[0] fdpint[1] fir dma buffer (transmit side) 1 page interrupt 1 : occurred 0 : normal this register indicates when various fir-related interrupts occur. when fdpint[4] or fdpint[3] is set to 1, the v r 4102 stops the dma requests. when fdpint[2] or fdpint[1] is set to 1 during the fdpcnt bit of the dpcntr register (0x0c00 004c) is set to 1 (dma buffer 1 page interrupt is enabled), the v r 4102 stops the dma requests. chapter 14 icu (interrupt control unit) 314 14.2.18 msysint2reg (0x0b00 0206) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved dsiuintr firintr tclkintr hspintr ledintr rtcl2intr r/w r r r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..6] reserved write 0 when writing. 0 is returned after a read. d[5] dsiuintr dsiu interrupt enable 1 : enable 0 : prohibit d[4] firintr fir interrupt enable 1 : enable 0 : prohibit d[3] tclkintr tclock counter interrupt enable 1 : enable 0 : prohibit d[2] hspintr hsp interrupt enable 1 : enable 0 : prohibit d[1] ledintr led interrupt enable 1 : enable 0 : prohibit d[0] rtcl2intr rtclong2 timer interrupt enable 1 : enable 0 : prohibit this register is used to mask various interrupts in the v r 4102 system. chapter 14 icu (interrupt control unit) 315 14.2.19 mgiuinthreg (0x0b00 0208) bit d15 d14 d13 d12 d11 d10 d9 d8 name ints[31] ints[30] ints[29] ints[28] ints[27] ints[26] ints[25] ints[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name ints[23] ints[22] ints[21] ints[20] ints[19] ints[18] ints[17] ints[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] ints[31..16] enable gpio[31..16] pin interrupt 1 : enable 0 : prohibit this register is used to mask various giu-related interrupts. chapter 14 icu (interrupt control unit) 316 14.2.20 mfirintreg (0x0b00 020a) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved firint fdpint[4] fdpint[3] fdpint[2] fdpint[1] r/w r r r r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..5] reserved write 0 when writing. 0 is returned after a read. d4 firint fir unit interrupt enable 1 : enable 0 : prohibit d[3] fdpint[4] fir dma buffer 2 page interrupt (receive side) enable 1 : enable 0 : prohibit d[2] fdpint[3] fir dma buffer 2 page interrupt (transmit side) enable 1 : enable 0 : prohibit d[1] fdpint[2] fir dma buffer 1 page interrupt (receive side) enable 1 : enable 0 : prohibit d[0] fdpint[1] fir dma buffer 1 page interrupt (transmit side) enable 1 : enable 0 : prohibit this register is used to mask various fir-related interrupts. chapter 14 icu (interrupt control unit) 317 14.3 notes for register setting there is no register setting flow in relation to the icu. with regard to the interrupt mask registers, the initial setting is initial = 0= mask after start up. therefore, enough masks must be cleared to provide sufficient interrupts for the cpus start-up processing. this is always necessary when battint_intr = nmi. the initial setting for battint_intr is initial = 0 = nmi. a 1 must be written to the register to switch this setting to int0. soft_intr is a software interrupt that is output to int0 by setting 1 to the softintreg register. writing a 0 clears the interrupt. 318 [memo] 319 chapter 15 pmu (power management unit) this chapter describes the pmus operation and register settings. 15.1 general the pmu performs power management within the v r 4102 and controls the power supply throughout the system which includes the v r 4102. ? reset control ? shutdown control ? power-on control ? low-power mode control the pmu also performs settings to use the gpio[12:9], gpio[3:0] signals as a start-up factor. 15.1.1 reset control the operations of the rtc, peripheral units, cpu core, and pmuintreg bit settings during a reset are listed below. table 15-1. bit operations during reset reset type rtc peripheral units cpu core pmuintreg rtc reset reset reset cold reset rtcrst=1 rstsw reset active reset cold reset rstsw=1 (1) rtc reset when the rtcrst# signal is asserted, the pmu resets all peripheral units including the rtc unit. it also asserts the ccoldresetb and creset signals (internal) and resets the cpu core. in addition, the rtcrst bit in pmuintreg is set (to 1). after the cpu is restarted, the rtcrst bit must be checked and cleared (to 0) by software. (2) rstsw reset when the rstsw# signal is asserted, the pmu resets all peripheral units except for rtc and pmu. next, it asserts the ccoldresetb and creset signals (internal) and resets the cpu core. in addition, the rstsw bit in pmuintreg is set (to 1). after the cpu is restarted, the rstsw bit must be checked and cleared (to 0) by software. chapter 15 pmu (power management unit) 320 15.1.2 shutdown control the operations of the rtc, peripheral units, cpu core, and pmuintreg bit settings during a reset are listed below. table 15-2. bit operations during shutdown shutdown type rtc peripheral units cpu core pmuintreg hal timer shutdown active reset cold reset haltimerrst=1 deadmans sw shutdown active reset cold reset timoutrst=1 software shutdown active reset cold reset - battery low shutdown active reset cold reset battinh=1 battery lock cancel shutdown active reset cold reset - (1) hal timer shutdown after the cpu is activated (following the mode change from shutdown or hibernate mode to fullspeed mode), the software must write 1 to pmucntregs haltimerrst bit within about four seconds to clear the hal timer. if the hal timer is not reset within about four seconds after the cpu is activated, the pmu resets all peripheral units except for rtc and pmu. next, it asserts the ccoldresetb and creset signals (internal) and resets the cpu core. in addition, the timoutrst bit in pmuintreg is set (to 1). after the cpu is restarted, the timoutrst bit must be checked and cleared (to 0) by software. (2) deadmans sw shutdown when the deadmans sw function is enabled, the software must write 1 to dsuclrregs dswclr bit each time a deadmans sw setting is made, to clear the deadmans sw counter (for details, see chapter 17). if the deadmans sw counter is not cleared during a deadmans sw setting, the pmu resets all peripheral units except for rtc and pmu. next, it asserts the ccoldresetb and creset signals (internal) and resets the cpu core. in addition, the dmsrst bit in pmuintreg is set (to 1). after the cpu is restarted, the dmsrst bit must be checked and cleared (to 0) by software. (3) software shutdown when the hibernate instruction is executed, the pmu checks for currently pending interrupts. if there are no pending interrupts, it stops the cpu clock. it then resets all peripheral units except for rtc and pmu. the pmu register contents do not change. chapter 15 pmu (power management unit) 321 15.1.3 power-on control the causes of cpu activation (mode change from shutdown mode or hibernate mode to fullspeed mode) are called power-on factors. there are twelve power-on factors: a power switch interrupt (power), eight types of gpio activation interrupts (gpio[12:9], gpio[3..0]), a dcd interrupt (dcd#), a touch panel interrupt, and an alarm interrupt. battery low detection is a factor that prevents cpu activation. (1) activation via power switch interrupt when the power signal is asserted, the pmu asserts the poweron signal and provides external notification that the cpu is being activated. after asserting the poweron signal, the pmu checks the battinh signal and then de-asserts the poweron signal. if the battinh/battint# signal is high (1), the pmu cancels peripheral unit reset, then starts the cold reset sequence to activate the cpu core. if the battinh/battint# signal is low (0), the pmu sets 1 to pmuintregs battinh bit and then performs another shutdown. after the cpu is restarted, the battinh bit must be checked and cleared (to 0) by software. figure 15-1. activation via power switch interrupt (battinh/battint# = 1) battinh/ battint# (i) mpower(o) poweron(o) power(i) rtc(internal) h figure 15-2. activation via power switch interrupt (battinh/battint# = 0) battinh / battint# (i) mpower(o) poweron(o) power(i) rtc(internal) l l chapter 15 pmu (power management unit) 322 (2) activation via gpio activation interrupt when the gpio[12:9], gpio[3..0] signal is asserted, the pmu checks the gpio[12:9], gpio[3..0]s activation interrupt enable bit. if gpio[12:9], gpio[3..0] activation interrupts are enabled, the pmu asserts the poweron signal and provides external notification that the cpu is being activated (since the gpio[12:9], gpio[2..0] activation enable interrupt bit is cleared after an rtc is reset, the gpio[12:9], gpio[2..0] signal cannot be used for activation immediately after an rtc reset. however, activation can occur at the falling edge of the gpio[3] signal immediately after an rtc reset for gpio[3] only). the pmu asserts the poweron signal, then checks the battinh/ battint# signal and de-asserts the poweron signal. when the battinh/battint# signal is high (1), the pmu cancels peripheral unit reset, then starts the cold reset sequence to activate the cpu core. when the battinh/battint# signal is low (0), the pmu sets 1 to pmuintregs battinh bit and then performs another shutdown. after the cpu is restarted, the battinh bit must be checked and cleared (to 0) by software. the cpu sets 1 to the corresponding gpiointr bit in the pmuintreg regardless of whether activation succeeds or fails. figure 15-3. activation via gpio activation interrupt (battinh/battint# = 1) battinh/ battint#(i) mpower(o) poweron(o) gpio[12:9]/ gpio[3..0](i/o) rtc(internal) h figure 15-4. activation via gpio activation interrupt (battinh/battint# = 0) battinh/ battint#(i) mpower(o) poweron(o) gpio[12:9]/ gpio[3..0](i/o) rtc(internal) l l chapter 15 pmu (power management unit) 323 (3) activation via dcd interrupt when the dcd# signal is asserted, the pmu asserts the poweron signal and provides external notification that the cpu is being activated. after asserting the poweron signal, the pmu checks the battinh/battint# signal and then de-asserts the poweron signal. if the battinh/battint# signal is high (1), the pmu cancels peripheral unit reset, then starts the cold reset sequence to activate the cpu core. if the battinh/battint# signal is low (0), the pmu sets 1 to pmuintregs battinh bit and then performs another shutdown. after the cpu is restarted, the battinh bit must be checked and cleared (to 0) by software. the pmuintregs dcdst bit does not indicate whether a dcd interrupt has occurred but instead reflects the current status of the dcd# pin. caution while poweron is active, the pmu cannot recognize changes in the dcd# signal. if the dcd# state when poweron is active is different from the dcd# state when poweron is inactive, the change in the dcd# signal is detected only after poweron is inactive. however, if the dcd# state when poweron is active is the same as the dcd# state when poweron is inactive, any changes in the dcd# signal that occur while poweron is active are not detected. figure 15-5. activation via dcd interrupt (battinh/battint# = 1) battinh/ battint#(i) mpower(o) poweron(o) dcd#(i) rtc(internal) h figure 15-6. activation via dcd interrupt (battinh/battint# = 0) battinh/ battint#(i) mpower(o) poweron(o) dcd#(i) rtc(internal) l l chapter 15 pmu (power management unit) 324 (4) activation via alarm interrupt when the alarm interrupt (alarm_intr) signal is asserted, the pmu asserts the poweron signal and provides external notification that the cpu is being activated. after asserting the poweron signal, the pmu checks the battinh/battint# signal and then de-asserts the poweron signal. if the battinh/battint# signal is high (1), the pmu cancels peripheral unit reset, then starts the cold reset sequence to activate the cpu core. if the battinh/battint# signal is low (0), the pmu sets 1 to pmuintregs battinh bit and then performs another shutdown. after the cpu is restarted, the battinh bit must be checked and cleared (to 0) by software. figure 15-7. activation via alarm interrupt (battinh/battint# = 1) battinh/ battint#(i) mpower(o) poweron(o) alarm_intr(internal) rtc(internal) h figure 15-8. activation via alarm interrupt (battinh/battint# = 0) battinh/ battint#(i) mpower(o) poweron(o) alarm_intr(internal) rtc(internal) l l 15.1.4 power mode the v r 4102 supports the following four power modes. ? fullspeed mode ? standby mode ? suspend mode ? hibernate mode figure 15-9 illustrates the transition between the different power modes. chapter 15 pmu (power management unit) 325 to set standby, suspend, or hibernate mode from fullspeed mode, execute a standby, suspend, or hibernate instruction respectively. to set fullspeed mode from standby, suspend, or hibernate mode, generate an interrupt or perform any reset. table 15-3 outlines the power modes. figure 15-9. power mode state transition fullspeed mode standby mode suspend mode hibernate mode (4) (1) (3) (2) (6) (5) (1) (2) (3) (4) (5) (6) standby instruction & pipeline flash & sysad idle & pclock high all interrupts suspend instruction & pipeline flash & sysad idle & pclock high & tclock high & dram self refresh batteryint poweron rtcrst alarm keytouch pentouch gpio[3..0] gpio[14..9] dcd# rtclong hibernate instruction & pipeline flash & sysad idle & pclock high & tclock high & masterout high & dram self refresh poweron alarm dcd# gpio[3..0] gpio[12:9] chapter 15 pmu (power management unit) 326 table 15-3. power mode mode internal peripheral unit cpu core rtc icu dcu others fullspeed on on on selectable note on standby on on on selectable note off suspend on on off off off hibernate on off off off off off off off off off off note see chapter 13 for details. (1) fullspeed mode in fullspeed mode, all internal clocks and the bus clock operate. in this mode, all the functions of the v r 4102 can be executed. (2) standby mode in standby mode, all internal clocks, other than those provided to the internal peripheral units and the internal timer/interrupt unit of the cpu core, are fixed to high level. to switch to standby mode from fullspeed mode, first execute the standby instruction. the v r 4102 waits until the sysad bus (internal) enters idle status after the completion of the wb stage of the standby instruction. then, the internal clock is shut down, and the pipeline stops. pll, timer/interrupt clock, internal bus clocks (tclock, masterout), and rtc continue to operate. in standby mode, the processor returns to fullspeed mode when an interrupt occurs. at this time, the contents of bits indicating the states of pins in the peripheral units registers are undefined. the contents of other fields are retained. (3) suspend mode in suspend mode, all internal clocks (including tclock) other than those supplied to the rtc/icu/pmu internal peripheral units and the internal timer/interrupt unit of the cpu core are fixed to high level. to switch to suspend mode from fullspeed mode, first execute the suspend instruction. the v r 4102 waits until the sysad bus (internal) enters idle status after the completion of the wb stage of the suspend instruction, dram has entered self-refresh mode, and the mpower pin has been made inactive. then, the internal clocks (including tclock) are shut down, and the pipeline stops. pll, timer interrupt clock, masterout, and rtc continue to operate. if the suspend instruction is executed during dma transfer, the dram transfer is suspended, and operation is undefined. in suspend mode, the processor returns to fullspeed mode when an interrupt request from the peripheral units or any resets occur. at this time, the contents of bits indicating the states of pins in the peripheral units registers are undefined. the contents of other fields are retained. chapter 15 pmu (power management unit) 327 (4) hibernate mode in hibernate mode, all the clocks supplied to internal peripheral units other than rtc/icu/pmu and to the cpu core are fixed to high level. to switch to hibernate mode from fullspeed mode, first execute the hibernate instruction. the v r 4102 waits until the sysad bus (internal) enters idle status after the completion of the wb stage of the hibernate instruction, dram has entered self-refresh mode, and the mpower pin has been made inactive. then, the internal clocks (including tclock and masterout) are shut down, and the pipeline stops. pll also stops, but rtc continue to operate. in hibernate mode, the processor returns to fullspeed mode when it is alarmed from the rtc, the power-on switch is pressed, or dcd# pin is asserted. at this time, the contents of bits indicating the states of pins in the peripheral units registers and caches in the cpu core are undefined. the contents of other fields are retained. 15.2 register set the pmu registers are listed below. table 15-4. pmu registers address r/w register symbols function 0x0b00 00a0 r/w pmuintreg pmu interrupt/status register 0x0b00 00a2 r/w pmucntreg pmu control register 0x0b00 00a4 r/w pmuint2reg pmu interrupt register 2 0x0b00 00a6 r/w pmucnt2reg pmu control register 2 each register is described in detail below. chapter 15 pmu (power management unit) 328 15.2.1 pmuintreg (0x0b00 00a0) (1/2) bit d15 d14 d13 d12 d11 d10 d9 d8 name gpio3intr gpio2intr gpio1intr gpio0intr reserved dcdst rtcintr battinh r/w r/w r/w r/w r/w r r r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name battlock cardlock timoutrst rtcrst rstsw dmsrst battintr powersw intr r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 1 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15] gpio3intr gpio[3] activation interrupt detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[14] gpio2intr gpio[2] activation interrupt detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[13] gpio1intr gpio[1] activation interrupt detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[12] gpio0intr gpio[0] activation interrupt detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[11] reserved write 0 when writing. 0 is returned after a read. d[10] dcdst dcd# pin state. 1 : high 0 : low d[9] rtcintr rtc alarm interrupt detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[8] battinh battery low detection during activation. cleared to 0 when 1 is written. 1 : detected 0 : not detected chapter 15 pmu (power management unit) 329 (2/2) bit name function d[7] battlock battery lock interrupt detection note 1 : detected 0 : not detected d[6] cardlock pcmcia card lock interrupt detection note 1 : detected 0 : not detected d[5] timoutrst hal timer reset detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[4] rtcrst rtc reset detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[3] rstsw reset switch interrupt detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[2] dmsrst deadmans switch interrupt detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[1] battintr battery low detection during normal operation. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[0] powerswintr power switch interrupt detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected note these bits are used by software. these are never set by hardware, and their settings never affect hardware. this register is used to set whether the cpu detects a power-on factor and reset. it also indicates the status of the dcd# pin. chapter 15 pmu (power management unit) 330 15.2.2 pmucntreg (0x0b00 00a2) (1/2) bit d15 d14 d13 d12 d11 d10 d9 d8 name gpio3msk gpio2msk gpio1msk gpio0msk gpio3trg gpio2trg gpio1trg gpio0trg r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 0 0 0 1 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name standby reserved reserved reserved reserved haltimer rst reserved reserved r/w r/wrrrrr/wrr rtcrst 0 0 0 0 0 0 1 0 other resets 0 0 0 0 0 0 1 0 bit name function d[15] gpio3msk gpio[3] activation enable 1 : enable 0 : prohibit d[14] gpio2msk gpio[2] activation enable 1 : enable 0 : prohibit d[13] gpio1msk gpio[1] activation enable 1 : enable 0 : prohibit d[12] gpio0msk gpio[0] activation enable 1 : enable 0 : prohibit d[11] gpio3trg gpio[3] activation interrupt type 1 : falling edge detection 0 : rising edge detection d[10] gpio2trg gpio[2] activation interrupt type 1 : falling edge detection 0 : rising edge detection d[9] gpio1trg gpio[1] activation interrupt type 1 : falling edge detection 0 : rising edge detection d[8] gpio0trg gpio[0] activation interrupt type 1 : falling edge detection 0 : rising edge detection d[7] standby standby mode setting. this setting is performed only for software, and does not affect hardware in any way. 1 : standby mode 0 : normal mode note holds the value before reset chapter 15 pmu (power management unit) 331 (2/2) bit name function d[6..3] reserved write 0 when writing. 0 is returned after a read. d[2] haltimerrst hal timer reset 1 : reset 0 : set d[1] reserved write 1 when writing. 1 is returned after a read. d[0] reserved write 0 when writing. 0 is returned after a read. this register is used to set cpu shutdown and overall system management operations. the haltimerrst bit must be reset within about four seconds of activation. resetting of the haltimerrst bit indicates that the v r 4102 itself has been activated normally. if the haltimerrst bit is not reset within about four seconds of activation, program execution is regarded as abnormal (possibly due to a runaway) and an automatic shutdown is performed. the gpio[3..0]msk bits are used to set enable/prohibit for activation from hibernate mode when the corresponding interrupt (gpio[3..0]) occurs. the gpio3msk bit is set to 1 by rtcrst, and the other bits are cleared to 0 (prohibit). accordingly, the gpio[2..0] cannot be used for activation immediately after an rtcrst reset. the gpio activation interrupt is valid only when the cpus operation mode is hibernate mode. chapter 15 pmu (power management unit) 332 15.2.3 pmuint2reg (0x0b00 00a4) bit d15 d14 d13 d12 d11 d10 d9 d8 name gpio12intr gpio11intr gpio10intr gpio9intr reserved reserved reserved reserved r/w r/w r/w r/w r/w r r r r rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15] gpio12intr gpio[12] activation interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[14] gpio11intr gpio[11] activation interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[13] gpio10intr gpio[10] activation interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[12] gpio9intr gpio[9] activation interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected d[11:0] reserved write 0 when writing. 0 is returned after a read. this register is used to specify whether the gpio[12:9] interrupt is detected as a power-on factor. chapter 15 pmu (power management unit) 333 15.2.4 pmucnt2reg (0x0b00 00a6) bit d15 d14 d13 d12 d11 d10 d9 d8 name gpio12msk gpio11msk gpio10msk gpio9msk gpio12trg gpio11trg gpio10trg gpio9trg r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15] gpio12msk gpio[12] activation enable 1 : enable 0 : prohibit d[14] gpio11msk gpio[11] activation enable 1 : enable 0 : prohibit d[13] gpio10msk gpio[10] activation enable 1 : enable 0 : prohibit d[12] gpio9msk gpio[9] activation enable 1 : enable 0 : prohibit d[11] gpio12trg gpio[12] activation interrupt type 1 : falling edge detection 0 : rising edge detection d[10] gpio11trg gpio[11] activation interrupt type 1 : falling edge detection 0 : rising edge detection d[9] gpio10trg gpio[11] activation interrupt type 1 : falling edge detection 0 : rising edge detection d[8] gpio9trg gpio[9] activation interrupt type 1 : falling edge detection 0 : rising edge detection d[7:0] reserved write 0 when writing. 0 is returned after a read. this register is used to specify the settings for activation via gpio [12:9] interrupts. the gpio activation interrupt is valid only when the cpus operation mode is hibernate mode. 334 [memo] 335 chapter 16 rtc (realtime clock unit) this chapter describes the rtc units operations and register settings. 16.1 general the rtc unit has a total of four timers, including the following three types. ? rtclong this is a 24-bit programmable counter that counts down using 32.768-khz cycles. cycle interrupts occur for up to 512 seconds. the rtc unit includes two rtclong timers. ? tclockcount this is a 25-bit programmable counter that counts down using tclock cycles. cycle interrupts occur for up to 1 to 2 seconds. this counter is used for performance evaluation. ? elapsedtime this is a 48-bit up counter that counts up using 32.768-khz cycles. it counts up to 272 years before returning to zero. it includes 48-bit comparators (ecmphreg, ecmplreg, and ecmpmreg) and 48-bit alarm time registers (etimelreg, etimemreg, and etimehreg) to enable interrupts to occur at specified times. chapter 16 rtc (realtime clock unit) 336 16.2 register set the rtc registers are listed below. table 16-1. rtc registers address r/w register symbols function 0x0b00 00c0 r/w etimelreg elapsed time l register 0x0b00 00c2 r/w etimemreg elapsed time m register 0x0b00 00c4 r/w etimehreg elapsed time h register 0x0b00 00c8 r/w ecmplreg elapsed compare l register 0x0b00 00ca r/w ecmpmreg elapsed compare m register 0x0b00 00cc r/w ecmphreg elapsed compare h register 0x0b00 00d0 r/w rtcl1lreg rtc long 1 l register 0x0b00 00d2 r/w rtcl1hreg rtc long 1 h register 0x0b00 00d4 r rtcl1cntlreg rtc long 1 count l register 0x0b00 00d6 r rtcl1cnthreg rtc long 1 count h register 0x0b00 00d8 r/w rtcl2lreg rtc long 2 l register 0x0b00 00da r/w rtcl2hreg rtc long 2 h register 0x0b00 00dc r rtcl2cntlreg rtc long 2 count l register 0x0b00 00de r rtcl2cnthreg rtc long 2 count h register 0x0b00 01c0 r/w tclklreg tclk l register 0x0b00 01c2 r/w tclkhreg tclk h register 0x0b00 01c4 r tclkcntlreg tclk count l register 0x0b00 01c6 r tclkcnthreg tclk count h register 0x0b00 01de r/w rtcintreg rtc interrupt register each register is described in detail below. chapter 16 rtc (realtime clock unit) 337 16.2.1 elapsed time registers (1) etimelreg (0x0b00 00c0) bit d15 d14 d13 d12 d11 d10 d9 d8 name etime[15] etime[14] etime[13] etime[12] etime[11] etime[10] etime[9] etime[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name etime[7] etime[6] etime[5] etime[4] etime[3] etime[2] etime[1] etime[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] etime[15:0] elapsedtime bit [15:0] note continues counting (2) etimemreg (0x0b00 00c2) bit d15 d14 d13 d12 d11 d10 d9 d8 name etime[31] etime[30] etime[29] etime[28] etime[27] etime[26] etime[25] etime[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name etime[23] etime[22] etime[21] etime[20] etime[19] etime[18] etime[17] etime[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] etime[31:16] elapsedtime bit [31:16] note continues counting chapter 16 rtc (realtime clock unit) 338 (3) etimehreg (0x0b00 00c4) bit d15 d14 d13 d12 d11 d10 d9 d8 name etime[47] etime[46] etime[45] etime[44] etime[43] etime[42] etime[41] etime[40] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name etime[39] etime[38] etime[37] etime[36] etime[35] etime[34] etime[33] etime[32] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] etime[47:32] elapsedtime bit [47:32] note continues counting these registers indicate the elapsed timers value. they count up using a 32.768-khz cycle and when a match occurs with the elapsed compare registers, an alarm (elapsed time interrupt) occurs (and the count-up continues). a write operation is valid once values have been written to all registers (etimelreg, etimemreg, and etimehreg). chapter 16 rtc (realtime clock unit) 339 16.2.2 elapsed time compare registers (1) ecmplreg (0x0b00 00c8) bit d15 d14 d13 d12 d11 d10 d9 d8 name ecmp[15] ecmp[14] ecmp[13] ecmp[12] ecmp[11] ecmp[10] ecmp[9] ecmp[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name ecmp[7] ecmp[6] ecmp[5] ecmp[4] ecmp[3] ecmp[2] ecmp[1] ecmp[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] ecmp[15:0] value to be compared with elapsedtime bit [15:0] note previous value is retained (2) ecmpmreg (0x0b00 00ca) bit d15 d14 d13 d12 d11 d10 d9 d8 name ecmp[31] ecmp[30] ecmp[29] ecmp[28] ecmp[27] ecmp[26] ecmp[25] ecmp[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name ecmp[23] ecmp[22] ecmp[21] ecmp[20] ecmp[19] ecmp[18] ecmp[17] ecmp[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] ecmp[31:16] value to be compared with elapsedtime bit [31:16] note previous value is retained chapter 16 rtc (realtime clock unit) 340 (3) ecmphreg (0x0b00 00cc) bit d15 d14 d13 d12 d11 d10 d9 d8 name ecmp[47] ecmp[46] ecmp[45] ecmp[44] ecmp[43] ecmp[42] ecmp[41] ecmp[40] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name ecmp[39] ecmp[38] ecmp[37] ecmp[36] ecmp[35] ecmp[34] ecmp[33] ecmp[32] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] ecmp[47:32] value to be compared with elapsedtime bit [47:32] note previous value is retained use these registers to set the values to be compared with values in the elapsed time registers. chapter 16 rtc (realtime clock unit) 341 16.2.3 rtc long 1 registers (1) rtcl1lreg (0x0b00 00d0) bit d15 d14 d13 d12 d11 d10 d9 d8 name rtcl1p[15] rtcl1p[14] rtcl1p[13] rtcl1p[12] rtcl1p[11] rtcl1p[10] rtcl1p[9] rtcl1p[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name rtcl1p[7] rtcl1p[6] rtcl1p[5] rtcl1p[4] rtcl1p[3] rtcl1p[2] rtcl1p[1] rtcl1p[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] rtcl1p[15:0] [15:0] for rtclong1 counter cycle note previous value is retained chapter 16 rtc (realtime clock unit) 342 (2) rtcl1hreg (0x0b00 00d2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name rtcl1p[23] rtcl1p[22] rtcl1p[21] rtcl1p[20] rtcl1p[19] rtcl1p[18] rtcl1p[17] rtcl1p[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:8] reserved write 0 when writing. 0 is returned after a read. d[7:0] rtcl1p[23:16] [23:16] for rtclong1 counter cycle note previous value is retained use these registers to set the rtclong1 counter cycle. the rtclong1 counter begins its countdown at the value written to these registers. a write operation is valid once values have been written to both registers (rtcl1lreg and rtcl1hreg). cautions 1. the rtc unit is stopped when all zeros are written. 2. any combined setting of rtcl1hreg = 0x0000 and rtcl1lreg = 0x0001, 0x0002, 0x0003, 0x0004 is prohibited. chapter 16 rtc (realtime clock unit) 343 16.2.4 rtc long 1 count registers (1) rtcl1cntlreg (0x0b00 00d4) bit d15 d14 d13 d12 d11 d10 d9 d8 name rtcl1c[15] rtcl1c[14] rtcl1c[13] rtcl1c[12] rtcl1c[11] rtcl1c[10] rtcl1c[9] rtcl1c[8] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name rtcl1c[7] rtcl1c[6] rtcl1c[5] rtcl1c[4] rtcl1c[3] rtcl1c[2] rtcl1c[1] rtcl1c[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] rtcl1c[15:0] rtclong1 counter bit [15:0] note continues counting chapter 16 rtc (realtime clock unit) 344 (2) rtcl1cnthreg (0x0b00 00d6) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name rtcl1c[23] rtcl1c[22] rtcl1c[21] rtcl1c[20] rtcl1c[19] rtcl1c[18] rtcl1c[17] rtcl1c[16] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:8] reserved write 0 when writing. 0 is returned after a read. d[7:0] rtcl1c[23:16] rtclong1 counter bit [23:16] note continues counting these registers indicate the rtclong1 counters values. the countdown uses a 32.768-khz cycle and begins at the value set to the rtclong1 registers. an rtclong1 interrupt occurs when the counter reaches 0x00 0001 (at which point the counter returns to the start value and continues counting). chapter 16 rtc (realtime clock unit) 345 16.2.5 rtc long 2 registers (1) rtcl2lreg (0x0b00 00d8) bit d15 d14 d13 d12 d11 d10 d9 d8 name rtcl2p[15] rtcl2p[14] rtcl2p[13] rtcl2p[12] rtcl2p[11] rtcl2p[10] rtcl2p[9] rtcl2p[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name rtcl2p[7] rtcl2p[6] rtcl2p[5] rtcl2p[4] rtcl2p[3] rtcl2p[2] rtcl2p[1] rtcl2p[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] rtcl2p[15:0] [15:0] for rtclong2 counter cycle note previous value is retained chapter 16 rtc (realtime clock unit) 346 (2) rtcl2hreg (0x0b00 00da) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name rtcl2p[23] rtcl2p[22] rtcl2p[21] rtcl2p[20] rtcl2p[19] rtcl2p[18] rtcl2p[17] rtcl2p[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:8] reserved write 0 when writing. 0 is returned after a read. d[7:0] rtcl2p[23:16] [23:16] for rtclong2 counter cycle note previous value is retained use these registers to set the rtclong2 counter cycle. the rtclong2 counter begins its countdown at the value written to these registers. a write operation is valid once values have been written to both registers (rtcl2lreg and rtcl2hreg). cautions 1. the rtc unit is stopped when all zeros are written. 2. any combined setting of rtcl2hreg = 0x0000 and rtcl2lreg = 0x0001, 0x0002, 0x0003, 0x0004 is prohibited. chapter 16 rtc (realtime clock unit) 347 16.2.6 rtc long 2 count registers (1) rtcl2cntlreg (0x0b00 00dc) bit d15 d14 d13 d12 d11 d10 d9 d8 name rtcl2c[15] rtcl2c[14] rtcl2c[13] rtcl2c[12] rtcl2c[11] rtcl2c[10] rtcl2c[9] rtcl2c[8] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name rtcl2c[7] rtcl2c[6] rtcl2c[5] rtcl2c[4] rtcl2c[3] rtcl2c[2] rtcl2c[1] rtcl2c[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:0] rtcl2c[15:0] rtclong2 counter bit [15:0] note continues counting chapter 16 rtc (realtime clock unit) 348 (2) rtcl2cnthreg (0x0b00 00de) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bitd7d6d5d4d3d2d1d0 name rtcl2c[23] rtcl2c[22] rtcl2c[21] rtcl2c[20] rtcl2c[19] rtcl2c[18] rtcl2c[17] rtcl2c[16] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function d[15:8] reserved write 0 when writing. 0 is returned after a read. d[7:0] rtcl2c[23:16] rtclong2 counter bit [23:16] note continues counting these registers indicate the rtclong2 counters values. the countdown uses a 32.768-khz cycle and begins at the value set to the rtclong2 registers. an rtclong2 interrupt occurs when the counter reaches 0x00 0001 (at which point the counter returns to the start value and continues counting). chapter 16 rtc (realtime clock unit) 349 16.2.7 tclock counter registers (1) tclklreg (0x0b00 01c0) bit d15 d14 d13 d12 d11 d10 d9 d8 name tclkp[15] tclkp[14] tclkp[13] tclkp[12] tclkp[11] tclkp[10] tclkp[9] tclkp[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name tclkp[7] tclkp[6] tclkp[5] tclkp[4] tclkp[3] tclkp[2] tclkp[1] tclkp[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:0] tclkp[15:0] [15:0] for tclock counter cycle chapter 16 rtc (realtime clock unit) 350 (2) tclkhreg (0x0b00 01c2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved tclkp[24] r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name tclkp[23] tclkp[22] tclkp[21] tclkp[20] tclkp[19] tclkp[18] tclkp[17] tclkp[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:9] reserved write 0 when writing. 0 is returned after a read. d[8:0] tclkp[24:16] [24:16] for tclock counter cycle use these registers to set the tclk counter cycle. the tclk counter begins its countdown at the value written to these registers. a write operation is valid once values have been written to both registers (tclklreg and tclkhreg). caution the tclk unit is stopped when all zeros are written. chapter 16 rtc (realtime clock unit) 351 16.2.8 tclock counter count registers (1) tclkcntlreg (0x0b00 01c4) bit d15 d14 d13 d12 d11 d10 d9 d8 name tclkc[15] tclkc[14] tclkc[13] tclkc[12] tclkc[11] tclkc[10] tclkc[9] tclkc[8] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name tclkc[7] tclkc[6] tclkc[5] tclkc[4] tclkc[3] tclkc[2] tclkc[1] tclkc[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:0] tclkc[15:0] tclock counter [15:0] chapter 16 rtc (realtime clock unit) 352 (2) tclkcnthreg (0x0b00 01c6) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved tclkc[24] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name tclkc[23] tclkc[22] tclkc[21] tclkc[20] tclkc[19] tclkc[18] tclkc[17] tclkc[16] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:9] reserved write 0 when writing. 0 is returned after a read. d[8:0] tclkc[24:16] tclock counter [24:16] use these registers to set the tclk counter value. the tclkcnt counter begins its countdown at the value written to the tclk counter registers. a tclk counter interrupt occurs when the counter reaches 0x000 0001 (at which point the counter returns to the start value and continues counting). chapter 16 rtc (realtime clock unit) 353 16.2.9 rtc interrupt register (1) rtcintreg (0x0b00 01de) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved rtcintr3 rtcintr2 rtcintr1 rtcintr0 r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000 note note note bit name function d[15:4] reserved write 0 when writing. 0 is returned after a read. d[3] rtcintr3 tclock counter interrupt. cleared to 0 when 1 is written. 1 : occurred 0 : normal d[2] rtcintr2 rtclong2 interrupt. cleared to 0 when 1 is written. 1 : occurred 0 : normal d[1] rtcintr1 rtclong1 interrupt. cleared to 0 when 1 is written. 1 : occurred 0 : normal d[0] rtcintr0 status bit for elapsed time interrupt. cleared to 0 when 1 is written. 1 : occurred 0 : normal note previous value is retained this register is used to monitor interrupts. 354 [memo] 355 chapter 17 dsu (deadmans switch unit) this chapter describes the dsu (deadmans switch unit)s operations and register settings. 17.1 general the dsu detects when the v r 4102 is in runaway (endless loop) state and resets the v r 4102 to minimize runaway time. the use of the dsu to minimize runaway time effectively minimizes data loss that can occur due to software-related runaway states. 17.2 register set the dsu registers are listed below. table 17-1. dsu registers address r/w symbol function 0x0b00 00e0 r/w dsucntreg dsu control register 0x0b00 00e2 r/w dsusetreg dsu dead time set register 0x0b00 00e4 w dsuclrreg dsu clear register 0x0b00 00e6 r/w dsutimreg dsu elapsed time register each register is described in detail below. chapter 17 dsu (deadmans switch unit) 356 17.2.1 dsucntreg (0x0b00 00e0) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved dswen r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] dswen deadmans switch function enable 1 : enable 0 : prohibit this register is used to enable use of the deadmans switch functions. chapter 17 dsu (deadmans switch unit) 357 17.2.2 dsusetreg (0x0b00 00e2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved dedtime[3] dedtime[2] dedtime[1] dedtime[0] r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..4] reserved write 0 when writing. 0 is returned after a read. d[3..0] dedtime[3..0] deadmans switch cycle setting 1111 15 sec 1110 14 sec : 0010 2 sec 0001 1 sec 0000 rfu this register sets the cycle for deadmans switch functions. the deadmans switch cycle can be set in 1-second increments in a range from 1 to 15 seconds. however, the v r 4102s operation is undefined when 0x0 has been set to dedtime[3..0]. the dsuclrregs dswclr bit must be set by software within the specified cycle time. chapter 17 dsu (deadmans switch unit) 358 17.2.3 dsuclrreg (0x0b00 00e4) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved dswclr r/w rrrrrrrw rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] dswclr deadmans switch counter clear. cleared to 0 when 1 is written. 1 : clear 0 : dont clear this register clears the deadmans switch counter. the v r 4102 automatically shuts down if 1 is not written to this register within the period set in dsusetreg. chapter 17 dsu (deadmans switch unit) 359 17.2.4 dsutimreg (0x0b00 00e6) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved crttime[3] crttime[2] crttime[1] crttime[0] r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..4] reserved write 0 when writing. 0 is returned after a read. d[3..0] crttime[3..0] current deadmans switch timer value (elapsed time) 1111 15 sec 1110 14 sec : 0010 2 sec 0001 1 sec 0000 rfu this register indicates the elapsed time for the current deadmans switch timer. chapter 17 dsu (deadmans switch unit) 360 17.3 register setting flow the dsu register setting flow is described below. 1. set the dsus count-up value (from 1 to 15 seconds). the cpu will be reset if it does not clear (1 is not written to dsuclrreg) the timer within this time period. dsudtmreg address : 0x0b00 00e2 data : 0x000x 2. enable the dsu. dsucntreg address : 0x0b00 00e0 data : 0x0001 3. clear the timer within the time period mentioned in step 1 above. dsuclrreg address : 0x0b00 00e4 data : 0x0001 for normal use, repeat step 3. to obtain the current elapsed time: dsitimreg address : 0x0b00 00e6 read (4 bits) 4. disable the dsu for suspend mode or a shutdown. dsucntreg address : 0x0b00 00e0 data : 0x0000 361 chapter 18 giu (general purpose i/o unit) this chapter describes the gius operations and register settings. 18.1 general the giu controls gpio and dcd# pins. gpio pins are ports that support output functions and input functions (including three types of interrupt trigger detection functions). the interrupts occur in response to an input signal change (rising edge or falling edge of signal), low level, or high level. the clocks and input buffer types used for interrupt detection at a gpio pin are listed below. when not used for an interrupt, the registers corresponding to these pins can be written to output a low-level or high-level signal. each register can be read to check the state of the signal currently being input to the corresponding pin. table 18-1. gpio pin functions pin interrupt detection clock (internal) input buffer type output clock (internal) gpio[49..32] e e tclock gpio[31..16] tclock normal tclock gpio[15](dcd#) masterout normal e gpio[14..9] masterout normal masterout gpio[8..5] tclock normal masterout gpio[4] tclock schmitt tclock gpio[3..0] rtc schmitt rtc cautions the function of gpio[15] is fixed as dcd# input signal. this pin cannot be used as a general-purpose input/output pin. chapter 18 giu (general purpose i/o unit) 362 18.2 register set the giu registers are listed below. table 18-2. giu registers address r/w register symbols function 0x0b00 0100 r/w giuiosell gpio input/output select register l 0x0b00 0102 r/w giuioselh gpio input/output select register h 0x0b00 0104 r/w giupiodl gpio port input/output data register l 0x0b00 0106 r/w giupiodh gpio port input/output data register h 0x0b00 0108 r/w giuintstatl gpio interrupt status register l 0x0b00 010a r/w giuintstath gpio interrupt status register h 0x0b00 010c r/w giuintenl gpio interrupt enable register l 0x0b00 010e r/w giuintenh gpio interrupt enable register h 0x0b00 0110 r/w giuinttypl gpio interrupt type (edge or level) select register l 0x0b00 0112 r/w giuinttyph gpio interrupt type (edge or level) select register h 0x0b00 0114 r/w giuintalsell gpio interrupt active level select register l 0x0b00 0116 r/w giuintalselh gpio interrupt active level select register h 0x0b00 0118 r/w giuinthtsell gpio interrupt hold/through select register l 0x0b00 011a r/w giuinthtselh gpio interrupt hold/through select register h 0x0b00 011c r/w giupodatl gpio port output data register l 0x0b00 011e r/w giupodath gpio port output data register h chapter 18 giu (general purpose i/o unit) 363 18.2.1 giuiosell (0x0b00 0100) bit d15 d14 d13 d12 d11 d10 d9 d8 name ios[15] ios[14] ios[13] ios[12] ios[11] ios[10] ios[9] ios[8] r/w r r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name ios[7] ios[6] ios[5] ios[4] ios[3] ios[2] ios[1] ios[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] ios[15..0] gpio pin input/output select 1 : output 0 : input this register is used to set input/output values for gpio[15..0] pins. when the ios bit is set to 1, the corresponding gpio pin is set for output and the value that has been written to the corresponding piod bit in the giupiodl (gpio port input/output data register) is output. when this bit is set to 0, the corresponding gpio pin is set for input. caution since ios[15] (gpio[15] (dcd#)) is fixed as input, it cannot be set for output. chapter 18 giu (general purpose i/o unit) 364 18.2.2 giuioselh (0x0b00 0102) bit d15 d14 d13 d12 d11 d10 d9 d8 name ios[31] ios[30] ios[29] ios[28] ios[27] ios[26] ios[25] ios[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name ios[23] ios[22] ios[21] ios[20] ios[19] ios[18] ios[17] ios[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] ios[31..16] gpio pin input/output select 1 : output 0 : input this register is used to set input/output settings for gpio[31..16] pins. when the ios bit is set to 1, the corresponding gpio pin is set for output and the value that has been written to the corresponding piod bit in the giupiodh (gpio port input/output data register) is output. when this bit is set to 0, the corresponding gpio pin is set for input. chapter 18 giu (general purpose i/o unit) 365 18.2.3 giupiodl (0x0b00 0104) bit d15 d14 d13 d12 d11 d10 d9 d8 name piod[15] piod[14] piod[13] piod[12] piod[11] piod[10] piod[9] piod[8] r/w r r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name piod[7] piod[6] piod[5] piod[4] piod[3] piod[2] piod[1] piod[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] piod[15..0] gpio pin output data specification 1 : high 0 : low this register is used to read gpio pins and write data. the piod[15..0] bits correspond to the gpio[15..0] pins. when 1 is set to the corresponding ios bit in the giuiosell register (gpio input/output select register), the data written to the piod bit is output via the corresponding gpio pin. when the value of the corresponding ios bit in the giuiosell register (gpio input/output select register) is 0, writing a value to the piod bit does not affect the gpio pin (the write data is ignored). when the value of the ios bit in the giuiosell register (gpio input/output select register) is 0, reading the piod bit enables the corresponding gpio pins state to be read. caution since piod[15] (gpio[15] (dcd#)) is fixed as input, write data cannot be output via this pin. chapter 18 giu (general purpose i/o unit) 366 18.2.4 giupiodh (0x0b00 0106) bit d15 d14 d13 d12 d11 d10 d9 d8 name piod[31] piod[30] piod[29] piod[28] piod[27] piod[26] piod[25] piod[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name piod[23] piod[22] piod[21] piod[20] piod[19] piod[18] piod[17] piod[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] piod[31..16] gpio pin output data specification 1 : high 0 : low this register is used to read gpio pins and write data. the piod[31..16] bits correspond to the gpio[31..16] pins. when 1 is set to the corresponding ios bit in the giuioselh register (gpio input/output select register), the data written to the piod bit is output via the corresponding gpio pin. when the value of the corresponding ios bit in the giuioselh register (gpio input/output select register) is 0, writing a value to the piod bit does not affect the gpio pin (the write data is ignored). when the value of the ios bit in the giuioselh register (gpio input/output select register) is 0, reading the piod bit enables the corresponding gpio pins state to be read. chapter 18 giu (general purpose i/o unit) 367 18.2.5 giuintstatl (0x0b00 0108) bit d15 d14 d13 d12 d11 d10 d9 d8 name ints[15] ints[14] ints[13] ints[12] ints[11] ints[10] ints[9] ints[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name ints[7] ints[6] ints[5] ints[4] ints[3] ints[2] ints[1] ints[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] ints[15..0] interrupt to gpio pin. cleared to 0 when 1 is written. 1 : interrupt occurred 0 : no interrupt this register indicates the interrupt status of gpio pins. the ints[15..0] bits correspond to the gpio[15..0] pins. 1 is set to the corresponding ints bit when 1 is set to the corresponding inte bit in the giuintenl register (gpio interrupt enable register) and when the signal input to an interrupt-enabled gpio pin meets the conditions set via the giunttypl register (gpio interrupt type (edge or level) select register) and the giuintalsell register (gpio interrupt active level select register). caution the function of gpio[15] is fixed as dcd# signal input. chapter 18 giu (general purpose i/o unit) 368 18.2.6 giuintstath (0x0b00 010a) bit d15 d14 d13 d12 d11 d10 d9 d8 name ints[31] ints[30] ints[29] ints[28] ints[27] ints[26] ints[25] ints[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name ints[23] ints[22] ints[21] ints[20] ints[19] ints[18] ints[17] ints[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] ints[31..16] interrupt to gpio pin. cleared to 0 when 1 is written. 1 : interrupt occurred 0 : no interrupt this register indicates the interrupt status of gpio pins. the ints[31..16] bits correspond to the gpio[31..16] pins. 1 is set to the corresponding ints bit when 1 is set to the corresponding inte bit in the giuintenh register (gpio interrupt enable register) and when the signal input to an interrupt-enabled gpio pin meets the conditions set via the giuinttyph register (gpio interrupt type (edge or level) select register) and the giuintalselh register (gpio interrupt active level select register). chapter 18 giu (general purpose i/o unit) 369 18.2.7 giuintenl (0x0b00 010c) bit d15 d14 d13 d12 d11 d10 d9 d8 name inte[15] inte[14] inte[13] inte[12] inte[11] inte[10] inte[9] inte[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name inte[7] inte[6] inte[5] inte[4] inte[3] inte[2] inte[1] inte[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] inte[15..0] interrupt enable to gpio pin 1 : interrupt enable 0 : interrupt prohibit this register is used to set interrupt enable status for gpio pins. the inte[15..0] bits correspond to the gpio[15..0] pins. when 1 is set to the corresponding inte bit, interrupts are enabled for the corresponding gpio pins. caution the function of gpio[15] is fixed as dcd# signal input. chapter 18 giu (general purpose i/o unit) 370 18.2.8 giuintenh (0x0b00 010e) bit d15 d14 d13 d12 d11 d10 d9 d8 name inte[31] inte[30] inte[29] inte[28] inte[27] inte[26] inte[25] inte[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name inte[23] inte[22] inte[21] inte[20] inte[19] inte[18] inte[17] inte[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] inte[31..16] interrupt enable to gpio pin 1 : interrupt enable 0 : interrupt prohibit this register is used to set interrupt enable status for gpio pins. the inte[31..16] bits correspond to the gpio[31..16] pins. when 1 is set to the corresponding inte bit, interrupts are enabled for the corresponding gpio pins. chapter 18 giu (general purpose i/o unit) 371 18.2.9 giuinttypl (0x0b00 0110) bit d15 d14 d13 d12 d11 d10 d9 d8 name intt[15] intt[14] intt[13] intt[12] intt[11] intt[10] intt[9] intt[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name intt[7] intt[6] intt[5] intt[4] intt[3] intt[2] intt[1] intt[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] intt[15..0] interrupt detection method 1 : edge 0 : level this register is used to set the detection method (trigger) for interrupts to gpio pins. the intt[15..0] bits correspond to the gpio[15..0] pins. when 1 is set to the corresponding intt bit, the edge detection method is used for the interrupt signal at the corresponding gpio pin (an interrupt is triggered when the signal state changes from low to high or from high to low). the level detection method is used when 0 is set, in which case the level set to corresponding bit in the giuintalsell register (gpio interrupt active level select register) is detected. caution the function of gpio[15] is fixed as dcd# signal input. chapter 18 giu (general purpose i/o unit) 372 18.2.10 giuinttyph (0x0b00 0112) bit d15 d14 d13 d12 d11 d10 d9 d8 name intt[31] intt[30] intt[29] intt[28] intt[27] intt[26] intt[25] intt[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name intt[23] intt[22] intt[21] intt[20] intt[19] intt[18] intt[17] intt[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] intt[31..16] interrupt detection method 1 : edge 0 : level this register is used to set the detection method for interrupts to gpio pins. the intt[31..16] bits correspond to the gpio[31..16] pins. when 1 is set to the corresponding intt bit, the edge detection method is used for the interrupt signal at the corresponding gpio pin (an interrupt is triggered when the signal state changes from low to high or from high to low). the level detection method is used when 0 is set, in which case the level set to corresponding bit in the giuintalselh register (gpio interrupt active level select register) is detected. chapter 18 giu (general purpose i/o unit) 373 18.2.11 giuintalsell (0x0b00 0114) bit d15 d14 d13 d12 d11 d10 d9 d8 name intl[15] intl[14] intl[13] intl[12] intl[11] intl[10] intl[9] intl[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name intl[7] intl[6] intl[5] intl[4] intl[3] intl[2] intl[1] intl[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] intl[15..0] interrupt setting during level detection method 1 : high active 0 : low active this register is used to set the active level when using the level detection method for interrupts to gpio pins. the intl[15..0] bits correspond to the gpio[15..0] pins. when 1 is set to the corresponding intl bit, the high-active level detection method is used for interrupts at the corresponding gpio pin. the low-active level detection method is used when 0 is set to this bit. the contents of this register are not reflected when the edge detection method is selected via the giuinttypl register (gpio interrupt type (edge or level) select register). when using this register, be sure to set the level detection method via the giuinttypl register (gpio interrupt type (edge or level) select register). caution the function of gpio[15] is fixed as dcd# signal input. chapter 18 giu (general purpose i/o unit) 374 18.2.12 giuintalselh (0x0b00 0116) bit d15 d14 d13 d12 d11 d10 d9 d8 name intl[31] intl[30] intl[29] intl[28] intl[27] intl[26] intl[25] intl[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name intl[23] intl[22] intl[21] intl[20] intl[19] intl[18] intl[17] intl[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] intl[31..16] interrupt setting during level detection method 1 : high active 0 : low active this register is used to set the active level when using the level detection method for interrupts to gpio pins. the intl[31..16] bits correspond to the gpio[31..16] pins. when 1 is set to the corresponding intl bit, the high-active level detection method is used for interrupts at the corresponding gpio pin. the low-active level detection method is used when 0 is set to this bit. the contents of this register are not reflected when the edge detection method is selected via the giuinttyph register (gpio interrupt type (edge or level) select register). when using this register, be sure to set the level detection method via the giuinttyph register (gpio interrupt type (edge or level) select register). chapter 18 giu (general purpose i/o unit) 375 18.2.13 giuinthtsell (0x0b00 0118) bit d15 d14 d13 d12 d11 d10 d9 d8 name inth[15] inth[14] inth[13] inth[12] inth[11] inth[10] inth[9] inth[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name inth[7] inth[6] inth[5] inth[4] inth[3] inth[2] inth[1] inth[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] inth[15..0] gpio pin interrupt signal hold/through 1 : hold 0 : through this register is used to set whether or not interrupt signals to the gpio pins should be held. the inth[15..0] bits correspond to the gpio[15..0] pins. when 1 is set to the corresponding inth bit, any interrupt signal input to the corresponding gpio pin is held. when 0 is set to this bit, any interrupt signal input to the corresponding gpio pin is not held and is instead allowed to pass through. any held interrupt signal is cleared when 1 is set to the corresponding bit in the giuintstatl register (gpio interrupt status register). inth[15..0] are not affected by giuintenl (interrupt enable register). if 1 (hold) is set to the inth bit while the interrupt enable bit is set to prohibit interrupts, any change in the pin state is retained as change data. therefore, an interrupt still occurs when the interrupt enable bit is again set to enable interrupts. caution the function of gpio[15] is fixed as dcd# signal input. chapter 18 giu (general purpose i/o unit) 376 18.2.14 giuinthtselh (0x0b00 011a) bit d15 d14 d13 d12 d11 d10 d9 d8 name inth[31] inth[30] inth[29] inth[28] inth[27] inth[26] inth[25] inth[24] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name inth[23] inth[22] inth[21] inth[20] inth[19] inth[18] inth[17] inth[16] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] inth[31..16] gpio pin interrupt signal hold/through 1 : hold 0 : through this register is used to set whether or not interrupt signals to the gpio pins should be held. the inth[31..16] bits correspond to the gpio[31..16] pins. when 1 is set to the corresponding inth bit, any interrupt signal input to the corresponding gpio pin is held. when 0 is set to this bit, any interrupt signal input to the corresponding gpio pin is not held and is instead allowed to pass through. any held interrupt signal is cleared when 1 is set to the corresponding bit in the giuintstath register (gpio interrupt status register). inth[31..16] are not affected by giuintenh (interrupt enable register). if 1 (hold) is set to the inth bit while the interrupt enable bit is set to prohibit interrupts, any change in the pin state is retained as change data. therefore, an interrupt still occurs when the interrupt enable bit is again set to enable interrupts. chapter 18 giu (general purpose i/o unit) 377 the relationship between settings of gpio interrupts enable/prohibit and hold/through is as below. interrupt trigger setting of giuinthsel setting of giuinten hold in giu notation to icu masked held not noticed not masked held noticed hold masked o canceled held noticed masked through not noticed not masked through noticed level through masked o canceled through not noticed masked held not noticed not masked held noticed hold masked o canceled held noticed masked through not noticed not masked prohibited prohibited edge through masked o canceled through not noticed chapter 18 giu (general purpose i/o unit) 378 18.2.15 giupodatl (0x0b00 011c) bit d15 d14 d13 d12 d11 d10 d9 d8 name piod[47] piod[46] piod[45] piod[44] piod[43] piod[42] piod[41] piod[40] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bitd7d6d5d4d3d2d1d0 name piod[39] piod[38] piod[37] piod[36] piod[35] piod[34] piod[33] piod[32] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15..0] piod[47..32] gpio pin output data specification 1 : high 0 : low this register is used to set the output level for gpio pins. the piod[47..32] bits correspond to the gpio[47..32] pins. the data written to the piod bit is output via the corresponding gpio pin. the set value can be read by reading the piod bit. pins set by this register are output-only. pins set by this register are used exclusively from other function pins. therefore, when using this register, set the enable bit to prohibit in the corresponding unit. the correspondences between piod bits and function pins are listed in the table on the next page. chapter 18 giu (general purpose i/o unit) 379 table 18-3. table of correspondences between gpio[47..32] and function pins piod bit gpio pin function pin piod[47] gpio[47] dcts# piod[46] gpio[46] drts# piod[45] gpio[45] ddin piod[44] gpio[44] ddout piod[43] gpio[43] kscan[11] piod[42] gpio[42] kscan[10] piod[41] gpio[41] kscan[9] piod[40] gpio[40] kscan[8] piod[39] gpio[39] kscan[7] piod[38] gpio[38] kscan[6] piod[37] gpio[37] kscan[5] piod[36] gpio[36] kscan[4] piod[35] gpio[35] kscan[3] piod[34] gpio[34] kscan[2] piod[33] gpio[33] kscan[1] piod[32] gpio[32] kscan[0] chapter 18 giu (general purpose i/o unit) 380 18.2.16 giupodath (0x0b00 011e) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved pioen[1] pioen[0] r/w rrrrrrr/wr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved piod[49] piod[48] r/w rrrrrrr/wr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..0] reserved reserved d[9] pioen[1] gpio[49] pin output control 1 : enable 0 : disable d[8] pioen[0] gpio[48]/dbus32 pin output control 1 : enable 0 : disable d[7..2] reserved reserved d[1..0] piod[49..48] gpio pin output data specification 1 : high 0 : low this register is used to set the output level for gpio pins. the pioen[1..0] bits or the piod[49..48] bits correspond to the gpio[49..48]. the data written to the piod bit is output via the corresponding gpio pin. the set value can be read by reading the piod bit. pins set by this register are output-only. pins set by this register are used exclusively from other function pins. therefore, when using this register, set the enable bit to prohibit in the corresponding unit. the correspondence between piod bit and function pin is listed below. table 18-4. table of correspondence between gpio[48] and function pin piod bit gpio pin function pin piod[48] gpio[48] dbus32 381 chapter 19 piu (touch panel interface unit) this chapter describes the pius operations and register settings. 19.1 general the piu uses an on-chip a/d converter and detects the x and y coordinates of pen contact locations on the touch panel and scans the general-purpose a/d input port. since the touch panel control circuit and the a/d converter (conversion precision: 10 bits) are both on-chip, the touch panel is connected directly to the v r 4102. the pius function, namely the detection of x and y coordinates, is performed partly by hardware and partly by software. hardware tasks : ? touch panel applied voltage control ? reception of coordinate data software task : ? processing of coordinate data based on data sampled by hardware features of the pius hardware tasks are described below. ? can be directly connected to touch panel with four-pin resistance layers (on-chip touch panel driver) ? interface for on-chip a/d converter ? voltage detection at three general-purpose ad ports and one audio input port ? operation of a/d converter based on various settings and control of voltage applied to touch panel ? sampling of x-coordinate and y-coordinate data ? variable coordinate data sampling interval ? interrupt is triggered if pen touch occurs regardless of cpu operation mode (interrupts do not occur when in cpu hibernate mode) ? four dedicated buffers for up to two pages each of coordinate data ? four buffers for a/d port scan ? auto/manual options for coordinate data sampling start/stop control chapter 19 piu (touch panel interface unit) 382 19.1.1 block diagrams figure 19-1. piu peripheral block diagram tpy1 tpy0 tpx1 tpx0 audioin adin2 adin1 adin0 selector 4 4 adc aiu piu v r 4102 i/o buffer 1 battery, etc. touch panel i/o buffer ? touch panel a set of four pins are located at the edges of the x-axis and y-axis resistance layers, and the two layers have high resistance when there is no pen contact and low resistance when there is pen contact. the resistance between the two edges of the resistance layers is about 1 k : . when a voltage is applied to both edges of the y-axis resistance layer, the voltage (v y1 and v y2 in the figure below) is measures at the x-axis resistance layers pins to determine the y coordinate. similarly, when a voltage is applied to both edges of the x-axis resistance layer, the voltage (v x1 and v x2 in the figure below) is measures at the y-axis resistance layers pins to determine the x coordinate. for greater precision, voltage applied to individual resistance-layer pins can be measured to obtain x and y coordinate data based on four voltage measurements. the obtained coordinate data are stored to piupbnmreg register (n = 0, 1, m = 0 to 3). figure 19-2. equivalent circuit of coordinate detection (a) y-coordinate detection tpy1: 3v tpy1: 0v tpy0: 0v tpy0: 3v tpx0 tpx0 tpy0 (b) x-coordinate detection tpy0 tpx0: 3v tpx1: 0v tpx0: 0v tpx1: 3v v y2 v y1 v x1 v x2 chapter 19 piu (touch panel interface unit) 383 figure 19-3. internal block diagram of piu general purpose a/d ports and audio input port touch panel inside the v r 4102 internal bus piu internal bus controller piu registers scan sequencer tp interface controller a/d converter the piu includes three blocks: an internal bus controller, a scan sequencer, and a tp interface controller. ? internal bus controller the internal bus controller controls the internal bus, dma, the piu registers, and interrupts and performs serial/parallel conversion of data from the a/d converter. ? scan sequencer the scan sequencer is used for piu state management. ? tp interface controller the tp interface controller is used to control the touch panel. chapter 19 piu (touch panel interface unit) 384 19.2 scan sequencer state transition figure 19-4. scan sequencer state transition diagram waitpentouch datascan interval adportscan cmdscan standb y disable piuseqen=1 & adpsstart=1 piuseqen= 1 timeout release & autostop=1 touch auto adpsstart= piuseqen=1 & piumode=01 piuseqen=0 release piuseqen=0 piuseqen=0 piupwr=0 piupwr=1 reset=1 piuseqen=1 & scanstart=1 scanstart=1 piuseqen=0 or scanstop=1 ? disable state in this state, the a/d converter is in standby mode, the output pins are in touch detection mode (no piu interrupt), and the input pins are in mask mode (to prevent misoperation when an undefined input is applied). ? standby state in this state, the unit is in scan idle mode. the touch panel is in low-power mode (0-v voltage is applied to the touch panel and the a/d converter is in disable mode). normally, this is the state from which various mode settings are made. caution state transitions occur when the piuseqen bit is active, so the piuseqen bit must be set as active after each mode setting has been completed. ? adportscan state this is the state in which voltage is measured at the three a/d converters general-purpose ports and one audio input port. after the a/d converter is activated and voltage data is obtained, the data is stored in the pius internal data buffer (piuabxreg). after the four ports are scanned, a padcmdintr interrupt occurs. after this interrupt occurs, the adpsstart bit is automatically set as inactive and the state changes to the state in which the adpsstart bit was active. chapter 19 piu (touch panel interface unit) 385 ? cmdscan state when in this state, the a/d converter operates using various settings. voltage data from one port only is fetched based on a combination of the touch panel pin setting (tpx[1:0], tpy[1:0]) and the selection of an input port (tpx[1:0], tpy[1:0], audioin, adin[2:0]) to the a/d converter. use piucmdreg to make the touch panel pin setting and to select the input port. ? waitpentouch state this is the standby state that waits for a touch panel touch state. when the piu detects a touch panel touch state, penchgintr (an internal interrupt in the piu) occurs. at this point, if the padautoscan bit is active, the state changes to the pendatascan state. during the waitpentouch state, it is possible to change to suspend mode because the panel state can be detected even when tclock has been stopped. ? pendatascan state this is the state in which touch panel coordinates are detected. the a/d converter is activated and the four sets of data for each coordinate are sampled. caution if one complete pair of coordinates is not obtained during the interval between one pair of coordinates and the next coordinate data, a paddatalostintr interrupt occurs. ? intervalnextscan state this is the standby state that waits for the next coordinate sampling period or a touch panel release state. after the touch panel state is detected, the time period specified via piusivlreg elapses before the transition to the pendatascan state. if the piu detects a release state within the specified time period, penchgintr (an internal interrupt in the piu) occurs. at this point, the state changes to the waitpentouch state if the padatstop bit is active. if the padatstop bit is inactive, it changes to the pendatascan state after the specified time period has elapsed. chapter 19 piu (touch panel interface unit) 386 19.3 register set the piu registers are listed below. table 19-1. piu registers address r/w register symbols function 0x0b00 0122 r/w piucntreg piu control register 0x0b00 0124 r/w piuintreg piu interrupt cause register 0x0b00 0126 r/w piusivlreg piu data sampling interval register 0x0b00 0128 r/w piustblreg piu a/d converter start delay register 0x0b00 012a r/w piucmdreg piu a/d command register 0x0b00 0130 r/w piuascnreg piu a/d port scan register 0x0b00 0132 r/w piuamskreg piu a/d scan mask register 0x0b00 013e r piucivlreg piu check interval register 0x0b00 02a0 r/w piupb00reg piu page 0 buffer 0 register 0x0b00 02a2 r/w piupb01reg piu page 0 buffer 1 register 0x0b00 02a4 r/w piupb02reg piu page 0 buffer 2 register 0x0b00 02a6 r/w piupb03reg piu page 0 buffer 3 register 0x0b00 02a8 r/w piupb10reg piu page 1 buffer 0 register 0x0b00 02aa r/w piupb11reg piu page 1 buffer 1 register 0x0b00 02ac r/w piupb12reg piu page 1 buffer 2 register 0x0b00 02ae r/w piupb13reg piu page 1 buffer 3 register 0x0b00 02b0 r/w piuab0reg piu a/d scan buffer 0 register 0x0b00 02b2 r/w piuab1reg piu a/d scan buffer 1 register 0x0b00 02b4 r/w piuab2reg piu a/d scan buffer 2 register 0x0b00 02b6 r/w piuab3reg piu a/d scan buffer 3 register 0x0b00 02bc r/w piupb04reg piu page 0 buffer 4 register 0x0b00 02be r/w piupb14reg piu page 1 buffer 4 register these registers are described in detail below. chapter 19 piu (touch panel interface unit) 387 19.3.1 piucntreg (0x0b00 0122) (1/2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved penstp penstc padstate[2] padstate[1] padstate[0] padatstop padatstart r/w r r/w r r r r r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name padscan stop padscan start padscan type piumode[1] piumode[0] piuseqen piupwr padrst r/w r/w r/w r/w r/w r/w r/w r/w w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15] reserved write 0 when writing. 0 is returned after a read. d[14] penstp previous touch panel contact state 1 : touch 0 : release d[13] penstc current touch panel contact state 1 : touch 0 : release d[12..10] padstate[2:0] scan sequencer status 111 : cmdscan 110 : intervalnextscan 101 : pendatascan 100 : waitpentouch 011 : rfu 010 : adportscan 001 : standby 000 : disable d[9] padatstop sequencer auto stop setting during touch panel release state 1 : auto stop after sampling data for one set of coordinates during release state 0 : no auto stop (even during release state) d[8] padatstart sequencer auto start setting during touch panel touch state 1 : auto start during touch state 0 : no auto start during touch state d[7] padscanstop forced stop setting for touch panel sequencer 1 : forced stop after sampling data for one set of coordinates 0 : do not stop chapter 19 piu (touch panel interface unit) 388 (2/2) bit name function d[6] padscanstart start setting for touch panel sequencer 1 : forced start 0 : do not start d[5] padscantype touch pressure sampling enable 1: enable 0: prohibit d[4..3] piumode[1..0] piu mode setting 11 : rfu 10 : rfu 01 : operate a/d converter using any command 00 : sample coordinate data d[2] piuseqen scan sequencer operation enable 1 : enable 0 : prohibit d[1] piupwr piu power mode setting 1 : set piu output as active and change to standby mode 0 : set panel to touch detection state and set piu operation stop enabled mode d[0] padrst piu reset. once the padrst bit is set to 1, it is automatically cleared to 0 after four tclock cycles. 1 : reset 0 : normal this register is used to make various settings for the piu. some bits in this register cannot be set in a specific state of scan sequencer. the combination of the setting of this register and the sequencer state is as follows. chapter 19 piu (touch panel interface unit) 389 table 19-2. piucntreg bit manipulation and states piucntreg bit manipulation scan sequencers state disable standby waitpentouch pendata scan padrst note 1 0 o 1 e disable disable disable piupwr 0 o 1 standby ? uu 1 o 0 ? disable uu piuseqen 0 o 1 u waitpentouch ? ? 1 o 0 ? ? standby standby padatstart 0 o 1 ue pendatascan note 2 u 1 o 0 ueeu padatstop 0 o 1 ueuu 1 o 0 ueuu padscanstart 0 o 1 u pendatascan note 3 uu 1 o 0 ueuu padscanstop 0 o 1 ueu standby note 4 1 o 0 ueue piucntreg bit manipulation scan sequencers state intervalnextscan adportscan cmdscan padrst note 1 0 o 1 disable disable disable piupwr 0 o 1? ? ? 1 o 0 uuu piuseqen 0 o 1? ? ? 1 o 0 standby standby standby padatstart 0 o 1 uuu 1 o 0 uuu padatstop 0 o 1 uuu 1 o 0 uuu padscanstart 0 o 1 uuu 1 o 0 uuu padscanstop 0 o 1 standby standby note 4 standby note 4 1 o 0? ee notes 1. after 1 is written, the bit is automatically cleared to 0 after four tclock cycles. 2. state transition occurs during touch state 3. state transition occurs when piuseqen = 1 4. state transition occurs after one set of data is sampled. this bit is cleared to 0 after the state transition occurs. remarks e : the bit change is retained but there is no state transition. u : setting prohibited (operation not guaranteed) ? : combination of state and bit status before setting does not exist chapter 19 piu (touch panel interface unit) 390 19.3.2 piuintreg (0x0b00 0124) bit d15 d14 d13 d12 d11 d10 d9 d8 name ovp reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved padcmd intr padadp intr padpage1 intr padpage0 intr paddlost intr reserved penchg intr r/w r r/w r/w r/w r/w r/w r r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15] ovp valid page id bit (older valid page) 1 : valid data older than page 1 buffer data is retained 0 : valid data older than page 0 buffer data is retained d[14..7] reserved write 0 when writing. 0 is returned after a read. d[6] padcmdintr piu command scan interrupt. cleared to 0 when 1 is written. 1 : indicates that command scan found valid data 0 : indicates that command scan did not find valid data in buffer d[5] padadpintr piu a/d port scan interrupt . cleared to 0 when 1 is written. 1 : indicates that a/d port scan found valid data with 1 value in buffer 0 : indicates that a/d port scan did not find valid data with 1 value in buffer d[4] padpage1intr piu data buffer page 1 interrupt. cleared to 0 when 1 is written. 1 : valid data with 1 value is stored in page 1 of data buffer 0 : no valid data with 1 value in page 1 of data buffer d[3] padpage0intr piu data buffer page 0 interrupt. cleared to 0 when 1 is written. 1 : valid data with 1 value is stored in page 0 of data buffer 0 : no valid data with 1 value in page 0 of data buffer d[2] paddlostintr a/d data timeout. cleared to 0 when 1 is written. 1 : not data with 1 value found within specified time 0 : no timeout d[1] reserved write 0 when writing. 0 is returned after a read. d[0] penchgintr change in touch panel contact state. cleared to 0 when 1 is written. 1 : change has occurred 0 : no change this register is used to set or indicate an occurrence of pius various interrupt requests. chapter 19 piu (touch panel interface unit) 391 19.3.3 piusivlreg (0x0b00 0126) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved scanint val[10] scanint val[9] scanint val[8] r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name scanint val[7] scanint val[6] scanint val[5] scanint val[4] scanint val[3] scanint val[2] scanint val[1] scanint val[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 1 1 1 other resets 0 0 0 0 0 1 1 1 bit name function d[15..11] reserved write 0 when writing. 0 is returned after a read. d[10..0] scanintval[10..0] coordinate data scan sampling interval setting interval = scanintval[10..0] x 30 p s this register sets the sampling interval for coordinate data sampling. the sampling interval for one pair of coordinate data is the value set via scanintval[10..0] multiplied by 30 p s. accordingly, the logical range of sampling intervals that can be set in 30- p s units is from 0 p s to 60,810 p s (about 60 ms). actually, if the sampling interval setting is shorter than the time required for obtaining a pair of coordinate data or adportscan data, a piulostintr interrupt will occur. if piulostintr interrupts occur frequently, set a longer interval time. figure 19-5. interval times and states remarks s : voltage stabilization standby time (stable(5:0) in piustblreg) a : a/d converters conversion time (about 10 p s) t : touch/release detection datascan interval interval adportscan datascan state s a s a s a s a a a a a s a s a s a s a s t t interval time operation chapter 19 piu (touch panel interface unit) 392 19.3.4 piustblreg (0x0b00 0128) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved stable[5] stable[4] stable[3] stable[2] stable[1] stable[0] r/w r r r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 1 1 1 other resets 0 0 0 0 0 1 1 1 bit name function d[15..6] reserved write 0 when writing. 0 is returned after a read. d[5..0] stable[5..0] panel applied voltage stabilization standby time standby time = stable[5..0] u 30 p s during a/d scan, this can be used as a timeout counter. the voltage stabilization standby time for the voltage applied to the touch panel can be set via stable[5..0] in 30- p s units between 0 p s and 1,890 p s. the setting of this register is also used as a timeout period during a/d scan. chapter 19 piu (touch panel interface unit) 393 19.3.5 piucmdreg (0x0b00 012a) (1/2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved stableon tpyen1 tpyen0 tpxen1 tpxen0 r/w r r r r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name tpyd1 tpyd0 tpxd1 tpxd0 adcmd[3] adcmd[2] adcmd[1] adcmd[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 1 1 1 1 other resets 0 0 0 0 1 1 1 1 bit name function d[15..13] reserved write 0 when writing. 0 is returned after a read. d[12] stableon touch panel applied voltage stabilization time set (stable[5..0] of piustblreg) enable 1 : retain panel voltage stabilization time 0 : ignore panel voltage stabilization time (voltage stabilization standby time = 0) d[11..10] tpyen[1..0] tpy port input/output switching during command scan 00 : tpy1 input, tpy0 input 01 : tpy1 input, tpy0 output 10 : tpy1 output, tpy0 input 11 : tpy1 output, tpy0 output d[9..8] tpxen[1..0] tpx port input/output switching during command scan 00 : tpx1 input, tpx0 input 01 : tpx1 input, tpx0 output 10 : tpx1 output, tpx0 input 11 : tpx1 output, tpx0 output d[7..6] tpyd[1..0] tpy output level during command scan 00 : tpy1 = l, tpy0 = l 01 : tpy1 = l, tpy0 = h 10 : tpy1 = h, tpy0 = l 11 : tpy1 = h, tpy0 = h tpyd value is ignored when tpyen is set for input. d[5..4] tpxd[1..0] tpx output level during command scan 00 : tpx1 = l, tpx0 = l 01 : tpx1 = l, tpx0 = h 10 : tpx1 = h, tpx0 = l 11 : tpx1 = h, tpx0 = h tpxd value is ignored when tpxen is set for input. chapter 19 piu (touch panel interface unit) 394 (2/2) bit name function d[3..0] adcmd[3..0] a/d converter input port selection for command scan 1111 : a/d converter standby mode request 1110 : rfu : 1000 : rfu 0111 : audioin port 0110 : adin2 port 0101 : adin1 port 0100 : adin0 port 0011 : tpy1 port 0010 : tpy0 port 0001 : tpx1 port 0000 : tpx0 port this register sets the switching or output level of ports during command scan operation. chapter 19 piu (touch panel interface unit) 395 19.3.6 piuascnreg (0x0b00 0130) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved tppscan adps start r/w rrrrrrr/wr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..2] reserved write 0 when writing. 0 is returned after a read. d[1] tppscan port selection for adportscan 1 : select tpx[1:0], tpy[1:0] (for touch panel) as a/d port 0 : select adin[3:0] (general-purpose) as a/d port d[0] adpsstart adporscan start 1 : start adportscan 0 : do not perform adportscan the adportscan begins when the adpsstart bit is set. after the adportscan is completed, the state returns to the state when adportscan was started. automatically adpsstart bit is reset (to 0) after adportscan is completed. if the adportscan is not completed within the time period set via piustblregs stable bits, a piulostintr interrupt occurs as a timeout interrupt. some bits in this register cannot be set in a specific state of scan sequencer. the combination of the setting of this register and the sequencer state is as follows. chapter 19 piu (touch panel interface unit) 396 table 19-3. piuascnreg bit manipulation and states piuascnreg bit manipulation scan sequencers state disable standby waitpentouch pendata scan addstart 0 o 1 u adportscan note uu 1 o 0 u disable uu tppscan 0 o 1 eeee 1 o 0 eeee piucntreg bit manipulation scan sequencers state intervalnextscan adportscan cmdscan addstart 0 o 1 u adportscan note u 1 o 0 u disable u tppscan 0 o 1 u waitpentouch ? 1 o 0 ? ? standby note after adportscan is completed, the bit is automatically cleared to 0. remarks e : the bit change is retained but there is no state transition. u : setting prohibited (operation not guaranteed) ? : combination of state and bit status before setting does not exist chapter 19 piu (touch panel interface unit) 397 19.3.7 piuamskreg (0x0b00 0132) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name adinm3 adinm2 adinm1 adinm0 tpym1 tpym0 tpxm1 tpxm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..8] reserved write 0 when writing. 0 is returned after a read. d[7] adinm[3] audio input port mask valid only during a/d scan. if masked, a/d conversions are not performed for the corresponding port. d[6..4] adinm[2..0] general-purpose a/d port mask valid only during a/d scan. if masked, a/d conversions are not performed for the corresponding port. 1 : mask 0 : normal d[3..2] tpym[1..0] touch panel a/d port tpy mask valid only during a/d scan. if masked, a/d conversions are not performed for the corresponding port. 1 : mask 0 : normal d[1..0] tpxm[1..0] touch panel a/d port tpx mask valid only during a/d scan. if masked, a/d conversions are not performed for the corresponding port. 1 : mask 0 : normal this register is used to set masking of each a/d port. its setting is valid only during a/d port scanning operation. chapter 19 piu (touch panel interface unit) 398 19.3.8 piucivlreg (0x0b00 013e) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved checkin tval[10] checkin tval[9] checkin tval[8] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name checkin tval[7] checkin tval[6] checkin tval[5] checkin tval[4] checkin tval[3] checkin tval[2] checkin tval[1] checkin tval[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..11] reserved write 0 when writing. 0 is returned after a read. d[10..0] chkintval[10..0] interval count value this register is used for real-time reading of internal register values being counted down based on the piusivlreg setting. chapter 19 piu (touch panel interface unit) 399 19.3.9 piupbnmreg (0x0b00 02a0 to 0x0b00 02ae, 0x0b00 02bc to 0x0b00 02be) remark n = 0, 1, m = 0 to 4 piupb00reg (0x0b00 02a0) piupb04reg (0x0b00 02bc) piupb13reg (0x0b00 02ae) piupb01reg (0x0b00 02a2) piupb10reg (0x0b00 02a8) piupb14reg (0x0b00 02be) piupb02reg (0x0b00 02a4) piupb11reg (0x0b00 02aa) piupb03reg (0x0b00 02a6) piupb12reg (0x0b00 02ac) bit d15 d14 d13 d12 d11 d10 d9 d8 name valid reserved reserved reserved reserved reserved paddata[9] paddata[8] r/w r/wrrrrrr/wr/w rtcrst 0 0 0 0 0 0 0 0 other resets000000 0 0 bitd7d6d5d4d3d2d1d0 name paddata[7] paddata[6] paddata[5] paddata[4] paddata[3] paddata[2] paddata[1] paddata[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function d[15] valid indicates validity of data in paddata 1 : valid 0 : invalid d[14..10] reserved write 0 when writing. 0 is returned after a read. d[9..0] paddata[9..0] a/d converters sampling data this register is used to store coordinate data and touch pressure data. there are four coordinate data buffers and one pair of touch pressure data buffer, each of which holds two pages of coordinate data or pressure data, and the addresses (register addresses) where the coordinate data or the pressure data is stored are fixed. read coordinate data from the corresponding register in a valid page. the valid bit, which indicates when the data is valid, is automatically rendered invalid when the page buffer interrupt cause (piupage0intr or piupage1intr in piuintreg) is cleared. table 19-4. detected coordinates and page buffers detected data page0 buffer page1 buffer x+ piupb00reg piupb10reg x e piupb01reg piupb11reg y+ piupb02reg piupb12reg y e piupb03reg piupb13reg z (touch pressure) piupb04reg piupb14reg chapter 19 piu (touch panel interface unit) 400 19.3.10 piuabnreg (0x0b00 02b0 to 0x0b00 02b6) remark n = 0 to 3 piuab0reg (0x0b00 02b0) piuab1reg (0x0b00 02b2) piuab2reg (0x0b00 02b4) piuab3reg (0x0b00 02b6) bit d15 d14 d13 d12 d11 d10 d9 d8 name valid reserved reserved reserved reserved reserved paddata[9] paddata[8] r/w r/wrrrrrr/wr/w rtcrst 0 0 0 0 0 0 0 0 other resets000000 0 0 bitd7d6d5d4d3d2d1d0 name paddata[7] paddata[6] paddata[5] paddata[4] paddata[3] paddata[2] paddata[1] paddata[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function d[15] valid indicates validity of data in paddata 1 : valid 0 : invalid d[14..10] reserved write 0 when writing. 0 is returned after a read. d[9..0] paddata[9..0] a/d converters sampling data this register is used to store general-purpose a/d port sampling data, audio input port sampling data, and command scan data. there are four data buffers and the addresses (register address) where the data is stored are fixed. the valid bit, which indicates when the data is valid, is automatically rendered invalid when the page buffer interrupt cause (piuadpintr in piuintreg) is cleared. table 19-5. a/d ports and data buffers register during adportscan during cmdscan tppscan = 0 tppscan = 1 piuab0reg piuab1reg piuab2reg piuab3reg adin0 adin1 adin2 audioin tpx0 tpx1 tpy0 tpy1 cmdscandata e e e chapter 19 piu (touch panel interface unit) 401 19.4 register setting flow be sure to reset the piu before operating the scan sequencer. setting initial values via a reset sets particular values for the sequence interval, etc., that are required. the registers for which these initial settings are necessary are listed below. piusitvlreg scanintval [10:0] piustblreg stable [3:0] interrupt mask cancellation settings are required for registers other than the piu registers. setting unit register bit value icu msysintreg piuintr 1 interrupt mask clear icu mpiuintreg bit 6:0 0x7f clock mask clear cmu cmuclkmsk mskpiu 1 (1) register setting flow for voltage detection at a/d general-purpose ports and audio input port standby, waitpentouch, or interval state <1> piuamskreg ad port and audio input port mask setting <2> piuascnreg adpsstart = 1 p adportscan state <3> piuascnreg adpsstart = 0 p standby, waitpentouch, or interval state (2) register setting flow for auto scan coordinate detection standby state <1> piucntreg piumode [1:0] = 00 padatscan = 1 padatstop = 1 <2> piucntreg piuseqen = 1 p waitpentouch state chapter 19 piu (touch panel interface unit) 402 (3) register setting flow for manual scan coordinate detection disable state <1> piucntreg piupwr = 1 p standby state <2> piucntreg piumode[1:0] = 00 padscanstart = 1 <3> piucntreg piuseqen = 1 p pendatascan state (4) register setting flow during suspend mode transition standby, waitpentouch, or interval state <1> piucntreg piuseqen = 0 p standby state <2> piucntreg piupwr = 1 p disable state (5) register setting flow when returning from suspend mode transition disable state <1> piucntreg piupwr = 1 p standby state <2> piucntreg piumode [1:0] = 00 padatscan = 1 padatstop = 1 <3> piucntreg piuseqen = 1 p waitpentouch state touch detected p pendatascan state (6) register setting flow for command scan disable state <1> piucntreg piupower = 1 p standby state <2> piucntreg piumode [1:0] = 01 <3> piucntreg set touch panel pins, select input port <4> piucntreg piuseqen = 1 p cmdscan state chapter 19 piu (touch panel interface unit) 403 19.5 relationships among tpx, tpy, and adin pins and states state padstate[2:0] tpx[1:0] tpy[1:0] adin[2:0] audioin power off (pen status detection) disable hh d ee e e e low-power standby standby 00 00 e e e e pen status detection waitpentouch/interval hh d ee e e e voltage detection at general-purpose ad0 port adportscan 00 00 e e e i voltage detection at general-purpose ad1 port adportscan 00 00 e e i e voltage detection at general-purpose ad2 port adportscan 00 00 e i e e voltage detection at audio input port adportscan 00 00 i e e e tpy1 = h, tpy0 = l, tpx0 = samp (x+) paddatascan e ihl e e e e tpy1 = l, tpy0 = h, tpx0 = samp (x e ) paddatascan e ilh e e e e tpx1 = h, tpx0 = l, tpy0 = samp (y+) paddatascan hl e i e e e e tpx1 = l, tpx0 = h, tpy0 = samp (y e ) paddatascan lh e i e e e e touch pressure detection (z) paddatascan hh d ee e e e remarks 0 : low level input 1 : high level input l : low level output h : high level output l : a/d converter input d : touch interrupt input (via pull-down resistor) d : no touch interrupt input (via pull-down resistor) e : dont care chapter 19 piu (touch panel interface unit) 404 19.6 timing 19.6.1 touch/release detection timing touch/release detection does not use the a/d converter but instead uses the voltage level of the tpy1 pin to determine the panels touch/release state. the following figure shows a touch/release detection timing diagram. figure 19-6. touch/release detection timing state tpy,tpx (padscantype = 0) (tpy1) 1 (touch) waitpentouch touch detected 0 (release) standby lowpower l datascan x-, x+, y-, y+ interval release detected 1 (touch) 0 (release) tpy,tpx (padscantype = 1) touch detected lowpower z, x-, x+, y-, y+ release detected 19.6.2 a/d port scan timing the a/d port scan function sequentially scans the a/d converters four input channel port pins and stores the data in the data buffer used for a/d port scanning. the following figure shows an a/d port scan timing diagram. figure 19-7. a/d port scan timing xxx state: st andby, waitpentouch, or interval state audioin, adin[2:0] adpsstart bit (piuascnreg) adportscan audioin, adin2, adin1, adin0 xxx xxx chapter 19 piu (touch panel interface unit) 405 19.7 data loss interrupt conditions the piu issues a piudatalostintr interrupt when any of the following four conditions exist. once a piudatalostintr interrupt occurs, the sequencer is forcibly changed to the standby state. 1. data for one coordinate has not been obtained within the interval period 2. the a/d port scan has not been completed within the time set via piustblreg 3. transfer of the next coordinate data has begun while valid data for both pages remains in the buffer 4. the next data transfer starts while there is valid data in the adportscan buffer (1) when data for one coordinate has not been obtained within the interval period cause this condition occurs when the aiu has exclusive use of the a/d converter and the piu is therefore unable to use the a/d converter. if this data loss condition occurs frequently, implement a countermeasure that temporarily prohibits the aius use of the a/d converter. response after clearing the cause of the piudatalostintr interrupt, set piuciucntregs padatstart bit or padscanstart bit to restart the coordinate detection operation. once the piudatalostintr interrupt is cleared, the page in which the loss occurred becomes invalid. if the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the piudatalostintr interrupt. (2) when the a/d port scan has not been completed within the time set via piustblreg cause same as cause of condition 1 response after clearing the cause of the piudatalostintr interrupt, set piuascnregs adpsstart bit to restart the a/d port scan operation. once the piudatalostintr interrupt is cleared, the page in which the loss occurred becomes invalid. if the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the piudatalostintr interrupt. (3) when transfer of the next coordinate data has begun while valid data for both pages remains in the buffer cause this condition is caused when the data buffer contains two pages of valid data (both the piupage1intr and piupage0intr interrupts have occurred) but the valid data has not been processed. if the a/d converter is used frequently, this may shorten the time that would normally be required from when both pages become full until when the data loss occurs. chapter 19 piu (touch panel interface unit) 406 response in condition 3, valid data contained in the pages when the piudatalostintr interrupt occurs is never overwritten. after two pages of valid data are processed, clear the causes of the three interrupts (piudatalostintr, piupage1intr, and piupage0intr). after clearing these interrupt causes, set the padatstart bit or padscanstart bit of piucntreg to restart the coordinate detection operation. (4) when the next data transfer starts while there is valid data in the adportscan buffer cause this condition is caused when valid data is not processed even while the adportscan buffer holds valid data (padadpintr interrupt occurrence). response in condition 4, valid data contained in the buffer when the piudatalostintr interrupt occurs is never overwritten. after valid data in the buffer is processed, clear the causes of the two interrupts (piudatalostintr, padadpintr). after clearing these interrupt causes, set the adpsstart bit of piuascnreg to restart the general- purpose a/d port scan. chapter 19 piu (touch panel interface unit) 407 19.8 comparison of v r 4102 and v r 4101 tm table 19-6. comparison of pius of v r 4102 and v r 4101 item v r 4102 v r 4101 a/d converter on-chip (10 bits) external (10/12 bits) data transfer transfer to buffer in piu dma transfer data buffers four buffers (two pages each) for coordinate data only four buffers for a/d scan one buffer scan types coordinate data scan command scan a/d scan coordinate data scan command scan main battery scan sub battery scan a/d port scan activation states standby, waitpen touch, interval standby panel applied voltage stabilization standby time counter 6 bits 4 bits panel applied voltage during low- voltage mode all four touch panel pins are at low level all four touch panel pins are at hi-z panel state during disable state touch detection state (interrupts do not occur when cpu is in hibernate mode.) all four touch panel pins are at hi-z handling of valid data when data loss occurs valid data is always retained valid data is overwritten data interrupt three types of special-purpose interrupts (two coordinate data interrupts, a/d scan interrupt, and command scan interrupt) two types of page boundary interrupts piudatardyintr no yes 408 [memo] 409 chapter 20 aiu (audio interface unit) this chapter describes the aius operations and register settings. 20.1 general the aiu supports speaker output and mic input operations. it is also used to set the a/d and d/a converter operations. 20.2 register set the aiu registers are listed below. table 20-1. aiu registers address r/w register symbols function 0x0b00 0160 r/w mdmadatreg mike dma data register 0x0b00 0162 r/w sdmadatreg speaker dma data register 0x0b00 0166 r/w sodatreg speaker output data register 0x0b00 0168 r/w scntreg speaker output control register 0x0b00 016a r/w scnvrreg speaker conversion rate register 0x0b00 0170 r/w midatreg mike input data register 0x0b00 0172 r/w mcntreg mike input control register 0x0b00 0174 r/w mcnvrreg mike conversion rate register 0x0b00 0178 r/w dvalidreg data valid register 0x0b00 017a r/w seqreg sequential register 0x0b00 017c r/w intreg interrupt register these registers are described in detail below. chapter 20 aiu (audio interface unit) 410 20.2.1 mdmadatreg (0x0b00 0160) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved mdma[9] mdma[8] r/w rrrrrrr/wr/w rtcrst 00000010 other resets 0 0 0 0 0 0 1 0 bitd7d6d5d4d3d2d1d0 name mdma[7] mdma[6] mdma[5] mdma[4] mdma[3] mdma[2] mdma[1] mdma[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 00000000 other resets 0 0 0 0 0 0 0 0 bit name function d[15:10] reserved write 0 when writing. 0 is returned after a read. d[9:0] mdma[9:0] mic input dma data (from midatreg to buffer) this register is used prior to dma transfer to store 10-bit data that has been converted by the a/d converter and stored in midatreg. write is used for debugging and is enabled when aiumen bit of seqreg is set to 1. this register is cleared (0x0200) by resetting aiumen bit of seqreg to 0. chapter 20 aiu (audio interface unit) 411 20.2.2 sdmadatreg (0x0b00 0162) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved sdma[9] sdma[8] r/w rrrrrrr/wr/w rtcrst 00000010 other resets 0 0 0 0 0 0 1 0 bitd7d6d5d4d3d2d1d0 name sdma[7] sdma[6] sdma[5] sdma[4] sdma[3] sdma[2] sdma[1] sdma[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 00000000 other resets 0 0 0 0 0 0 0 0 bit name function d[15:10] reserved write 0 when writing. 0 is returned after a read. d[9:0] sdma[9:0] speaker output dma data (from buffer to sodatreg) this register is used to store 10-bit dma data for speaker output. when sodatreg is empty, the data is transferred to sodatreg. write is used for debugging and is enabled when aiusen bit of seqreg is set to 1. this register is cleared (0x0200) by resetting aiusen bit of seqreg to 0. chapter 20 aiu (audio interface unit) 412 20.2.3 sodatreg (0x0b00 0166) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved sodat[9] sodat[8] r/w rrrrrrr/wr/w rtcrst 0 0 0 0 0 0 1 0 other resets 0 0 0 0 0 0 1 0 bitd7d6d5d4d3d2d1d0 name sodat[7] sodat[6] sodat[5] sodat[4] sodat[3] sodat[2] sodat[1] sodat[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:10] reserved write 0 when writing. 0 is returned after a read. d[9:0] sodat[9:0] speaker output data (from sdmadatreg to d/a converter) this register is used to store 10-bit dma data for speaker output. data is sent from the d/a converter to sdmadatreg. write is used for debugging and is enabled when aiusen bit of seqreg is set to 1. this register is cleared (0x0200) by resetting aiusen bit of seqreg to 0. chapter 20 aiu (audio interface unit) 413 20.2.4 scntreg (0x0b00 0168) bit d15 d14 d13 d12 d11 d10 d9 d8 name daenaiu reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved sstate reserved sstopen reserved r/w rrrrrrr/wr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15] daenaiu this is the speaker d/a enable bit. it controls the on/off status of the vref input to the d/a converters ladder resistors. 1 : vref on 0 : vref off d[14:4] reserved write 0 when writing. 0 is returned after a read. d[3] sstate indicates speaker operation state 1 : in operation 0 : stopped d[2] reserved write 0 when writing. 0 is returned after a read. d[1] sstopen speaker output dma transfer 1-page boundary interrupt stop 1 : stop dma request at 1-page boundary 0 : stop dma request at 2-page boundary d[0] reserved write 0 when writing. 0 is returned after a read. this register is used to control the aius speaker block. daenaiu bit controls the connection of dv dd and vref input to ladder type resistors in the d/a converter. setting this bit to 0 (off) allows low power consumption when not using the d/a converter. when using d/a converter, this bit must be set following the sequence described in 20.3. the contents of sstate bit is valid only when aiusen bit of seqreg is set to 1. chapter 20 aiu (audio interface unit) 414 20.2.5 scnvrreg (0x0b00 016a) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved scnvr[2] scnvr[1] scnvr[0] r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:3] reserved write 0 when writing. 0 is returned after a read. d[2:0] scnvr[2:0] d/a conversion rate 111 : rfu : 101 : rfu 100 : 8 ksps 011 : rfu 010 : 44.1 ksps 001 : 22.05 ksps 000 : 11.025 ksps this register is used to select a conversion rate for the d/a converter. chapter 20 aiu (audio interface unit) 415 20.2.6 midatreg (0x0b00 0170) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved midat[9] midat[8] r/w rrrrrrr/wr/w rtcrst 0 0 0 0 0 0 1 0 other resets 0 0 0 0 0 0 1 0 bitd7d6d5d4d3d2d1d0 name midat[7] midat[6] midat[5] midat[4] midat[3] midat[2] midat[1] midat[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:10] reserved write 0 when writing. 0 is returned after a read. d[9:0] midat[9:0] mic input data (from a/d to mdmadatreg) this register is used to store 10-bit speaker input data that has been converted by the a/d converter. data is sent to mdmadatreg and is received from the a/d converter. write is used for debugging and is enabled when aiumen bit of seqreg is set to 1. this register is cleared (0x0200) by resetting aiumen bit of seqreg to 0. chapter 20 aiu (audio interface unit) 416 20.2.7 mcntreg (0x0b00 0172) bit d15 d14 d13 d12 d11 d10 d9 d8 name adenaiu reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved mstate reserved mstopen adreqaiu r/w rrrrrrr/wr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15] adenaiu this is the mic a/d enable bit. it controls the on/off status of the vref input to the d/a converters ladder resistors in the a/d converter. 1 : vref on 0 : vref off d[14:4] reserved write 0 when writing. 0 is returned after a read. d[3] mstate indicates mic operation state (= aiumen) 1 : in operation 0 : stopped d[2] reserved write 0 when writing. 0 is returned after a read. d[1] mstopen mic input dma transfer 1-page boundary interrupt stop 1 : stop dma request at 1-page boundary 0 : stop dma request at 2-page boundary d[0] adreqaiu a/d use request bit 1 : request 0 : normal this register is used to control the aius mic block. adenaiu bit controls the connection of av dd and vref input to ladder type resistors in the a/d converter. setting this bit to 0 (off) allows low power consumption when not using the a/d converter. when using a/d converter, this bit must be set following the sequence described in 20.3. the contents of mstate bit is valid only when aiumen bit of seqreg is set to 1. this unit has priority when a conflict occurs with the piu in relation to a/d requests. chapter 20 aiu (audio interface unit) 417 20.2.8 mcnvrreg (0x0b00 0174) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved mcnvr[2] mcnvr[1] mcnvr[0] r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:3] reserved write 0 when writing. 0 is returned after a read. d[2:0] mcnvr[2:0] a/d conversion rate 111 : rfu : 101 : rfu 100 : 8 ksps 011 : rfu 010 : 44.1 ksps 001 : 22.05 ksps 000 : 11.025 ksps this register is used to select a conversion rate for the a/d converter. chapter 20 aiu (audio interface unit) 418 20.2.9 dvalidreg (0x0b00 0178) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved sodatv sdmav midatv mdmav r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:4] reserved write 0 when writing. 0 is returned after a read d[3] sodatv this indicates when valid data has been stored in sodatreg. 1 : valid data exists 0 : no valid data d[2] sdmav this indicates when valid data has been stored in sdmadatreg. 1 : valid data exists 0 : no valid data d[1] midatv this indicates when valid data has been stored in midatreg. 1 : valid data exists 0 : no valid data d[0] mdmav this indicates when valid data has been stored in mdmareg. 1 : valid data exists 0 : no valid data this register indicates when valid data has been stored in sodatreg, sdmadatreg, midatreg, or mdmareg. if data has been written directly to sodatreg, sdmadatreg, midatreg, or mdmareg via software, the bits in this register are not active, so write 1 via software. write is used for debugging and is enabled when aiusen or aiumen bit of seqreg is set to 1. if aiusen = 0 or aiumen = 0 in seqreg, then sodatv = sdmav = 0 or midatv = mdmav = 0. chapter 20 aiu (audio interface unit) 419 20.2.10 seqreg (0x0b00 017a) bit d15 d14 d13 d12 d11 d10 d9 d8 name aiurst reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved aiumen reserved reserved reserved aiusen r/w r r r r/w r r r r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15] aiurst aiu reset via software 1 : reset 0 : normal d[14:5] reserved write 0 when writing. 0 is returned after a read. d[4] aiumen mic block operation enable, dma enable 1 : enable operation 0 : disable operation d[3:1] reserved write 0 when writing. 0 is returned after a read. d[0] aiusen speaker block operation enable, dma enable 1 : enable operation 0 : disable operation this register is used to enable/disable the aius operation. chapter 20 aiu (audio interface unit) 420 20.2.11 intreg (0x0b00 017c) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved mendintr mintr midleintr mstintr r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved sendintr sintr sidleintr reserved r/w r r r r r/w r/w r/w r rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:12] reserved write 0 when writing. 0 is returned after a read. d[11] mendintr mic dma 2 page interrupt. cleared to 0 when 1 is written. 1 : occurred 0 : normal d[10] mintr mic dma 1 page interrupt. cleared to 0 when 1 is written. 1 : occurred 0 : normal d[9] midleintr mic idle interrupt (receive data loss). cleared to 0 when 1 is written. 1 : occurred 0 : normal d[8] mstintr mic receive complete interrupt. cleared to 0 when 1 is written. 1 : occurred 0 : normal d[7:4] reserved write 0 when writing. 0 is returned after a read. d[3] sendintr speaker dma 2 page interrupt. cleared to 0 when 1 is written. 1 : occurred 0 : normal d[2] sintr speaker dma 1 page interrupt. cleared to 0 when 1 is written. 1 : occurred 0 : normal d[1] sidleintr speaker idle interrupt (mute). cleared to 0 when 1 is written. 1 : occurred 0 : normal d[0] reserved write 0 when writing. 0 is returned after a read. this register indicates the aius interrupt status. when data is received from the a/d converter, midleintr is set if valid data still exists in midatreg (midatv = 1). in this case, midatreg is overwritten. mstintr is set when data is received in mdmadatreg. when data is passed to the d/a converter, sidleintr is set if there is no valid data in sodatreg (sodatv = 0). however, this interrupt is valid only after aiusen = 1, after which sodatv = 1. chapter 20 aiu (audio interface unit) 421 20.3 operation sequence 20.3.1 output (speaker) 1. set conversion rate (0x0b00 016a: scnvr = arbitrary) 2. set output data area to dmaau 3. dma enable in dcu 4. set d/a converters vref to on (0x0b00 0168: daenaiu = 1) 5. wait for vref resistor stabilization time (about 5 p s) (use the rtc counter) even if speaker power is set to on without waiting for vref resistor stabilization time and speaker operation is enabled, speaker output starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8) ( p s) 6. set speaker power on via gpio. 7. speaker operation enable (0x0b00 017a: aiusen = 1) dma request receive acknowledge and dma data from dma 0x0b00 0178: sdmav = sodatv = 1 output 10-bit data (0x0b00 0166: sodat) to d/a converter sodatv = 0, sdmav = 1 send sdmadatreg data to sodatreg sodatv = 1, sdmav = 0 output dma request and store the second data to sdmadatreg sodatv = 1, sdmav = 1 refresh data at each conversion timing interval (becomes sidleintr = 1 when dma is slow and sodatv = 0 during conversion timing interval, and (mute) interrupt occurs) dma page boundary interrupt occurs at page boundary page interrupt is cleared when output continues 8. speaker operation to disable (0x0b00 017a: aiusen = 0) 9. set speaker power off via gpio. 10. set d/a converters vref to off (0x0b00 0168: daenaiu = 0) 11. dma disable in dcu chapter 20 aiu (audio interface unit) 422 20.3.2 input (mic) 1. set conversion rate (0x0b00 0174: mcnvr = arbitrary) 2. set input data area in dmaau 3. dma enable in dcu 4. set a/d converters vref to on (0x0b00 0172: adenaiu = 1) mic power can be set on and mic operation can be enabled without waiting for vref resistor stabilization time (about 5 p s). however, in such a case, sampling starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8) ( p s) 5. set mic power on via gpio. 6. mic operation enable (0x0b00 017a: aiumen = 1) output a/d request (adreqaiu) to a/d converter return acknowledge (aiuadack) and 10-bit conversion data from a/d converter store data in midatreg 0x0b00 0178: mdmav = 0, midatv = 1 transfer data from midatreg to mdmadatreg mdmav = 1, midatv = 0 the intmst value becomes 1 and an interrupt (receive complete) occurs issue dma request and store midmadatreg data to memory. mdmav = 0, midatv = 0 an a/d request is issued once per conversion timing interval and 10-bit data is received (becomes midleintr = 1 when dma is slow and midatv = 1 during conversion timing interval, and (data loss) interrupt occurs) dma page boundary interrupt occurs at page boundary (page interrupt is cleared when output continues) 7. mic operation to disable (0x0b00 017a: aiumen = 0) 8. set mic power off via gpio 9. set a/d converters vref to off (0x0b00 0172: aiuaden = 0) 10. dma disable in dcu 423 chapter 21 kiu (keyboard interface unit) this chapter describes the kius operations and register settings. 21.1 general the kiu includes 12 scan lines and 8 detection lines. the number of key inputs to be detected can be selected from 96/80/64, by switching the number of scan lines from 12/10/8. the register can be set to enable the 12 scan lines to be used as a general-purpose output port. 21.2 register set the kiu registers are listed below. table 21-1. kiu registers address r/w register symbols function 0x0b00 0180 r/w kiudat0 kiu data0 register 0x0b00 0182 r/w kiudat1 kiu data1 register 0x0b00 0184 r/w kiudat2 kiu data2 register 0x0b00 0186 r/w kiudat3 kiu data3 register 0x0b00 0188 r/w kiudat4 kiu data4 register 0x0b00 018a r/w kiudat5 kiu data5 register 0x0b00 0190 r/w kiuscanrep kiu scan/repeat register 0x0b00 0192 r kiuscans kiu scan status register 0x0b00 0194 r/w kiuwks kiu wait ke yscan stable register 0x0b00 0196 r/w kiuwki kiu wait ke yscan interval register 0x0b00 0198 r/w kiuint kiu interrupt register 0x0b00 019a w kiurst kiu reset register 0x0b00 019c r/w kiugpen kiu general purpose output enable 0x0b00 019e r/w scanline kiu scan line register chapter 21 kiu (keyboard interface unit) 424 21.2.1 kiudatn (0x0b00 0180 to 0x0b00 018a) remark n = 0 to 5 kiudat0 (0x0b00 0180) kiudat1 (0x0b00 0182) kiudat2 (0x0b00 0184) kiudat3 (0x0b00 0186) kiudat4 (0x0b00 0188) kiudat5 (0x0b00 018a) bit d15 d14 d13 d12 d11 d10 d9 d8 name keydat[15] keydat[14] keydat[13] keydat[12] keydat[11] keydat[10] keydat[9] keydat[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name keydat[7] keydat[6] keydat[5] keydat[4] keydat[3] keydat[2] keydat[1] keydat[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..8] keydat[15..8] scan data from odd-numbered scans d[7..0] keydat[7..0] scan data from even-numbered scans these registers are used to hold key scan data. each kiu data register is able to hold the data from one scan operation. how scan data is input to the registers is as below. bit register keydat[15..8] keydat[7..0] kiudat0 scan[1] scan[0] kiudat1 scan[3] scan[2] kiudat2 scan[5] scan[4] kiudat3 scan[7] scan[6] kiudat4 scan[9] scan[8] kiudat5 scan[11] scan[10] chapter 21 kiu (keyboard interface unit) 425 21.2.2 kiuscanrep (0x0b00 0190) bit d15 d14 d13 d12 d11 d10 d9 d8 name keyen reserved reserved reserved reserved reserved stprep[5] stprep[4] r/w r/wrrrrrr/wr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name stprep[3] stprep[2] stprep[1] stprep[0] scanstp scanstart atstp atscan r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bit name function d[15] keyen key scan 1 : enable 0 : prohibit d[14..10] reserved write 0 when writing. 0 is returned after a read. d[9..4] stprep[5..0] key scan sequencer stop count setting 111111 : 63 times : 000001 : 1 time 000000 : 64 times d[3] scanstp key scan stop 1 : stop 0 : operate d[2] scanstart key scan start 1 : start 0 : stop d[1] atstp key auto stop setting 1 : auto stop 0 : not auto stop d[0] atscan key auto scan setting 1 : auto scan 0 : not auto scan this register is used to enable operation of the key scan unit and to make settings for key scan and the key scan sequencer. ? key scan sequencer stop count setting this sets the number of key scan sequencer stops when no keys are being pressed. chapter 21 kiu (keyboard interface unit) 426 ? key scan stop when the scanstp bit is set to 1, the key scan sequencer stops. however, if this bit is set to 1 during a key scan operation, the key scan sequencer stops after the current set of key data is received. ? key scan start when the scanstart bit is set to 1, the key scan sequencer starts regardless of key contact detection. ? key scan auto stop setting when the atstop bit is set to 1, the key scan sequencer stops automatically when the data remains all zeros for the number of key scan times specified by stoprep. ? key auto scan setting when the atscan bit is set to 1, the key scan operation automatically starts after key contact is detected. chapter 21 kiu (keyboard interface unit) 427 21.2.3 kiuscans (0x0b00 0192) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved sstat[1] sstat[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..2] reserved write 0 when writing. 0 is returned after a read. d[1..0] sstat[1..0] kiu sequencer status 11 : scanning 10 : interval next scan 01 : waitkeyin 00 : stopped this register indicates the current kiu sequencer status. chapter 21 kiu (keyboard interface unit) 428 details of the status of the kiu sequencer are described below. ? scanning: this is the state where the scan sequencer performs key scan to load key data. ? interval next scan: this is the state where the scan of a set of key data note has completed and waiting for the start of the next key scan. the interval after the completion of the scan of a set of key data until the start of the next scan is set on the kiuwkireg. note the number of data bits depends on the number of kscan pins used as below. the number of kscan pins is set in scanline register. kscan pins number of data bits 8 64 bits 10 80 bits 12 96 bits ? wait key in: this is the state of waiting for key input in the key auto scan mode. when the scan sequencer is enabled while atscan bit of kiuscanrep register is set to 1, the v r 4102 waits for key input in this state. in this case, all outputs of the kscan pins note are in high level. when shifting the cpu to suspend mode (or standby mode with tclock masked), be sure to set the kiu to the auto scan mode before the shift and confirm that the sequencer in the wait key in state. note the number of pins is set in line[1..0] bits of scanline register as below. line[1..0] number of kscan pins 10 8 01 10 00 12 ? stopped: this is the state where the sequencer is disabled. chapter 21 kiu (keyboard interface unit) 429 21.2.4 kiuwks (0x0b00 0194) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved t3cnt[4] t3cnt[3] t3cnt[2] t3cnt[1] t3cnt[0] t2cnt[4] t2cnt[3] r/w r r/w r/w r/w r/w r/w r/w r/w rtcrst 0 1 1 1 1 1 1 1 other resets 0 1 1 1 1 1 1 1 bitd7d6d5d4d3d2d1d0 name t2cnt[2] t2cnt[1] t2cnt[0] t1cnt[4] t1cnt[3] t1cnt[2] t1cnt[1] t1cnt[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15] reserved write 0 when writing. 0 is returned after a read. d[14..10] t3cnt[4..0] wait time setting ((t3cnt[4..0] + 1) * 30 p s) 11111 : 960 p s : 00001 : 60 p s 00000 : rfu d[9..5] t2cnt[4..0] off time setting ((t2cnt[4..0] + 1) * 30 p s) 11111 : 960 p s : 00001 : 60 p s 00000 : rfu d[4..0] t1cnt[4..0] stabilization time setting ((t1cnt[4..0] + 1) * 30 p s) 11111 : 960 p s : 00001 : 60 p s 00000 : rfu this register is used to set the wait time between when the key scan sequencer sets the kscan pin high during a key matrix scan and when the status is read from the kport pin. the t1cnt bit is used to set the stabilization time between when voltage is applied to the kscan pin and when the key scan data is read. the t2cnt bit is used to set the time between when the key data is read and when voltage applied to the kscan pin is set to off. the t3cnt bit is used to set the time between when voltage applied to the kscan pin is set to off and when voltage can be again applied to the kscan pin. the status of output from the kscan pins and the timing of kport sampling are shown below. chapter 21 kiu (keyboard interface unit) 430 t1 t1 kscan[n] kscan[n+1] hi-z kport sampling t2 t3 t2 hi-z hi-z hi-z kport sampling 21.2.5 kiuwki (0x0b00 0196) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved wintvl[9] wintvl[8] r/w rrrrrrr/wr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name wintvl[7] wintvl[6] wintvl[5] wintvl[4] wintvl[3] wintvl[2] wintvl[1] wintvl[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..10] reserved write 0 when writing. 0 is returned after a read. d[9..0] wintvl[9..0] key scan interval time setting (wintvl[9..0]*30 p s) 1111111111 : 30690 p s : 0000000001 : 30 p s 0000000000 : no wait this register is used to set the interval time between when one set of key data is obtained by the key scan sequencer and when the next set of key data is obtained. chapter 21 kiu (keyboard interface unit) 431 21.2.6 kiuint (0x0b00 0198) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved kdatlost kdatrdy scanint r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..3] reserved write 0 when writing. 0 is returned after a read. d[2] kdatlost key scan data lost interrupt. cleared to 0 when 1 is written. 1 : yes 0 : no d[1] kdatrdy key data scan complete interrupt. cleared to 0 when 1 is written. 1 : yes 0 : no d[0] scanint key input detection interrupt. cleared to 0 when 1 is written. 1 : yes 0 : no this register indicates the type of interrupt that has occurred in the kiu. chapter 21 kiu (keyboard interface unit) 432 21.2.7 kiurst (0x0b00 019a) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved kiurst r/w rrrrrrrw rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] kiurst kiu reset. cleared to 0 when 1 is written. 1 : reset 0 : normal operation this register is used to forcibly reset the kiu. chapter 21 kiu (keyboard interface unit) 433 21.2.8 kiugpen (0x0b00 019c) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved kgpen[11] kgpen[10] kgpen[9] kgpen[8] r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name kgpen[7] kgpen[6] kgpen[5] kgpen[4] kgpen[3] kgpen[2] kgpen[1] kgpen[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..12] reserved write 0 when writing. 0 is returned after a read. d[11..0] kgpen[11..0] scan pin function 1 : use as output port 0 : use as scan pin this register is used to set whether or not the kscan pins will function as a general-purpose output port. setting a 1 to each bit in this register enables the kscan pin to function as a general-purpose output port. the output port setting are made via the gius giupodatl register (0x0b00 011c). chapter 21 kiu (keyboard interface unit) 434 21.2.9 scanline (0x0b00 019e) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved line[1] line[0] r/w rrrrrrr/wr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..2] reserved write 0 when writing. 0 is returned after a read. d[1..0] line[1..0] scan pin use/do not use setting 11 : do not use scan pins for key scan the kius scan pins can be used as an output port. 10 : use eight key scan pins (kscan[7..0]) key scan uses eight key scan pins (supports 64 keys) the remaining four pins can be used as an output port. 01 : use ten key scan pins (kscan[9..0]) key scan uses ten key scan pins (supports 80 keys) the remaining two pins can be used as an output port. 00 : use twelve key scan pins (kscan[11..0]) key scan uses twelve key scan pins (supports 96 keys) no pins can be used as an output port. this register is used to switch the number of scan lines. 435 chapter 22 dsiu (debug serial interface unit) this chapter describes the dsius operations and register settings. 22.1 general the dsiu (debug serial interface unit) supports transfer rates up to 115.2 kbps. in addition to the ddin and ddout input/output pins, the dsiu supports the dcts# and drts# pins that are used for hardware flow control. 22.2 register set the dsiu registers are listed below. table 22-1. dsiu registers address r/w register symbols function 0x0b00 01a0 r/w portreg port change register 0x0b00 01a2 r modemreg modem control register 0x0b00 01a4 r/w asim00reg asynchronous mode 0 register 0x0b00 01a6 r/w asim01reg asynchronous mode 1 register 0x0b00 01a8 r rxb0rreg receive buffer register (extended) 0x0b00 01aa r rxb0lreg receive buffer register 0x0b00 01ac r/w txs0rreg transmit data register (extended) 0x0b00 01ae r/w txs0lreg transmit data register 0x0b00 01b0 r asis0reg status register 0x0b00 01b2 r/w intr0reg debug siu interrupt register 0x0b00 01b6 r/w bprm0reg baud rate generator prescaler mode register 0x0b00 01b8 r/w dsiuresetreg debug siu reset register these registers are described in detail below. chapter 22 dsiu (debug serial interface unit) 436 22.2.1 portreg (0x0b00 01a0) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved cddin cddout cdrts cdcts r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:4] reserved write 0 when writing. 0 is returned after a read. d[3] cddin this pin is used to switch the ddin pin for use as a general-purpose output pin. 1 : general-purpose output 0 : ddin d[2] cddout this pin is used to switch the ddout pin for use as a general-purpose output pin. 1 : general-purpose output 0 : ddout d[1] cdrts this pin is used to switch the drts# pin for use as a general-purpose output pin. 1 : general-purpose output 0 : drts# d[0] cdcts this pin is used to switch the dcts# pin for use as a general-purpose output pin. 1 : general-purpose output 0 : dcts# this register is used to switch the dsiu pin for use as a general-purpose output pin. note that the output value should be set in the giu when the dsiu pins are set to general-purpose outputs. chapter 22 dsiu (debug serial interface unit) 437 22.2.2 modemreg (0x0b00 01a2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved drts dcts r/w rrrrrrrr rtcrst 0 0 0 0 0 0 1 1 other resets 0 0 0 0 0 0 1 1 bit name function d[15:2] reserved write 0 when writing. 0 is returned after a read. d[1] drts drts# pin output 1: high level 0: low level d[0] dcts dcts# pin input 1: high level 0: low level this register is used for flow control and can be used to pass signals between the v r 4102 and external agents. note that the setting of rxe0 bit of asim00reg is reflected on the output from drts# pin. chapter 22 dsiu (debug serial interface unit) 438 22.2.3 asim00reg (0x0b00 01a4) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved rxe0 ps0[1] ps0[0] cl0 sl0 reserved reserved r/w r r/w r/w r/w r/w r/w r r rtcrst 1 0 0 0 0 0 0 0 other resets 1 0 0 0 0 0 0 0 bit name function d[15:8] reserved write 0 when writing. 0 is returned after a read. d[7] reserved write 1 when writing. 1 is returned after a read. d[6] rxe0 debug serial reception enable 1 : enable 0 : prohibit d[5:4] ps0[1:0] debug serial parity select 11 : even parity 10 : odd parity 01 : zero parity bits during transmit no parity during receive 00 : no parity. set to 00 for extended-bit operations d[3] cl0 debug serial character length setting 1 : 8 bits 0 : 7 bits d[2] sl0 debug serial stop bit setting 1 : 2 bits 0 : 1 bit d[1:0] reserved write 0 when writing. 0 is returned after a read. this register is used to make various serial communication settings for debugging. the setting of rxe0 bit is reflected on the output from drts# pin. 0 is output when this bit is set to 1 (reception enable), and 1 is output when this bit is set to 0 (reception prohibit). if this register is changed during transmission or reception of serial data for debugging, the dsius operations cannot be guaranteed. chapter 22 dsiu (debug serial interface unit) 439 22.2.4 asim01reg (0x0b00 01a6) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved ebs0 r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:1] reserved write 0 when writing. 0 is returned after a read. d[0] ebs0 extended bit operation enable 1 : enable 0 : prohibit this register is used to set extended bit operations for the dsiu. when 1 is set to the ebs0 bit, one bit is added to the 8-bit data length for transmission and reception to enable operations using 9-bit data. extended-bit operations are valid only when 00 has been set to asim00regs ps0[1:0] bit. if a value other than 00 has been set to asim00regs ps0[1:0] bit, the ebs0 bit specification is ignored and extended-bit operations cannot be performed. chapter 22 dsiu (debug serial interface unit) 440 22.2.5 rxb0rreg (0x0b00 01a8) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved rxb0[8] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name rxb0[7] rxb0[6] rxb0[5] rxb0[4] rxb0[3] rxb0[2] rxb0[1] rxb0[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:9] reserved write 0 when writing. 0 is returned after a read. d[8:0] rxb0[8:0] receive data [8:0] this register is used to store debug serial receive data. the rxb0[8] bit stores the extended bit during extended-bit operations and stores a zero during 7- or 8-bit character reception. the rxb0[7] bit stores a zero during 7-bit character reception. chapter 22 dsiu (debug serial interface unit) 441 22.2.6 rxb0lreg (0x0b00 01aa) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name rxb0l[7] rxb0l[6] rxb0l[5] rxb0l[4] rxb0l[3] rxb0l[2] rxb0l[1] rxb0l[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:8] reserved write 0 when writing. 0 is returned after a read. d[7:0] rxb0l[7:0] receive data [7:0] this register is used to store debug serial receive data. the rxb0l[7] bit stores a zero during 7-bit character reception. the only difference between this register and rxb0rreg is that this register does not support extended-bit operations. chapter 22 dsiu (debug serial interface unit) 442 22.2.7 txs0rreg (0x0b00 01ac) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved txs0[8] r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bitd7d6d5d4d3d2d1d0 name txs0[7] txs0[6] txs0[5] txs0[4] txs0[3] txs0[2] txs0[1] txs0[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15:9] reserved write 0 when writing. 0 is returned after a read. d[8:0] txs0[8:0] transmit data [8:0] this register is used to store debug serial transmit data. the txs0[8] bit is used to transmit the extended bit during extended-bit operations. chapter 22 dsiu (debug serial interface unit) 443 22.2.8 txs0lreg (0x0b00 01ae) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name txs0l[7] txs0l[6] txs0l[5] txs0l[4] txs0l[3] txs0l[2] txs0l[1] txs0l[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets 1 1 1 1 1 1 1 1 bit name function d[15:8] reserved write 0 when writing. 0 is returned after a read. d[7:0] txs0l[7:0] transmit data [7:0] this register is used to store debug serial transmit data. the only difference between this register and txs0rreg is that this register does not support extended-bit operations. chapter 22 dsiu (debug serial interface unit) 444 22.2.9 asis0reg (0x0b00 01b0) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name sot0 reserved reserved reserved reserved pe0 fe0 ove0 r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:8] reserved write 0 when writing. 0 is returned after a read. d[7] sot0 transmit mode status 1 : transmission start 0 : transmission complete d[6:3] reserved write 0 when writing. 0 is returned after a read. d[2] pe0 parity error status 1 : parity error 0 : normal d[1] fe0 framing error status 1 : framing error 0 : normal d[0] ove0 overrun error status 1 : overrun error status 0 : normal this register indicates the debug serial transmit/receive status. a write to the txs0rreg or txs0lreg register sets 1 to the sot0 bit. when the transmission is completed, 1 is set to the intr0reg registers intst0 bit and the sot0 bit is cleared to zero. this bit can be used as a means of determining whether or not it is possible to write to the transmission shift register when transmitting data in debug serial mode. if the received data contains a parity error, 1 is set to the pe0 bit. if the stop bit is not detected, 1 is set to the fe0 bit. an overrun error occurs and 1 is set to the ove0 bit if the sequencer completes the next receive processing before receive data is read from the receive buffer. when an overrun error occurs, the old data in the receive buffer is overwritten by the newly received data. chapter 22 dsiu (debug serial interface unit) 445 22.2.10 intr0reg (0x0b00 01b2) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved intdcd intser0 intsr0 intst0 r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:4] reserved write 0 when writing. 0 is returned after a read. d[3] intdcd cts# change interrupt. cleared to 0 when 1 is written. 1 : cts change interrupt 0 : normal d[2] intser0 debug serial receive error interrupt. cleared to 0 when 1 is written. 1 : error interrupt 0 : normal d[1] intsr0 debug serial receive complete interrupt. cleared to 0 when 1 is written. 1 : receive complete 0 : other d[0] intst0 debug serial transmit complete interrupt. cleared to 0 when 1 is written. 1 : transmit complete 0 : other this register indicates interrupt events that occur during debug serial transmission. when debug serial operations are in the reception-enable mode, and either the pe0 bit, fe0 bit, or ove0 bit in the asis0reg has been set, 1 is set to the intser0 bit. when debug serial operations are in the reception-enable mode, and receive data is transferred to the receive buffer, 1 is set to the intsr0 bit. when one frame of transmit data is sent from the transmit register, 1 is set to the intst0 bit. when the cts# (flow control signal from an external agent) is changed, 1 is set to intdcd bit. chapter 22 dsiu (debug serial interface unit) 446 22.2.11 bprm0reg (0x0b00 01b6) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name brce0 reserved reserved reserved reserved bpr0[2] bpr0[1] bpr0[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:8] reserved write 0 when writing. 0 is returned after a read. d[7] brce0 baud rate generator count enable 1 : enable 0 : prohibit d[6:3] reserved write 0 when writing. 0 is returned after a read. d[2:0] bpr0[2:0] debug serial baud rate setting 111 : 115200 bps 110 : 57600 bps 101 : 38400 bps 100 : 19200 bps 011 : 9600 bps 010 : 4800 bps 001 : 2400 bps 000 : 1200 bps this register is used to set the baud rate for debug serial communications. debug serial operations are not guaranteed if the baud rate is changed during transmission or reception. chapter 22 dsiu (debug serial interface unit) 447 22.2.12 dsiuresetreg (0x0b00 01b8) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved dsiurst r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:1] reserved write 0 when writing. 0 is returned after a read d[0] dsiurst debug serial reset. cleared to 0 when 1 is written. 1 : reset 0 : normal this register is used to reset the debug serial mode. chapter 22 dsiu (debug serial interface unit) 448 22.3 description of operations 22.3.1 data format serial data is transmitted and received in full-duplex mode. the format of the transmit and receive data is shown in the following figure. each frame includes a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length in one data frame, along with the parity setting, and stop bit length specification are all made via the mode registers (asim00reg and asim01reg). figure 22-1. data format for transmission and reception character bits d0 parity d7 d6 d5 d4 d3 d2 d1 start stop 1 data frame z start bit : 1 bit z character bits (dn) : 7, 8, or 9 bits (when using extended bit) (n = 0 to 8) z parity bit : even parity, odd parity, zero parity, or no parity z stop bit(s) : 1 bit or 2 bits chapter 22 dsiu (debug serial interface unit) 449 22.3.2 transmission after the dcts# pin value is confirmed as 1, writing data to a transmission shift register (txs0reg or txs0lreg) activates transmission via the ddout pin. use the transmit complete interrupt (dsiu_intst0) service routine to write the next data to txs0reg or txs0lreg. transmission enable status the dsiu unit is always set to transmission enable status. the dcts# pin is used when it is necessary to confirm that the remote side is ready to receive. activation of transmit operation writing data to a transmission shift register (txs0reg or txs0lreg) activates the transmit operation. the transmit data is sent in lsb-first order, beginning with the start bit. the start bit, parity bit, and stop bit(s) are added automatically. transmit complete interrupt request once one frame of data has been sent, a transmit complete interrupt request (dsiu_intst0) occurs. if the next data to be transmitted is then not written to txs0reg or txs0lreg, the transmit operation is halted and the transmission rate is lowered. cautions 1. normally, the transmit complete interrupt request (dsiu_intst0) occurs when the txs0reg or txs0lreg register is empty. however, if a reset is input, the transmit complete interrupt request (dsiu_intst0) will not occur even when the transmission shift register (txs0reg or txs0lreg) is empty. 2. writing to either txs0reg or txs0lreg is prohibited during a transmit operation until dsiu_intst0 occurs. chapter 22 dsiu (debug serial interface unit) 450 figure 22-2. transmit complete interrupt timing dsiu_intst0 d0 parity d7 d6 d5 d4 d3 d2 d1 start stop ddout (a) stop bit length: 1 (b) stop bit length: 2 dsiu_intst0 d0 parity d7 d6 d5 d4 d3 d2 d1 start stop ddout stop chapter 22 dsiu (debug serial interface unit) 451 22.3.3 reception once reception enable has been set, sampling of the ddin pin begins and, when a start bit is detected, data reception begins. a receive complete interrupt (dsiu_intst0) occurs each time reception of one frame of data is completed. normally, this interrupt service is used to transfer receive data from a receive buffer (rxb0reg or rxb0lreg) to memory. reception enable status setting the asim00regs bit[6] sets enable status for the receive operation, and a zero is output to drts#. rxe0 = 1: reception enable status drts# = 0 rxe0 = 0: reception prohibit status drts# = 1 the reception hardware is initialized and enters idle mode when reception prohibit status has been set. once that happens, receive complete interrupts and receive error interrupts are not issued and the contents of the receive buffer are retained. activation of receive operation the receive operation is activated when a start bit is detected. the ddin pin is sampled at the interval set by the serial clock specified via the asim00reg. once a signals falling edge is detected at the ddin pin, the ddin pin is again sampled after an interval of eight serial clocks. this time, when a low-level state is detected it is recognized as a start bit and control is passed to the receive operation, after which the ddin pin continues to be sampled using an interval of 16 serial clocks. after eight serial clocks have elapsed since a signals falling edge was detected at the ddin pin, when sampling recognizes a high-level state it does not recognize the signals falling edge as a start bit. instead, the serial clock counter used for the sampling timing is initialized and the receive operation is halted until the next edge input. receive complete interrupt request when rxe0 = 1 and one frame of data has been received, the receive data in the shift register is transferred to rxb0reg and a receive complete interrupt request (dsiu_intsr0) is issued. even when an error has occurred, the receive data for which the error occurred is still transferred to a receive buffer (rxb0reg or rxb0lreg) and two interrupts; a receive complete interrupt (dsiu_intsr0) and a receive error interrupt (dsiu_intser0), occur at the same time. if the rxe0 bit is reset (to 0) during a receive operation, the receive operation is halted immediately. at that point, the contents of the receive buffer (rxb0reg or rxb0lreg) and asis0reg are not changed and neither the receive complete interrupt (dsiu_intsr0) nor the receive error interrupt (dsiu_intser0) occur. figure 22-3. receive complete interrupt timing dsiu_intsr0 d0 parity d7 d6 d5 d4 d3 d2 d1 start stop ddin chapter 22 dsiu (debug serial interface unit) 452 receive error flag receive operations can be affected by three types of error flags that are set during the receive operations: a parity error flag, a framing error flag, and an overrun error flag. a receive error interrupt request is issued after these three types of error flags are ored. during a receive error interrupt (dsiu_intser0), the contents of the asis0reg can be read to detect which kind of error occurred during reception. the contents of the asis0reg are reset (to 0) when the receive buffer (rxb0reg or rxb0lreg) is read or when the next data is received (another error flag is set if the next data also contains an error). table 22-2. receive error causes receive error cause parity error parity specified during reception does not match parity of receive data framing error stop bit is not detected overrun error reception of the next data is completed before data is read from the receive buffer figure 22-4. receive error timing dsiu_intsr0 d0 parity d7 d6 d5 d4 d3 d2 d1 start stop ddin dsiu_intser0 453 chapter 23 led (led control unit) this chapter describes led operations and register settings. 23.1 general an led is switched on and off at a regular interval. the interval can be set as programmable. this unit can operate during standby, suspend, or hibernate mode. 23.2 register set the led registers are listed below. table 23-1. led registers address r/w register symbols function 0x0b00 0240 r/w ledhtsreg led h time set register 0x0b00 0242 r/w ledltsreg led l time set register 0x0b00 0248 r/w ledcntreg led control register 0x0b00 024a r/w ledastcreg led auto stop time count register 0x0b00 024c r/w ledintreg led interrupt register these registers are described in detail below. chapter 23 led (led control unit) 454 23.2.1 ledhtsreg (0x0b00 0240) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved hts[4] hts[3] hts[2] hts[1] hts[0] r/w r r r r/w r/w r/w r/w r/w rtcrst 0 0 0 1 0 0 0 0 other resets 0 0 0 note note note note note bit name function d[15..5] reserved write 0 when writing. 0 is returned after a read. d[4..0] hts[4..0] led on time 00000 : prohibit 00001 : 0.0625 seconds 00010 : 0.125 seconds : 00100 : 0.25 seconds : 01000 : 0.5 seconds : 10000 : 1 second : 11111 : 1.9375 seconds note previous value is retained this register is used to set the leds on time (high-level width of ledout#). the on time ranges from 0.0625 to 1.9375 seconds and can be set in 0.0625-second units. the initial value is 1 second. this register cannot be changed once the ledenable bit of ledcntreg has been set as enable. operation is not guaranteed if a change is made after that point. chapter 23 led (led control unit) 455 23.2.2 ledltsreg (0x0b00 0242) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 00000000 other resets 00000000 bitd7d6d5d4d3d2d1d0 name reserved lts[6] lts[5] lts[4] lts[3] lts[2] lts[1] lts[0] r/w r r/w r/w r/w r/w r/w r/w r/w rtcrst 00100000 other resets 0 note note note note note note note bit name function d[15..7] reserved write 0 when writing. 0 is returned after a read. d[6..0] lts[6..0] led off time 0000000 : prohibit 0000001 : 0.0625 seconds 0000010 : 0.125 seconds : 0000100 : 0.25 seconds : 0001000 : 0.5 seconds : 0010000 : 1 second : 0100000 : 2 seconds : 1000000 : 4 seconds : 1111111 : 7.9375 seconds note previous value is retained this register is used to set the leds off time (low-level width of ledout#). the off time ranges from 0.0625 to 7.9375 seconds and can be set in 0.0625-second units. the initial value is 2 seconds. this register cannot be changed once the ledenable bit of ledcntreg has been set as enable. operation is not guaranteed if a change is made after that point. chapter 23 led (led control unit) 456 23.2.3 ledcntreg (0x0b00 0248) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved ledstop ledenable r/w rrrrrrr/wr/w rtcrst 0 0 0 0 0 0 1 0 other resets 0 0 0 0 0 0 note note bit name function d[15..2] reserved write 0 when writing. 0 is returned after a read. d[1] ledstop led on/off auto stop setting 1 : on 0 : off d[0] ledenable led on/off (blink) setting 1 : blink 0 : do not blink note previous value is retained this register is used to make various led settings. caution when setting up led activation, make sure that a value other than zero has already been set to the ledhtsreg, ledltsreg, and ledastcreg. the operation is not guaranteed if zero is set to these registers. chapter 23 led (led control unit) 457 23.2.4 ledastcreg (0x0b00 024a) bit d15 d14 d13 d12 d11 d10 d9 d8 name astc[15] astc[14] astc[13] astc[12] astc[11] astc[10] astc[9] astc[8] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 1 0 0 other resets 0 0 0 0 0 1 0 0 bitd7d6d5d4d3d2d1d0 name astc[7] astc[6] astc[5] astc[4] astc[3] astc[2] astc[1] astc[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 0 1 1 0 0 0 0 other resets 1 0 1 1 0 0 0 0 bit name function d[15..0] astc[15..0] led auto stop time count bit this register is a 16-bit down counter that sets the number of on/off times prior to automatic stopping of led activation. the set value is read during a read. the pair of operations in which the led is switched on once and off once is counted as 1 by this counter. the counter counts down from the set value and an ledint interrupt occurs when it reaches zero. the initial setting is 1,200 times (on/off pairs) in which each time includes one second of on time and two seconds of off time. caution setting a zero to this register is prohibited. the operation is not guaranteed if zero is set to this register. chapter 23 led (led control unit) 458 23.2.5 ledintreg (0x0b00 024c) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved ledint r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15..1] reserved write 0 when writing. 0 is returned after a read. d[0] ledint auto stop interrupt. cleared to 0 when 1 is written. 1 : yes 0 : no this register indicates when an auto stop interrupt has occurred. an auto stop interrupt occurs if 1 has already been set to bit 1 and bit 0 of the ledcntreg when the ledastcreg is cleared to 0. when this interrupt occurs, bit 1 and bit 0 of the ledcntreg are both cleared to 0. chapter 23 led (led control unit) 459 23.3 operation flow set ledhtsreg set ledltsreg ledcntreg ledstop = 1 set ledastcreg ledcntreg ledenable = 1 leds blink (auto stop) led blinking time setting x ledhtsreg sets led lighting time. x ledltsreg sets led off time. x ledastcreg sets number of leds blinking. caution setting these registers to 0 is prohibited because it may cause undefined operation. led auto-stop setting x ledstop sets the led blink auto-stop function to enable. this setting terminates led blinking automatically after blinking time set above has elapsed. led blinking start x ledenable starts led blinking. leds blink auto stop counter = 0? yes no ledenable = 0 ledstop = 0 ledint = 1 led blinking termination x ledenable = 0 terminates led blinking. led blinking x supervising the auto-stop counter led blinking terminates when the auto-stop counter reaches 0. caution setting the ledenable or ledstop bit to 0 during blinking is prohibited because it may cause undefined operation. led blinking terminate interrupt generation x ledint = 1 generates an interrupt request to the icu. leds off leds blinking start condition 460 [memo] 461 chapter 24 siu (serial interface unit) this chapter describes the sius operations and register settings. 24.1 general the siu is a serial interface that conforms to the rs-232-c communication standard and is equipped with two one-channel interfaces, one for transmission and one for reception. this unit is functionally compatible with the ns16550. 24.2 register set the siu registers are listed below. table 24-1. siu registers address lcr[7] r/w register symbols function r siurb receiver buffer register (read) 0 w siuth transmitter holding register (write) 0x0c00 0000 1 r/w siudll divisor latch (least significant byte) 0 r/w siuie interrupt enable 0x0c00 0001 1 r/w siudlm divisor latch (most significant byte) r siuiid interrupt identification register (read) 0x0c00 0002 e w siufc fifo control register (write) 0x0c00 0003 e r/w siulc line control register 0x0c00 0004 e r/w siumc modem control register 0x0c00 0005 e r/w siuls line status register 0x0c00 0006 e r/w siums modem status register 0x0c00 0007 e r/w siusc scratch register 0x0c00 0008 e r/w siuirsel siu/fir irda selector remark lcr[7] is the bit 7 of siulc register. chapter 24 siu (serial interface unit) 462 24.2.1 siurb (0x0c00 0000: lcr[7] = 0, read) bitd7d6d5d4d3d2d1d0 name rxd[7] rxd[6] rxd[5] rxd[4] rxd[3] rxd[2] rxd[1] rxd[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7..0] rxd[7..0] serial receive data this register stores receive data used in serial communications. to access this register, set lcr[7] (bit 7 of siulc register) to 0. 24.2.2 siuth (0x0c00 0000: lcr[7] = 0, write) bitd7d6d5d4d3d2d1d0 name txd[7] txd[6] txd[5] txd[4] txd[3] txd[2] txd[1] txd[0] r/w wwwwwwww rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7..0] txd[7..0] serial transmit data this register stores transmit data used in serial communications. to access this register, set lcr[7] (bit 7 of siulc register) to 0. chapter 24 siu (serial interface unit) 463 24.2.3 siudll (0x0c00 0000: lcr[7] = 1) bitd7d6d5d4d3d2d1d0 name dll[7] dll[6] dll[5] dll[4] dll[3] dll[2] dll[1] dll[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7..0] dll[7..0] baud rate generator divisor (low-order byte) this register is used to set the divisor (division rate) for the baud rate generator. the data in this register and the data in siudlm register on the high-order side are together handled as 16-bit data. to access this register, set lcr[7] (bit 7 of siulc register) to 1. chapter 24 siu (serial interface unit) 464 24.2.4 siuie (0x0c00 0001: lcr[7] = 0) bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved ie[3] ie[2] ie[1] ie[0] r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7..4] reserved write 0 when writing. 0 is returned after read. d[3] ie[3] modem status interrupt 1 : interrupt enable 0 : interrupt prohibit d[2] ie[2] receive status interrupt 1 : interrupt enable 0 : interrupt prohibit d[1] ie[1] transmitter holding register empty interrupt 1 : interrupt enable 0 : interrupt prohibit d[0] ie[0] receive data interrupt or timeout interrupt in fifo mode 1 : interrupt enable 0 : interrupt prohibit this register is used to specify interrupt enable/prohibit settings for the five types of interrupt used by the siu. these interrupts can be used to make the corresponding interrupt output signal (intr) active. overall use of interrupt functions can be halted by setting bit 0 to bit 3 of the interrupt enable register (ier) to zero. if one or more of the bits from bit 0 to bit 3 has a value of 1, the corresponding interrupt is enabled. when interrupts are prohibited, pending is not displayed in the iir[0] bit even when the interrupt condition has been met and intr output does not become active. other functions in the system are not affected even though interrupts are prohibited and the settings in the line status register and modem status register are valid. to access this register, set lcr[7] (bit 7 of siulc register) to 0. chapter 24 siu (serial interface unit) 465 24.2.5 siudlm (0x0c00 0001: lcr[7] = 1) bitd7d6d5d4d3d2d1d0 name dlm[7] dlm[6] dlm[5] dlm[4] dlm[3] dlm[2] dlm[1] dlm[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7..0] dlm[7..0] baud rate generator divisor (high-order byte) this register is used to set the divisor (division rate) for the baud rate generator. the data in this register and the data in siudll register on the low-order side are together handled as 16-bit data. to access this register, set lcr[7] (bit 7 of siulc register) to 1. chapter 24 siu (serial interface unit) 466 table 24-2. correspondence between baud rates and divisors baud rate divisor 50 23040 75 15360 110 10473 134.5 8565 150 7680 300 3840 600 1920 1200 920 1800 640 2000 573 2400 480 3600 320 4800 240 7200 160 9600 120 19200 60 38400 30 56000 21 128000 9 144000 8 192000 6 230400 5 288000 4 384000 3 576000 2 1152000 1 chapter 24 siu (serial interface unit) 467 24.2.6 siuiid (0x0c00 0002: read) bitd7d6d5d4d3d2d1d0 name iir[7] iir[6] reserved reserved iir[3] iir[2] iir[1] iir[0] r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 1 other resets 0 0 0 0 0 0 0 1 bit name function d[7..6] iir[7..6] becomes 11 when fcr0 = 1 d[5..4] reserved write 0 when writing. 0 is returned after read. d[3] iir[3] pending character timeout interrupt (in fifo mode) 1 : pending interrupt 0 : no pending interrupt d[2..1] iir[2..1] indicates the priority level of pending interrupt. see the following table. d[0] iir[0] pending interrupts 1 : no pending interrupt 0 : pending interrupt this register indicates priority levels for interrupts and existence of pending interrupt. from highest to lowest priority, these interrupts are receive line status, receive data ready, character timeout, transmit holding register empty, and modem status. the contents of iir[3] bit is valid only in fifo mode, and it is always 0 in 16550 mode. iir[2] bit becomes 1 when iir[3] bit is set to 1. chapter 24 siu (serial interface unit) 468 table 24-3. interrupt function siuiid register interrupt set/reset function bit3 note bit2 bit1 priority level interrupt type interrupt source interrupt reset control 0 1 1 highest (1st) receive line status overrun error, parity error, framing error, or break interrupt read line status register 0 1 0 2nd receive data ready receive data exists or has reached the trigger level. read the receive buffer register or lower trigger level via fifo. 1 1 0 2nd character timeout during the time period for the four most recent characters, not one character has been read from the receive fifo nor has a character been input to the receive fifo. during this period, at least one character has been held in the receive fifo. read receive buffer register 0 0 1 3rd transmit holding register empty transmit register is empty read iir (if it is the interrupt source) or write to transmit holding register 0 0 0 4th modem status cts#, dsr#, or dcd# read modem status register note fifo mode only chapter 24 siu (serial interface unit) 469 24.2.7 siufc (0x0c00 0002: write) bitd7d6d5d4d3d2d1d0 name fcr[7] fcr[6] reserved reserved fcr[3] fcr[2] fcr[1] fcr[0] r/w w w r r w w w w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7..6] fcr[7..6] receive fifo trigger level 11 : 14 bytes 10 : 08 bytes 01 : 04 bytes 00 : 00 byte d[5..4] reserved write 0 when writing. 0 is returned after read. d[3] fcr[3] switch between 16550 mode and fifo mode 1 : from 16550 mode to fifo mode 0 : from fifo mode to 16550 mode d[2] fcr[2] transmit fifo clear/counter clear. cleared to 0 when 1 is written. 1 : fifo clear/counter clear 0 : normal d[1] fcr[1] receive fifo clear/counter clear. cleared to 0 when 1 is written. 1 : fifo clear/counter clear 0 : normal d[0] fcr[0] receive/transmit fifo enable 1 : enable 0 : disable this register is used to control the fifos. chapter 24 siu (serial interface unit) 470 z fifo interrupt modes when receive fifo is enabled and receive interrupts are enabled, receive interrupts can occur as described below. 1. when the fifo is reached to the specified trigger level, a receive data ready interrupt occurs to inform the cpu. this interrupt is cleared when the fifo goes below the trigger level. 2. when the fifo is reached to the specified trigger level, the siuiid register indicates a receive data ready interrupt. as with the interrupt above, this interrupt is cleared when the fifo goes below the trigger level. 3. receive line status interrupts are assigned a higher priority level than are receive data ready interrupts. 4. when characters are transferred from the shift register to the receive fifo, 1 is set to the lsr0 bit. the value of this bit returns to 0 when the fifo becomes empty. when receive fifo is use-enabled and receive interrupts are enabled, receive fifo timeout interrupts can occur as described below. 1. the following are conditions under which fifo timeout interrupts occur. ? at least one character is being stored in the fifo. ? the time required for sending four characters has elapsed since the serial reception of the last character (includes the time for two stop bits in cases where a stop bit has been specified). ? the time required for sending four characters has elapsed since the cpu last accessed the fifo. the time between receiving the last character and issuing a timeout interrupt is a maximum of 160 ms when operating at 300 baud and receiving 12-bit data. 2. the transfer time for a character is calculated based on the baud rate clock for reception (internal) input as clock signals (which is why the elapsed time is in proportion to the baud rate). 3. once a timeout interrupt has occurred, the timeout interrupt is cleared and the timer is reset as soon as the cpu reads one character from the receive fifo. 4. if no timeout interrupt has occurred, the timer is reset when a new character is received or when the cpu reads the receive fifo. chapter 24 siu (serial interface unit) 471 when transmit fifo is use-enabled and transmit interrupts are enabled, transmit interrupts can occur as described below. 1. when the transmit fifo becomes empty, a transmit holding register empty interrupt occurs. this interrupt is cleared when a character is written to the transmit holding register (from one to 16 characters can be written to the transmit fifo during servicing of this interrupt), or when the siuiid (interrupt id register) is read. 2. if there are not at least two bytes of character data in the transmit fifo between one time when lsr[5] = 1 (transmit fifo is empty) and the next time when lsr[5] = 1, empty transmit fifo status is reported to the iir after a delay period calculated as the time for one character e the time for the last stop bit(s). when transmit interrupts are enabled, the first transmit interrupt that occurs after the fcr0 (fifo enable bit) is overwritten is indicated immediately. the priority level of the character timeout interrupt and receive fifo trigger level interrupt is the same as that of the receive data ready interrupt. the priority level of the transmit fifo empty interrupt is the same as that of the transmit holding register empty interrupt. z fifo polling mode when fcr0 = 1 (fifo is enabled), if the value of any or all of the interrupt enable register (siuie) bits 3 to 0 becomes 0, the siu enters fifo polling mode. because the transmit block and receive block are controlled separately, polling mode can be set for either or both blocks. when in this mode, the status of the transmit block and/or receive block can be checked by reading the line status register (siuls) via a user program. when in fifo polling mode, there is no notification when the trigger level is reached or when a timeout occurs, but the receive fifo and transmit fifo can still store characters as they normally do. chapter 24 siu (serial interface unit) 472 24.2.8 siulc (0x0c00 0003) bitd7d6d5d4d3d2d1d0 name lcr[7] lcr[6] lcr[5] lcr[4] lcr[3] lcr[2] lcr[1] lcr[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7] lcr[7] divisor latch access bit specification 1 : divisor latch access 0 : receive buffer, transmit holding register, interrupt enable register d[6] lcr[6] break control 1 : set break 0 : clear break d[5] lcr[5] parity fixing 1 : fixed parity 0 : parity not fixed d[4] lcr[4] parity setting 1 : set one bit as odd bit 0 : set one bit as even bit d[3] lcr[3] parity enable 1 : create parity (during transmission) or check parity (during reception) 0 : no parity (during transmission) or no checking (during reception) d[2] lcr[2] stop bit specification 1 : 1.5 bits (character length is 5 bits) 2 bits (character length is 6, 7, or 8 bits) 0 : 1 bit d[1..0] lcr[1..0] specifies the length of one character (number of bits) 11 : 8 bits 10 : 7 bits 01 : 6 bits 00 : 5 bits this register is used to specify the format for asynchronous data communication and exchange and to set the divisor latch access bit. the setting of bit 5 becomes valid according to settings in bits 4 and 3. bit 6 is used to send the break status to the receive sides uart. when bit6 = 1, the serial output (txd) is forcibly set to the spacing (0) state. chapter 24 siu (serial interface unit) 473 24.2.9 siumc (0x0c00 0004) bitd7d6d5d4d3d2d1d0 name reserved reserved reserved mcr[4] mcr[3] mcr[2] mcr[1] mcr[0] r/w r r r r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7..5] reserved write 0 when writing. 0 is returned after read. d[4] mcr[4] for diagnostic testing (local loopback) 1 : enable use of local loopback 0 : disable use of local loopback d[3] mcr[3] out2 signal (internal) specification 1 : output the low-level signal 0 : output the high-level signal d[2] mcr[2] out1 signal (internal) specification 1 : output the low-level signal 0 : output the high-level signal d[1] mcr[1] rts# output control 1 : output the low-level signal 0 : output the high-level signal d[0] mcr[0] dtr# output control 1 : output the low-level signal 0 : output the high-level signal this register is used for interface control with a modem or data set (or a peripheral device that emulates a modem). the settings of bit 3 and bit 2 become valid only when bit 4 is set to 1 (enable use of local loopback). z local loopback the local loopback can be used to test the transmit/receive data path in the siu. the following operation is executed when bit 4 value = 1. the transmit blocks serial output (txd) enters the marking state (logical 1) and the serial input (rxd) to the receive block is cut off. the transmit shift registers output is looped back to the receive shift registers input. the four modem control inputs (dsr#, cts#, ri (internal), and dcd#) are cut off and the four modem control outputs (dtr#, rts#, out1 (internal), and out2 (internal)) are internally connected to the corresponding modem control inputs. the modem control output pins are forcibly set as inactive (high level). during this kind of loopback mode, transmitted data can be immediately and directly received. this function can be used to check on the transmit/receive data bus within the siu. when in loopback mode, both transmission and receive interrupts can be used. the interrupt sources are external sources in relation to the transmit and receive blocks. although modem control interrupts can be used, the low-order four bits of the modem control register can be used instead of the four modem control inputs as interrupt sources. as usual, each interrupt is controlled by an interrupt enable register. chapter 24 siu (serial interface unit) 474 24.2.10 siuls (0x0c00 0005) bitd7d6d5d4d3d2d1d0 name lsr[7] lsr[6] lsr[5] lsr[4] lsr[3] lsr[2] lsr[1] lsr[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 1 1 0 0 0 0 0 other resets 0 1 1 0 0 0 0 0 bit name function d[7] lsr[7] indicates error detection (in fifo mode) 1 : parity error, framing error, or break is detected 0 : normal d[6] lsr[6] transmit block empty 1 : no data in transmit holding register or transmit shift register no data in transmit fifo (during fifo mode) 0 : data exists in transmit holding register or transmit shift register data exists in transmit fifo (during fifo mode) d[5] lsr[5] transmit holding register empty 1 : character is transferred to transmit shift register (during 16550 mode) transmit fifo is empty (during fifo mode) 0 : character is stored in transmit holding register (during 16550 mode) transmit data exists in transmit fifo (during fifo mode) d[4] lsr[4] break interrupt 1 : break interrupt detected 0 : normal d[3] lsr[3] framing error 1 : framing error detected 0 : normal d[2] lsr[2] parity error 1 : parity error detected 0 : normal d[1] lsr[1] overrun error 1 : overwrite receive data 0 : normal d[0] lsr[0] receive data ready 1 : receive data exists in fifo 0 : no receive data in fifo the cpu uses this register to get information related to data transfers. lsr[7] bit is valid only in fifo mode, and it indicates always 0 in 16550 mode. chapter 24 siu (serial interface unit) 475 bit4: break interrupt the value of bit 4 becomes 1 when the spacing mode (logical 0) is held longer than the time required for transmission of one word of receive data input (start bit + data bits + parity bit + stop bit). this bit value returns 0 when the cpu reads the contents of the line status register. when in fifo mode, if a break interrupt is detected for one character in the fifo, the character is regarded as an error character and the cpu is notified of a break interrupt when that character reaches the highest position in the fifo. when a break occurs, one zero character is sent to the fifo. the rxd enters marking mode, and when the next valid start bit is received, the next character can be transmitted. bit3: framing error this indicates that the received character data did not include a correct stop bit. the value of this becomes 1 when a zero (spacing level) stop bit is detected following the final data bit or parity bit. this bit value returns to 0 when the cpu reads the contents of the line status register. when in fifo mode, if a framing error is detected for one character in the fifo, the character is regarded as an error character and the cpu is notified of a framing error when that character reaches the highest position in the fifo. when a framing error occurs, the siu prepares for further synchronization. the next start bit is assumed to be the cause of the framing error and further data is not accepted until the next start bit has been sampled twice. bit2: parity error this error indicates that the received character data does not satisfy the even-parity or odd-parity setting specified by the even parity select bit. the value of this becomes 1 when a parity error is detected. this bit value returns to 0 when the cpu reads the contents of the line status register. when in fifo mode, if a parity error is detected for one character within the fifo, the character is regarded as an error character and the cpu is notified of a parity error when that character reaches the highest position in the fifo. bit1: overrun error (oe) when the cpu transfers the next character to the receive buffer register before it reads the receive buffer register, the characters existing in that register are deleted. the value of this bit becomes 1 when overrun status is detected and returns to 0 when the cpu reads the contents of the line status register. when in fifo mode, if the data exceeds the trigger level as it continues to be transferred to the fifo, even after the fifo becomes full an overrun error will not occur until all characters are stored in the shift register. the cpu is notified as soon as an overrun error occurs. the characters in the shift register are overwritten and are not transferred to the fifo. chapter 24 siu (serial interface unit) 476 24.2.11 siums (0x0c00 0006) bitd7d6d5d4d3d2d1d0 name msr[7] msr[6] msr[5] msr[4] msr[3] msr[2] msr[1] msr[0] r/w r r r r r/w r/w r/w r/w rtcrst undefined undefined undefined undefined 0 0 0 0 other resets undefined undefined undefined undefined 0 0 0 0 bit name function d[7] msr[7] complement of dcd# signal 1 : high level 0 : low level d[6] msr[6] complement of ri signal (internal) 1 : high level 0 : low level d[5] msr[5] complement of dsr# input 1 : high level 0 : low level d[4] msr[4] complement of cts# input 1 : high level 0 : low level d[3] msr[3] dcd# signal change 1 : change in dcd# signal 0 : no change d[2] msr[2] ri signal (internal) change 1 : change in ri signal (internal) 0 : no change d[1] msr[1] dsr# signal change 1 : change in dsr# signal 0 : no change d[0] msr[0] cts# signal change 1 : change in cts# signal 0 : no change this register indicates the current status of various control signals that are input to the cpu from a modem or other peripheral device. msr[3..0] bits are cleared to 0 when they are read. chapter 24 siu (serial interface unit) 477 24.2.12 siusc (0x0c00 0007) bitd7d6d5d4d3d2d1d0 name scr[7] scr[6] scr[5] scr[4] scr[3] scr[2] scr[1] scr[0] r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7..0] scr[7..0] can be freely applied by user this register is a readable/writable 8-bit register. it does not affect control of the siu. chapter 24 siu (serial interface unit) 478 24.2.13 siuirsel (0x0c00 0008) bitd7d6d5d4d3d2d1d0 name reserved reserved tmicmode tmictx irmsel[1] irmsel[0] irusesel sirsel r/w r r r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[7..6] reserved write 0 when writing. 0 is returned after read. d[5] tmicmode specifies the mode of the emitter or receptor module. d[4] tmictx specifies the communication rate. 1 : communication at 4 mbps 0 : communication at 1.15 mbps or less d[3..2] irmsel[1..0] sets the type of emitter/receptor module to be used 11 : rfu 10 : hp model (hsdl-1100 is assumed) 01 : temic model (tfds6000 is assumed) 00 : sharp model (ry5fd01d is assumed) d[1] irusesel selects siu or fir for use with irda emitter/receptor module 1 : fir uses irda module 0 : siu uses irda module d[0] sirsel selects whether the siu uses the irda module or the rs-232-c pins during communications 1 : use irda module 0 : use rs-232-c interface this register is used to set the irda module settings, irda module access privileges, and the sius communication format (irda or serial). the settings of tmicmode and tmictx bits are valid only when irmsel[1..0] bits are set to 01 (temic model). chapter 24 siu (serial interface unit) 479 the figure below shows the connection examples between the v r 4102 and irda modules. figure 24-1. connection example between the v r 4102 and irda module rxda irdin txd irdout rxdb firdin#/sel v r 4102 irda module (a) hp product rxd irdin txd irdout sel firdin#/sel v r 4102 irda module (b) temic product rxd irdin txd irdout firdin#/sel v r 4102 irda module (c) sharp product nc remark nc: no connection 480 [memo] 481 chapter 25 hsp (modem interface unit) this chapter describes the hsp units operations and register settings. 25.1 general the core of the hsp unit uses pctels pct288i chip. the main functions of the pct288i is as follows. <1> codec device control and serial l parallel conversion of the codec transmit/receive data <2> control of relay lines, hook lines, and other signal lines in daa (data access arrangement) block block diagrams of hsp unit and an example of connection between the v r 4102 and external agents are shown below. chapter 25 hsp (modem interface unit) 482 figure 25-1. hsp unit block diagram oclk0 oclk1 imclk ireset iaen iiowcb iiorcb oiocs16b oiochrdyb iaddr[11:0] ibd[15:0] obd[15:0] oe oirq2 oirq3 oirq4 oirq5 oirq10 oirq11 oirq12 oirq15 ocrystl icrystal iafesel[1] iafesel[0] ibyte icasin islaveb ihwpdnb iring ilc-sense ilv-sense in[4:0] opd ooff-hook ocid-relay oaferstb omute out[2] out[1] out[0] ooff-hookb isclk ifsi isdi ifsx ofsx osdo ocasout isa bus interface parallel i/o interface codec serial i/o interrupt control block fs telecon hc0 hspmclk seclk_hsp ck dq q_b iring ilcsense opd# offhook aferst# mute hspsclk sdi sdo testhsp bsc rst_gab ireset_before ibyte_before iafesel_before0 ihspout_before[15:0] hsp_intr hspinitreg hsp_address decoder iiowb iiorb iadd[4:0] cshspb hspinitreg i_tclk idin[15:0] ihspout[15:0] iaddr288_before[4:0] decode[4:0] decoder to level interrupt figure 25-2. circuit configuration block diagram examples v r 4102 (hsp) codec daa line speaker iring ilcsense offhook telcon sdo hspmclk aferst# hc0 fs sdi hspsclk txan txap rxa mute 3 4 chapter 25 hsp (modem interface unit) 483 25.2 register set the hsp registers are listed below. the data registers can be accessed as the control registers by specifying the index number and then reading from or writing to. all registers other than the hspinit register are original to the pct288i. table 25-1. hsp registers address r/w register symbols name 0x0c00 0020 r/w hspinit hsp initialize register 0x0c00 0022 r/w hspdata[7:0] hsp data register [7:0] 0x0c00 0023 r/w hspdata[15:8] hsp data register [15:8] 0x0c00 0024 w hspindex hsp index register 0x0c00 0028 r hspid[7:0] hsp id register 0x0c00 0029 r hsppcs[7:0] hsp i/o address program confirmation register 0x0c00 0029 w hsppctel[7:0] hsp signature checking port chapter 25 hsp (modem interface unit) 484 25.2.1 hsp initialize register (1) hspinit (0x0c00 0020) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved opd afesel byte bsc hsprst r/w r r r r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:5] reserved write 0 when writing. 0 is returned after read. d[4] opd power-down codec (indicates opd# pins state) 1 : high level 0 : low level d[3] afesel codec interface mode switch 1 : st7546, stlc7546(sgs), t7525(at) 0 : tlc320c44, tlc320ac01/02(ti) d[2] byte hsp data bus width setting 1 : 8 bits 0 : 16 bits d[1] bsc codec interface control 1 : normal 0 : initial value d[0] hsprst hsp unit reset (same as hardware reset) 1 : reset 0 : do not reset this register is used to control the hsp. bsc bit is used to control the codec interface. this bit must be set to 1 when using the hsp. the hardware reset and the reset by the hsprst bit result the same function. chapter 25 hsp (modem interface unit) 485 25.2.2 hsp data register, hsp index register hspdata[15..0] is a 16-bit data port. this register can be accessed as control registers according to the hspindex[15..0] setting. hspindex[15..0] is a write-only index register. the role of the data register changes according to the values set to this register. the correspondence between index numbers and registers is shown below. table 25-2. control register definitions index write read higher byte lower byte higher byte lower byte 0 hsptxdata[15..8] hsptxdata[7..0] hsprxdata[15..8] hsprxdata[7..0] 1 hspcntl[9..8] hspcntl[7..0] hspsts[15..8] hspsts[7..0] 2 reserved hspextout[7..0] hspid[7..0] hspextin[7..0] 3 hsptoc[3..0] hspmclk1[4..0] hsperrcnt[11..8] h sperrcnt[7..0] 4 reserved hspffsz[6..0] reserved 5 to 15 reserved reserved 16 to 255 setting prohibited setting prohibited described below are control registers. (1) hsptxdata (0x0c00 0022: index 0, write) bit d15 d14 d13 d12 d11 d10 d9 d8 name txdata[15] txdata[14] txdata[13] txdata[12] txdata[11] txdata[10] txdata[9] txdata[8] r/w wwwwwwww rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bitd7d6d5d4d3d2d1d0 name txdata[7] txdata[6] txdata[5] txdata[4] txdata[3] txdata[2] txdata[1] txdata[0] r/w wwwwwwww rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function d[15:0] txdata[15:0] transmit data chapter 25 hsp (modem interface unit) 486 (2) hspcntl (0x0c00 0022: index 1, write) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w wwwwwwww rtcrst 0 0 undefined undefined undefined undefined undefined undefined other resets 0 0 undefined undefined undefined undefined undefined undefined bitd7d6d5d4d3d2d1d0 name ntorst enirq start reserved entx irqs2 irqs1 irqs0 r/w wwwwwwww rtcrst 00000000 other resets 00000000 bit name function d[15:8] reserved write 0 when writing. d[7] ntorst disable timeout reset when this bit is 0, it enables a timeout to occur when a specified number of errors have been counted, at which point the hsp resets itself. 1 : disable 0 : enable d[6] enirq interrupt enable 1 : enable 0 : disable d[5] start rx/tx fifo pointer initialization when this bit is set to 1, the rx/tx fifo pointer is set to its initial position. 1 : initialize (at rising edge) 0 : status hold d[4] reserved write 0 when writing. d[3] entx transfer enable 1 : enable 0 : disable d[2:0] irqs[2:0] interrupt signal select. however, irq signal is always selected whatever value is set to these bits. caution if 1 is set to entx bit, the only way to stop the operation is by resetting the hsp unit. chapter 25 hsp (modem interface unit) 487 (3) hspextout (0x0c00 0022: index 2, write) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w wwwwwwww rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bitd7d6d5d4d3d2d1d0 name reserved hc0 telecon reserved mute aferst reserved offhook r/w wwwwwwww rtcrst undefined 0 0 0 0 1 0 0 other resets undefined 0 0 0 0 1 0 0 bit name function d[15:7] reserved write 0 when writing. d[6] hc0 select codec mode this bit is connected to the hc0 pin. 1 : high-level signal output 0 : low-level signal output d[5] telecon hand set relay control this bit is connected to the telecon pin. 1 : high-level signal output 0 : low-level signal output d[4] reserved write 0 when writing. d[3] mute mute speaker this bit is connected to the mute pin. 1 : high-level signal output 0 : low-level signal output d[2] aferst codec reset this bit is connected to the aferst# pin. 1 : high-level signal output 0 : low-level signal output d[1] reserved write 0 when writing. d[0] offhook off hook relay control this bit is connected to the offhook pin. 1 : high-level signal output 0 : low-level signal output this register is used to set output values of various signals when the index number is 2. chapter 25 hsp (modem interface unit) 488 (4) hsptoc and hspmclkd (0x0c00 0022: index 3, write) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved toc3 toc2 toc1 toc0 r/w wwwwwwww rtcrst undefined undefined undefined undefined 0 0 0 0 other resets undefined undefined undefined undefined 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved mclkd4 mclkd3 mclkd2 mclkd1 mclkd0 r/w wwwwwwww rtcrst undefined undefined undefined 1 1 1 1 0 other resets undefined undefined undefined 1 1 1 1 0 bit name function d[15:12] reserved write 0 when writing. d[11:8] toc[3:0] high-order 4 bits of timeout count d[7:5] reserved write 0 when writing. d[4:0] mclkd[4:0] hspmclk divisor to clock input hspmclk frequency = 18.432 mhz / (mclkd[4:0] + 2) the upper byte of this register sets the timeout counter value and lower byte sets the hspmclks division ratio when the index number is 3. toc[3:0] is used to set the high-order four bits of the final count of the timeout counter. the timeout counter is a 12-bit counter and is incremented once for each interrupt signal that is not serviced. the low-order 8 bits are automatically set to 0 when toc[3:0] is set. when the specified timeout count value is reached, to bit of hspsts register is set to 1. the user is responsible for resetting the hsp core to prevent a system hang-up. mclkd[4:0] is used to set the division ratio when the 18.432-mhz clock supplied to hspmclk pin can be output using a programmable division ratio. if mclkd[4:0] is 0, there is no clock division and the 18.432-mhz clock is output. note that an even number must be set to mclkd[4:0]. chapter 25 hsp (modem interface unit) 489 (5) hspffsz (0x0c00 0022: index 4, write) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w wwwwwwww rtcrst undefined undefined undefined 0 0 0 0 0 other resets undefined undefined undefined 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved ffsz5 ffsz4 ffsz3 ffsz2 ffsz1 ffsz0 r/w wwwwwwww rtcrst undefined undefined 1 0 0 0 0 0 other resets undefined undefined 1 0 0 0 0 0 bit name function d[15:6] reserved write 0 when writing. d[5:0] ffsz[5:0] fifo size control when the index number is 4, this register is used to set the transmit/receive buffer size, and can be set up to 32 (0x20). if buffer-full interrupt is enabled, an interrupt will occur when the data in the transmit/receive buffer reaches to the size set in this register. chapter 25 hsp (modem interface unit) 490 (6) hsprxdata (0x0c00 0022: index 0, read) bit d15 d14 d13 d12 d11 d10 d9 d8 name rxdata[15] rxdata[14] rxdata[13] rxdata[12] rxdata[11] rxdata[10] rxdata[9] rxdata[8] r/w rrrrrrrr rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bitd7d6d5d4d3d2d1d0 name rxdata[7] rxdata[6] rxdata[5] rxdata[4] rxdata[3] rxdata[2] rxdata[1] rxdata[0] r/w rrrrrrrr rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function d[15:0] rxdata[15:0] receive data from the receive fifo this register is used to store the receive data from the receive fifo when the index number is 0. chapter 25 hsp (modem interface unit) 491 (7) hspsts (0x0c00 0022: index 1, read) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 undefined undefined undefined other resets 0 0 0 0 0 undefined undefined undefined bitd7d6d5d4d3d2d1d0 name afesel1 afesel0 ibyte to cfgcp irqs rxovrun tx udrun r/w rrrrrrrr rtcrst undefined undefined undefined 0 0 0 0 0 other resets undefined undefined undefined 0 0 0 0 0 bit name function d[15:8] reserved 0 is returned after read. d[7:6] afesel[1:0] indicates the afesel[1:0] signal (internal) state d[5] ibyte indicates the byte signal (internal) state d[4] to error-related timeout 1 : timeout occurred 0 : no timeout d[3] cfgcp codec configuration complete 1 : complete 0 : not complete d[2] irqs pending interrupt exists 1 : exists 0 : no pending interrupts d[1] rxovrun receive overrun occurred 1 : occurred 0 : no receive overruns d[0] txudrun transmit underrun occurred 1 : occurred 0 : no transmit overruns this register is used to indicate the status in communication when the index number is 1. to bit is set (to 1) when the timeout counter reaches the value specified by the toc bit of hsptoc register. cfgcp bit indicates whether or not codec initialization has been completed. actually, this bit is set (to 1) when the start bit of hspcntl register has been set as active to reset the fifo pointer and then 9-word data has been transmitted (1 word = 16 bits). irqs bit indicates whether or not any pending interrupt exists. when an interrupt request from hsp to the cpu core is in pending, the request is cleared after this register is read. irqs, rxovrun, txudrun bits are cleared (to 0) when read. chapter 25 hsp (modem interface unit) 492 (8) hspid and hspextin (0x0c00 0022: index 2, read) bit d15 d14 d13 d12 d11 d10 d9 d8 name id7 id6 id5 id4 id3 id2 id1 id0 r/w rrrrrrrr rtcrst 0 0 0 1 0 0 0 0 other resets 0 0 0 1 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved ilcs iring r/w rrrrrrrr rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function d[15:8] id[7:0] indicates hsp units id and revision number d[7:2] reserved 0 is returned after read. d[1] ilcs ilcsense input pin state indication d[0] iring iring input pin state indication the upper byte of this register is used to indicate the id of hsp, and the lower byte is used to indicate the status of the hsp input signals. id[7:0] is divided into two parts. the high-order 4 bits id[7:4] indicate the id number of hsp, and the low-order 4 bits id[3:0] indicate the revision number of hsp. chapter 25 hsp (modem interface unit) 493 (9) hsperrcnt (0x0c00 0022: index 3, read) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved errcnt11 errcnt10 errcnt9 errcnt8 r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name errcnt7 errcnt6 errcnt5 errcnt4 errcnt3 errcnt2 errcnt1 errcnt0 r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets 0 0 0 0 0 0 0 0 bit name function d[15:12] reserved 0 is returned after read. d[11:0] errcnt[11:0] error count this register is used to indicate the number of errors when the index number is 3. this register indicates the number of overrun or underrun errors that have occurred. this is used for synchronizing software and hardware. 25.2.3 hsp id register, hsp i/o address program confirmation register the specific values are displayed to hspid[7:0] and hsppcs[7:0] registers following normal access of hsppctel register. 25.2.4 hsp signature checking port hsppctel[7:0] register must be accessed when to start using hsp unit. 0xa5 can be read from the hsppcs register by writing a certain value. other registers cannot be accessed unless this processing is executed. it must be executed during initialization. chapter 25 hsp (modem interface unit) 494 25.3 power control power control of the codec and afe can be performed using the opd# pin and the bsc bit (hspinit). the following is an example of a control method using these units. figure 25-3. block diagram of hsp interface power control v r 4102 voltage control unit l: on h: off codec afe telephone line opd# pin bsc bit hsp interface other than opd# (1) after rtc reset item opd# pin bsc bit hsp bus state v r 4102 power codec/afe power 1 when initialized l 0 note on off 2 during power-on of codec or afe h 0 note on on 3 when hsp buss gate is set to on h 1 normal on on 4 software modem control h 1 normal on on note refer to 2.3 pin status upon a specific state . (2) during power-down (v r 4102: fullspeed/standby/suspend mode) item opd# pin bsc bit hsp bus state v r 4102 power codec/afe power 1 operation complete h 1 normal on on 2 when hsp buss gate is set to off h 0 note on on 3 when codec or afe power is set to off l0 note on off 4 if necessary, execute standby/ suspend command l0 note on off note refer to 2.3 pin status upon a specific state . chapter 25 hsp (modem interface unit) 495 (3) during recovery from power-down (v r 4102: fullspeed/standby/suspend mode) item opd# pin bsc bit hsp bus state v r 4102 power codec/afe power 1 power down status l 0 note on off 2 during power-on of codec or afe h 0 note on on 3 when hsp buss gate is set to on h 1 normal on on 4 use hsp unit h 1 normal on on note refer to 2.3 pin status upon a specific state . (4) when changing to hibernate mode (the following processing must occur before entering hibernate mode) item opd# pin bsc bit hsp bus state v r 4102 power codec/afe power 1 operation complete h 1 normal on on 2 when hsp buss gate is set to off h 0 note on on 3 when codec or afe power is set to off l0 note on off 4 execute hibernate command l 0 note on off note refer to 2.3 pin status upon a specific state . (5) during recovery from hibernate mode to use hsp unit item opd# pin bsc bit hsp bus state v r 4102 power codec/afe power 1 during hibernate mode l 0 note on off 2 during power-on of codec or afe h 0 note on on 3 when hsp buss gate is set to on h 1 normal on on 4 use hsp unit h 1 normal on on note refer to 2.3 pin status upon a specific state . 496 [memo] 497 chapter 26 fir (fast irda interface unit) the fir operation and register settings are described below. 26.1 general this unit supports the irda 1.1 high-speed infrared communication physical layer standard. supported fir (fast sir) transfer rates include 0.576 mbps, 1.152 mbps, and 4 mbps. sir (up to 115.2 kbps) is not supported. chapter 26 fir (fast irda interface unit) 498 26.2 register set the fir registers are listed below. table 26-1. fir registers address r/w register symbols function 0x0c00 0040 r/w frstr fir reset register 0x0c00 0042 r/w dpintr dma page interrupt register 0x0c00 0044 r/w dpcntr dma control register 0x0c00 0050 w tdr transmit data register 0x0c00 0052 r rdr receive data register 0x0c00 0054 r/w imr interrupt mask register 0x0c00 0056 r/w fsr fifo setup register 0x0c00 0058 r/w irsr1 infrared setup register 1 0x0c00 005c r/w crcsr crc setup register 0x0c00 005e r/w fircr fir control register 0x0c00 0060 r/w mircr mir control register 0x0c00 0062 r/w dmacr dma control register 0x0c00 0064 r/w dmaer dma enable register 0x0c00 0066 r txir transmit indication register 0x0c00 0068 r rxir receive indication register 0x0c00 006a r ifr interrupt flag register 0x0c00 006c r rxsts receive status register 0x0c00 006e r/w txfl transmit frame length 0x0c00 0070 r/w mrxf maximum receive frame length 0x0c00 0074 r rxfl receive frame length register these registers are described in detail below. chapter 26 fir (fast irda interface unit) 499 26.2.1 frstr (0x0c00 0040) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved frst r/w rrrrrrrr/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d1 reserved write 0 when writing. 0 is returned after a read. d0 frst fir reset. set 0 when releasing reset. 0: normal 1: reset chapter 26 fir (fast irda interface unit) 500 26.2.2 dpintr (0x0c00 0042) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved fdpint5 fdpint4 fdpint3 fdpint2 fdpint1 r/w r r r r r/w r/w r/w r/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d5 reserved write 0 when writing. 0 is returned after a read. d4 fdpint5 this bit indicates an fir macro interrupt occurs. cleared to 0 when 1 is written. 0: normal 1: occurred d3 fdpint4 this bit indicates that the dma buffer (receive side) becomes full (2 pages). cleared to 0 when 1 is written. 0: normal 1: occurred (dma request is stopped) caution the last data of the transfer data is not guaranteed. d2 fdpint3 this bit indicates that the dma buffer (transmit side) becomes full (2 pages). cleared to 0 when 1 is written. 0: normal 1: occurred (dma request is stopped) caution the last data of the transfer data is not guaranteed. d1 fdpint2 this bit indicates that the dma buffer (receive side) becomes full (1 page). cleared to 0 when 1 is written. 0: normal 1: occurred (when bit 0 of dpcntr is 1, dma request is stopped) caution when 1-page transfer is set, the last data of the transfer data is not guaranteed. d0 fdpint1 this bit indicates that the dma buffer (transmit side) becomes full (1 page). cleared to 0 when 1 is written. 0: normal 1: occurred (when bit 0 of dpcntr is 1, dma request is stopped) caution when 1-page transfer is set, the last data of the transfer data is not guaranteed. this register is used to indicate the generation of firs dma page interrupt request. chapter 26 fir (fast irda interface unit) 501 26.2.3 dpcntr (0x0c00 0044) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved reserved fdpcnt r/w rrrrrrrr/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d1 reserved write 0 when writing. 0 is returned after a read. d0 fdpcnt dma transfer stopping boundary. 0: 2-page boundary (the last data of the second page is not guaranteed) 1: 1-page boundary (the last data of the first page is not guaranteed) chapter 26 fir (fast irda interface unit) 502 26.2.4 tdr (0x0c00 0050) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w wwwwwwww rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 r/w wwwwwwww rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 to d0 tdr7 to 0 transmit fifo [function] this register is used to store the address to which data is written for the transmit data store fifo. up to 64- or 32-byte data (determined by bit 3 of fsr) is stored to the transmit data store fifo. transmit data fifo is used as follows. (1) write data is written to the transmit data store fifo while the irda is operating. when a write operation is completed, the write pointer of the transmit data store fifo is incremented. however, if data is written when this write pointer is full, it is not incremented. after the data of frame size is written to the txfl register in a status other than the transmit busy status (start enable), if the data written to this register reaches frame size, data transfer starts even if the number of write to this register is short of the threshold. this is start 1. after that, data is always transferred if it reaches frame size, even if it is short of the threshold. this is start 2. (2) read after frame transfer is completed, the sequencer reads the transmit data during the data transfer sequence, and the read pointer is incremented. if read is done while the transmit fifo is empty, a transmit underrun error occurs. this stops the current frame transmission and then starts the abort frame transmission. the following frames scheduled to be transmitted next are not transferred. chapter 26 fir (fast irda interface unit) 503 26.2.5 rdr (0x0c00 0052) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 to d0 rdr7 to 0 receive fifo [function] this register is used to store the address from which data is read for the receive data store fifo. up to 64- or 32-byte data (determined by bit 3 of fsr) is stored to the receive data store fifo. receive data is used as follows. (1) write during a frame data reception, the sequencer writes the receive data during the data transfer sequence, and the write pointer is incremented. if data is written when the unread data in the receive fifo reaches the maximum volume, the receive overrun error occurs and the current frame reception is ended. the write pointer is not incremented. after the receive fifo is cleared, if the number of received frames is less than 7 frames, it is possible to continue frame reception. to receive 8 or more frames, read all the data and frames that are already received from the receive fifo, then clear the receive fifo and restart reception. (2) read data is read from the receive data store fifo while the irda is operating. when a read operation is completed, the read pointer of the receive data store fifo is incremented. however, it is not incremented when the receive fifo is empty. when the number of read frames reaches the receive frame size, an interrupt occurs and bit 7 of the rxsts register is set to 1. [caution] if data is read when the receive fifo is empty (read pointer = write pointer), it may contend with the sequencers write operation. this may cause undefined data. the error generated by read underrun is not reported in this macro. chapter 26 fir (fast irda interface unit) 504 26.2.6 imr (0x0c00 0054) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name imr7 imr6 imr5 imr4 imr3 imr2 imr1 imr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 to d0 imr7 to 0 these bits are used to enable/prohibit interrupt output. this register sets whether or not to inform outside when the interrupt is generated. each bit corresponds to the equivalent ifr register bit. when interrupt output is enabled and corresponding bit is 1, interrupt output is active. imrn interrupt output 0 1 prohibit enable [caution] the ifr register is set irrespective of this registers setting. chapter 26 fir (fast irda interface unit) 505 26.2.7 fsr (0x0c00 0056) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name rx_th1 rx_th0 tx_th1 tx_th0 f_size txf_clr rxf_clr tx_stop r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 and d6 rx_th1, 0 these bits are used to specify the receive fifos threshold. rx_th 1, 0 f_size = 0 f_size = 1 00 01 10 11 1 byte 4 bytes 16 bytes 26 bytes 1 byte 8 bytes 32 bytes 48 bytes d5 and d4 tx_th1, 0 these bits are used to specify the transmit fifos threshold. tx_th 1, 0 f_size = 0 f_size = 1 00 01 10 11 1 byte 8 bytes 16 bytes 26 bytes 1 byte 16 bytes 32 bytes 48 bytes d3 f_size this bit is used to specify the maximum size of transmit/receive fifo. f_size fifo maximum size 0 1 32 bytes 64 bytes d2 txf_clr transmit fifo clear trigger (read value = 0) when this bit is set to 1, the pointers of the transmit data fifo and transmit frame size fifo are initialized. d1 rxf_clr receive fifo clear trigger (read value = 0) when this bit is set to 1, the pointers of the receive data fifo, receive frame size fifo, and receive status fifo are initialized. d0 tx_stop transmission stop trigger (read value = 0) when this bit is set to 1, the current frame transmission is stopped and the abort frame transmission starts. the following frames scheduled to be transmitted next are not transferred. setting 1 to this bit also stops dma operation and generates the dma completion interrupt. this register is used to specify the settings for the transmit/receive fifos. chapter 26 fir (fast irda interface unit) 506 [caution] during transmission/reception, the contents of bits 7 through 3 of the fsr register must not be changed (refresh is possible). the data in the fifo is not cleared by fifo clear. regardless of transmission/reception, after data transfer is completed, set the tx_stop bit and stop the dma operation. when reception, confirm the transfer data command bit and stop the dma operation. chapter 26 fir (fast irda interface unit) 507 26.2.8 irsr1 (0x0c00 0058) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name irda_en reserved reserved reserved reserved reserved irda_md mir_md r/w r/wrrrrrr/wr/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 irda_en this bit is used to control (enable/prohibit) irda macro operation. when this bit is set to 1, peripheral main blocks reset is released and clock supply starts. 0: prohibit 1: enable d6 to d2 reserved write 0 when writing. 0 is returned after a read. d1 and d0 irda_md/ these bits are used to specify the irda/mir mode. mir_md irda_md mir_md operation mode frequency modulation method 0 1 1 1 or 0 0 1 fir mode mir full mode mir half mode 8 mhz 1.152mhz 0.576 mhz 4 ppm bit stream/stuff bit stream/stuff [caution] during transmission/reception, the contents of this register must not be changed (refresh is possible). when the irda_en bit is set, the peripheral main part reset is released and the clock supply starts. pulse output level changes according to operation mode changes. the operation mode should be changed after changing the irda operation to prohibit state (by setting bit (bit 7) to 0). once the mode is changed, be sure to switch bit inversion of i/o data on/off by setting bit 0 of the crcsr register. the output level does not change because output latch is reset. example) sequence of changing operation mode from fir mode to mir full mode clr1 0x7, irsr1 prohibit irda operation set1 0x1, irsr1 change the mode set1 0x0, crcsr set bit inversion set1 0x7, irsr1 enable irda operation chapter 26 fir (fast irda interface unit) 508 26.2.9 crcsr (0x0c00 005c) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name tx_en rx_en 4ppm_dis dpll_dis reserved non_crc crc_inv data_inv r/w r/w r/w r/w r/w r r/w r/w r/w rtcrst00000100 other resets 0 0 0 0 0 1 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 tx_en this bit is used to control (enable/prohibit) masking of transmit start enable flag. masking sequence transition to transmission enable state entered by writing the txfl register is: 0: prohibited 1: enabled d6 rx_en this bit is used to control (enable/prohibit) receive operation. releasing masking of receive line, sampling data, and generating receive clo cks are: 0: prohibited 1: enabled d5 4ppm_dis this bit is used to control (enable/prohibit) the 4ppm modulation (for debugging). the 4ppm modulation of transmit data is: 0: enabled 1: prohibited d4 dpll_dis this bit is used to control (enable/prohibit) the bit correction (for debugging). bit correction of received data is: 0: enabled 1: prohibited d3 reserved write 0 when writing. 0 is returned after a read. d2 non_crc this bit is used to control whether or not a crc is added for frames to be transmitted (for debugging). 0: add crc 1: do not add crc chapter 26 fir (fast irda interface unit) 509 bit name function d1 crc_inv this bit is used to set whether or not a crc is inverted to create an incorrect crc in the normal routine. 0: normal crc (not inverted) 1: inverted crc d0 data_inv this bit is used to set whether or not received/transmitted data i/o is inverted. 0: normal (not inverted) 1: inverted be sure to set as normal in fir, and set as inverted in mir. [caution] during transmission/reception, the contents of this register must not be changed (refresh is possible). 26.2.10 fircr (0x0c00 005e) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name pa_len2 pa_len1 pa_len0 w_pulse1 w_pulse0 f_width2 f_width1 f_width0 r/w r/w r/w r/w r r r/w r/w r/w rtcrst10000101 other resets 1 0 0 0 0 1 0 1 chapter 26 fir (fast irda interface unit) 510 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 to d5 pa_len2 to pa_len0 these bits are used to specify the number of pa (preamble) added to firs transmit frame. pa_len2 to 0 number of pa 001 010 011 100 (default) 111 1 2 4 16 32 others 16 (reserved) d4 and d3 w_pulse1 and w_pulse0 these bits are used to specify the undefined receive pulse width area. pulse width within the undefined receive pulse width area = recognized as single pulse pulse width within other than the undefined receive pulse width area = recognized as double pulse w_pulse 1 and 0 undefined receive pulse width area 00 7 to 8 clocks 01 (default) 8 to 9 clocks 10 9 to 10 clocks 11 10 to 11 clocks d2 to d0 f_width2 to f_width0 these bits are used to specify fir pulse modulation width. the firs output pulse is modulated to a pulse consisting of the number of reference clocks (48 mhz) specified by these bits. f_width2 to 0 single pulse double pulse 000 001 010 011 100 101 (default) 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks others setting prohibited [function] controls the fir operation. [caution] during transmission/reception, the contents of this register must not be changed. chapter 26 fir (fast irda interface unit) 511 26.2.11 mircr (0x0c00 0060) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name sta_len2 sta_len1 sta_len0 m_width4 m_width3 m_width2 m_width1 m_width0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst01001001 other resets 0 1 0 0 1 0 0 1 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 to d5 sta_len2 to sta_len0 these bits are used to specify the number of sta (start flag) added to mirs transmit frame. sta_len2 to 0 number of sta 001 010 (default) 011 100 111 1 2 4 16 32 others 2 (reserved) d4 to d0 m_width4 to m_width0 these bits are used to specify the mir pulse modulation width. the mirs output pulse is modulated to a pulse consisting of the number of reference clocks (48 mhz) specified by these bits. f_width4 to 0 single pulse 00000 00001 : 01001 (default) : 10100 : 11111 1 clock 2 clocks : 10 clocks : 21 clocks : 32 clocks [function] controls the mir operation. the nominal pulse width of mir is 1/4. therefore, be sure to set as follows: mir full mode (1.152 mhz) = 01001 (rate 10/42) mir half mode (0.576 mhz) = 10100 (rate 21/83) [caution] during transmission/reception, the contents of this register must not be changed. chapter 26 fir (fast irda interface unit) 512 26.2.12 dmacr (0x0c00 0062) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name aces_md trans_md reserved reserved reserved demand2 demand1 demand0 r/w r/w r/w r r r r/w r/w r/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 aces_md this bit is used to select the access mode. write 0 when writing. 0 is returned after a read. d6 trans_md this bit is used to specify the transfer direction. trans_md transfer direction 0 1 memory o tdr rdr o memory d5 to d3 reserved write 0 when writing. 0 is returned after a read. d2 to d0 demand2 to these bits are used to specify the demand size. demand0 demand2 to 0 demand size 000 001 010 011 100 101 110 1 2 3 4 5 6 7 111 free size [caution] during the dma operation (both the master side and irda side), the contents of this register must not be changed. chapter 26 fir (fast irda interface unit) 513 26.2.13 dmaer (0x0c00 0064) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved reserved dma_busy dma_en r/w rrrrrrrr/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d2 reserved write 0 when writing. 0 is returned after a read. d1 dma_busy dma busy status 1: busy 0: not busy d0 dma_en this bit is used as a dma operation enable trigger. 1: enable 0: disable note that the dma is not stopped by clearing this bit (to 0). [function] the dma_busy bit is set automatically by setting the dma_en bit to 1. the dma_busy bit is cleared when bit 0 of the fsr register is set or when all frame transmit data is written. chapter 26 fir (fast irda interface unit) 514 26.2.14 txir (0x0c00 0066) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name tx_busy reserved last_tfl tx_th_ov reserved txf_undr txf_full txf_emp r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 tx_busy transmission busy. this bit is set to 1 during the period between pa (in fir) or sta (in mir) transmission and abort transmission. 0: not busy 1: busy d6 reserved write 0 when writing. 0 is returned after a read. d5 last_tfl last transmission frame status. this bit indicates whether data exists or not in the transmission frame size fifo. this bit changes when the sta transmission sequence ends. its initial value is 1. 0: normal 1: exists d4 tx_th_ov transmission fifo threshold over status. this bit indicates whether or not the data size within the transmission fifo exceeds the threshold. 0: normal 1: excesses d3 reserved write 0 when writing. 0 is returned after a read. d2 txf_undr transmission fifo underrun status. this bit indicates whether or not data is read when there is no data in the transmission fifo. 0: normal 1: data is read d1 txf_full transmission fifo full status. this bit indicates that there is no writable space in the transmission fifo. 0: normal 1: no writable space d0 txf_emp transmission fifo empty status. this bit indicates whether or not data to be read exists in the transmission fifo. 0: normal 1: exists chapter 26 fir (fast irda interface unit) 515 26.2.15 rxir (0x0c00 0068) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name rx_busy end_data last_rfl rx_th_o reserved reserved rxf_full rxf_emp r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 rx_busy reception busy. this bit is set to 1 during the period between when pa (in fir) or sta (in mir) is detected and when reception ends. 0: not busy 1: busy d6 end_data frame last data status. this bit indicates whether the last data of frame that is received completely exists or not in the fifo. 0: normal 1: exists d5 last_rfl last reception frame status. this bit is set (to 1) when the reception result (frame size and status) of the 7th frame is stored. 0: normal 1: result is stored d4 rx_th_o reception fifo threshold over status. this bit indicates whether or not the data size within the reception fifo exceeds the threshold. 0: normal 1: excesses d3 and d2 reserved write 0 when writing. 0 is returned after a read. d1 rxf_full reception fifo full status. this bit indicates that there is no writable space in the reception fifo. 0: normal 1: no writable space d0 rxf_emp reception fifo empty status. this bit indicates whether or not data to be read exists in the reception fifo. 0: normal 1: exists chapter 26 fir (fast irda interface unit) 516 [caution] this register can be read only in irda mode. [remark] initial value is the value immediately after the irda operation is enabled or after the reception fifo is cleared. 0x00 is read while the operation stops. chapter 26 fir (fast irda interface unit) 517 26.2.16 ifr (0x0c00 006a) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name tx_abort tx_err rx_valid dma_end rx_end tx_end tx_wr_rq rx_rd_rq r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 tx_abort abort frame transmission end interrupt. this bit indicates that abort frame is transmitted and the following frames transfer reservation is cancelled. 0: normal 1: cancelled d6 tx_err transmission error interrupt. this bit indicates that the transmission error occurs. 0: normal 1: occurs d5 rx_valid reception result valid interrupt. this bit indicates that the last data of frame is read from the reception fifo and the received status becomes valid. 0: normal 1: valid d4 dma_end dma end interrupt. this bit indicates that the dma operation ends. 0: normal 1: ends d3 rx_end reception end interrupt. this bit indicates that sto is detected for each reception frame. 0: normal 1: detected d2 tx_end transmission end interrupt. this bit indicates that sto is transmitted for each transmission frame. 0: normal 1: detected chapter 26 fir (fast irda interface unit) 518 bit name function d1 tx_wr_rq transmission data write request interrupt. this bit indicates that a transmission data write request interrupt has occurred. 0: normal 1: occurs d0 rx_rd_rq reception data read request interrupt. this bit indicates that a reception data read request interrupt has occurred. 0: normal 1: occurs [caution] if bits 7 through 2 of the ifr register are set, the flags that are set to 1 before a read are all cleared to 0. chapter 26 fir (fast irda interface unit) 519 26.2.17 rxsts (0x0c00 006c) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name valid reserved reserved rxf_ov crc_err abort mrxf_ov reserved r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d8 reserved write 0 when writing. 0 is returned after a read. d7 valid valid status in the indication status. this bit is set to 1 when received data of one frame is read completely. 0: received data read not completed 1: received data read completed d6 and d5 reserved write 0 when writing. 0 is returned after a read. d4 rxf_ov receive fifo overrun error. this bit is set to 1 when a receive operation is stopped by receive fifos overrun. 0: normal 1: overrun d3 crc_err crc error. this bit is set t o 1 when the receive result crc does not match with expected value. 0: normal 1: crc error d2 abort abort detection error. this bit is set to 1 when a receive operation is stopped by abort frame detection. 0: normal 1: abort error d1 mrxf_ov maximum receive frame size error. this bit is set to 1 when a receive operation is stopped by maximum receive frame size overrun. 0: normal 1: overrun d0 reserved write 0 when writing. 0 is returned after a read. [function] reads data from the receive status store fifo, in which data of up to 7 frames can be stored. the fifo is initialized by setting bit 1 of the fsr register. received status fifo is used as follows. chapter 26 fir (fast irda interface unit) 520 (1) write (bits 4 to 1) the receive status is written to this register at the same timing of writing data to the receive frame length register. this register shares the write pointer with the receive frame length register. (2) write (bit 7) this bit is set to 1 when the data of receive frame size is read from the fifo. while this bit is 1, data is recognized as valid. (3) read this register shares the read pointer with the receive frame length register. the read pointer is incremented by reading the rxfl (receive frame length) register after valid data is read from this register. chapter 26 fir (fast irda interface unit) 521 26.2.18 txfl (0x0c00 006e) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved txfl12 txfl11 txfl10 txfl9 txfl8 r/w r r r r/w r/w r/w r/w r/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name txfl7 txfl6 txfl5 txfl4 txfl3 txfl2 txfl1 txfl0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d13 reserved write 0 when writing. 0 is returned after a read. d12 to d0 txfl12 to txfl0 transmit frame size. [function] this register functions as prebuffer address for data write to the transmit frame size data store fifo, in which data of up to 7 frames can be stored. setting value = transmit size C 1 setting range = 1 to 2 kbytes the fifo is initialized by setting bit 2 of the fsr register. (1) write the data transmit size of frames to be transferred is written to this register. transmission is enabled when data is written to this register in the state other than transmission busy state (after fifo initialization and after transmission completion). the frames whose number is specified by this register are transferred continuously (back-to-back transfer). during the single frame transfer, fifo should be initialized at each 1-frame transfer completion to restart transmit operation. (2) read the sequencer reads the transmission size from this register after the sta flag of transmission frame is transmitted completed. then, the read pointer is incremented. [caution] if data exists in the fifo when the sto transmit sequence is completed, continuous transfer mode is entered. when multiple frames are transferred, be sure to write data to the txfl register before the sto transmit sequence is completed. chapter 26 fir (fast irda interface unit) 522 26.2.19 mrxf (0x0c00 0070) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved mrxf12 mrxf11 mrxf10 mrxf9 mrxf8 r/w r r r r/w r/w r/w r/w r/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name mrxf7 mrxf6 mrxf5 mrxf4 mrxf3 mrxf2 mrxf1 mrxf0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d13 reserved write 0 when writing. 0 is returned after a read. d12 to d0 mrxf12 to mrxf0 specifies receivable maximum frame size. mrxf max tx frame length 0x0000 1 byte 0x0001 2 bytes :: 0x1fff 2 kbytes [function] the maximum frame size is stored in this register. when a 1-frame receive data is transferred to the receive fifo exceeding the receivable maximum frame size set by this register, an error occurs even under frame reception to end the current frame reception. this sets bit 1 of the rxsts register. after the receive fifo is cleared, if the number of received frames is less than 7 frames, it is possible to continue frame reception. to receive 8 or more frames, read all the data and frames that are already received from the receive fifo, then clear the receive fifo and restart reception. when receiving data via the dma operation, set the transfer size value by the following expression: dma receivable capacitance = set value x 7 frames caution the data exceeding the maximum size cannot be transferred to the fifo. chapter 26 fir (fast irda interface unit) 523 26.2.20 rxfl (0x0c00 0074) bit d15 d14 d13 d12 d11 d10 d9 d8 name reserved reserved reserved rxfl12 rxfl11 rxfl10 rxfl9 rxfl8 r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bitd7d6d5d4d3d2d1d0 name rxfl7 rxfl6 rxfl5 rxfl4 rxfl3 rxfl2 rxfl1 rxfl0 r/w rrrrrrrr rtcrst00000000 other resets 0 0 0 0 0 0 0 0 bit name function d15 to d13 reserved write 0 when writing. 0 is returned after a read. d12 to d0 rxfl12 to rxfl0 receive frame size. [function] this register functions as prebuffer address for data read from the receive frame size data store fifo, in which data of up to 7 frames can be stored. setting value = transmit size C 1 setting range = 1 to 2 kbytes the fifo is initialized by setting bit 1 of the fsr register. (1) write when the frame reception is completed after its data is transferred (even if only 1 byte) to the receive fifo, the sequencer writes the current transfer data size to this register, and the write pointer is incremented. when the frame reception is completed before its data is transferred to the receive fifo, write operation is not performed (lost frame). (2) read the read pointer is enabled to be incremented by reading valid data from the rxsts register, and the next data can be read. [caution] if a receive operation ends abnormally, the data size transferred to the receive fifo at that time is written to this register. when the data of 7 frames are stored, the receive line is automatically masked. therefore, the frame whose receive result cannot be stored is not transferred to the fifo. the update condition of the read pointer of the receive frame size store fifo is also valid in the test mode. 524 [memo] 525 chapter 27 cpu instruction set details this chapter provides a detailed description of the operation of each v r 4102 instruction in both 32- and 64-bit modes. the instructions are listed in alphabetical order. 27.1 instruction notation conventions in this chapter, all variable subfields in an instruction format (such as rs , rt , immediate , etc.) are shown in lowercase names. for the sake of clarity, we sometimes use an alias for a variable subfield in the formats of specific instructions. for example, we use rs = base in the format for load and store instructions. such an alias is always lower case, since it refers to a variable subfield. figures with the actual bit encoding for all the mnemonics are located at the end of this chapter, and the bit encoding also accompanies each instruction. in the instruction descriptions that follow, the operation section describes the operation performed by each instruction using a high-level language notation. the v r 4102 can operate as either a 32- or 64-bit microprocessor and the operation for both modes is included with the instruction description. special symbols used in the notation are described in table 27-1. chapter 27 cpu instruction set details 526 table 27-1. cpu instruction operation notations symbol meaning <- assignment. || bit string concatenation. x y replication of bit value x into a y -bit string. x is always a single-bit value. x y:z selection of bits y through z of bit string x . little-endian bit notation is always used. if y is less than z , this expression is an empty (zero length) bit string. +2 s complement or floating-point addition. -2 s complement or floating-point subtraction. *2 s complement or floating-point multiplication. div 2 s complement integer division. mod 2 s complement modulo. / floating-point division. <2 s complement less than comparison. and bit-wise logical and. or bit-wise logical or. xor bit-wise logical xor. nor bit-wise logical nor. gpr [ x ] general-register x . the content of gpr [0] is always zero. attempts to alter the content of gpr [0] have no effect. cpr [ z, x ] coprocessor unit z , general register x . ccr [ z, x ] coprocessor unit z , control register x . coc [ z ] coprocessor unit z condition signal. bigendianmem big-endian mode as configured at reset (0 -> little, 1 -> big). specifies the endianness of the memory interface (see loadmemory and storememory), and the endianness of kernel and supervisor mode execution. however, this value is always 0 since the v r 4102 supports the little endian order only. reverseendian signal to reverse the endianness of load and store instructions. this feature is available in user mode only, and is effected by setting the re bit of the status register. thus, reverseendian may be computed as (sr 25 and user mode). however, this value is always 0 since the v r 4102 supports the little endian order only. bigendiancpu the endianness for load and store instructions (0 -> little, 1 -> big). in user mode, this endianness may be reversed by setting sr 25 . thus, bigendiancpu may be computed as bigendianmem xor reverseendian. however, this value is always 0 since the v r 4102 supports the little endian order only. t + i : indicates the time steps between operations. each of the statements within a time step are defined to be executed in sequential order (as modified by conditional and loop constructs). operations which are marked t + i : are executed at instruction cycle i relative to the start of execution of the instruction. thus, an instruction which starts at time j executes operations marked t + i: at time i + j . the interpretation of the order of execution between two instructions or two operations which execute at the same time should be pessimistic; the order is not defined. chapter 27 cpu instruction set details 527 (1) instruction notation examples the following examples illustrate the application of some of the instruction notation conventions: example #1: gpr [rt] <- immediate || 0 16 sixteen zero bits are concatenated with an immediate value (typically 16 bits), and the 32-bit string (with the lower 16 bits set to zero) is assigned to general-purpose register rt . example #2: (immediate 15 ) 16 || immediate 15...0 bit 15 (the sign bit) of an immediate value is extended for 16 bit positions, and the result is concatenated with bits 15 through 0 of the immediate value to form a 32-bit sign extended value. 27.2 load and store instructions in the v r 4102 implementation, the instruction immediately following a load may use the loaded contents of the register. in such cases, the hardware interlocks, requiring additional real cycles, so scheduling load delay slots is still desirable, although not required for functional code. in the load and store descriptions, the functions listed in table 27-2 are used to summarize the handling of virtual addresses and physical memory. table 27-2. load and store common functions function meaning address translation uses the tlb to find the physical address given the virtual address. the function fails and an exception is taken if the required translation is not present in the tlb. load memory uses the cache and main memory to find the contents of the word containing the specified physical address. the low-order three bits of the address and the access type field indicate which of each of the four bytes within the data word need to be returned. if the cache is enabled for this access, the entire word is returned and loaded into the cache. store memory uses the cache, write buffer, and main memory to store the word or part of word specified as data in the word containing the specified physical address. the low-order three bits of the address and the access type field indicate which of each of the four bytes within the data word should be stored. as shown in table 27-3, the access type field indicates the size of the data item to be loaded or stored. regardless of access type or byte-numbering order (endianness), the address specifies the byte which has the smallest byte address in the addressed field. this is the rightmost byte in the v r 4102 since it supports the little- endian order only. chapter 27 cpu instruction set details 528 table 27-3. access type specifications for loads/stores access type mnemonic value meaning doubleword septibyte sextibyte quintibyte word triplebyte halfword byte 7 6 5 4 3 2 1 0 8 bytes (64 bits) 7 bytes (56 bits) 6 bytes (48 bits) 5 bytes (40 bits) 4 bytes (32 bits) 3 bytes (24 bits) 2 bytes (16 bits) 1 byte (8 bits) the bytes within the addressed doubleword which are used can be determined directly from the access type and the three low-order bits of the address. 27.3 jump and branch instructions all jump and branch instructions have an architectural delay of exactly one instruction. that is, the instruction immediately following a jump or branch (that is, occupying the delay slot) is always executed while the target instruction is being fetched from storage. a delay slot may not itself be occupied by a jump or branch instruction; however, this error is not detected and the results of such an operation are undefined. if an exception or interrupt prevents the completion of a legal instruction during a delay slot, the hardware sets the epc register to point at the jump or branch instruction that precedes it. when the code is restarted, both the jump or branch instructions and the instruction in the delay slot are reexecuted. because jump and branch instructions may be restarted after exceptions or interrupts, they must be restartable. therefore, when a jump or branch instruction stores a return link value, register r31 (the register in which the link is stored) may not be used as a source register. since instructions must be word-aligned, a jump register or jump and link register instruction must use a register which contains an address whose two low-order bits are zero. if these low-order bits are not zero, an address exception will occur when the jump target instruction is subsequently fetched. 27.4 system control coprocessor (cp0) instructions there are some special limitations imposed on operations involving cp0 that is incorporated within the cpu. although load and store instructions to transfer data to/from coprocessors and to move control to/from coprocessor instructions are generally permitted by the mips architecture, cp0 is given a somewhat protected status since it has responsibility for exception handling and memory management. therefore, the move to/from coprocessor instructions are the only valid mechanism for writing to and reading from the cp0 registers. several cp0 instructions are defined to directly read, write, and probe tlb entries and to modify the operating modes in preparation for returning to user mode or interrupt-enabled states. chapter 27 cpu instruction set details 529 27.5 cpu instruction this section describes the functions of cpu instructions in detail for both 32-bit mode and 64-bit mode. the exception that may occur by executing each instruction is shown in the last of each instructions description. for details of exceptions and their processes, see chapter 6. chapter 27 cpu instruction set details 530 add add add rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 add 1 0 0 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: add rd, rs, rt description: the contents of general register rs and the contents of general register rt are added to form the result. the result is placed into general register rd . in 64-bit mode, the operands must be valid sign-extended, 32-bit values. an overflow exception occurs if the carries out of bits 30 and 31 differ (2s complement overflow). the destination register rd is not modified when an integer overflow exception occurs. operation: 32 t: gpr [rd] <- gpr [rs] + gpr [rt] 64 t: temp <- gpr [rs] + gpr [rt] gpr [rd] <- (temp 31 ) 32 || temp 31...0 exceptions: integer overflow exception chapter 27 cpu instruction set details 531 addi add immediate addi rs addi 0 0 1 0 0 0 rt immediate 31 26 25 21 20 16 15 0 655 16 format: addi rt, rs, immediate description: the 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. the result is placed into general register rt. in 64-bit mode, the operand must be valid sign-extended, 32-bit values. an overflow exception occurs if carries out of bits 30 and 31 differ (2s complement overflow). the destination register rt is not modified when an integer overflow exception occurs. operation: 32 t: gpr [rt] <- gpr [rs] + (immediate 15 ) 16 || immediate 15...0 64 t: temp <- gpr [rs] + (immediate 15 ) 48 || immediate 15...0 gpr [rt] <- (temp 31 ) 32 || temp 31...0 exceptions: integer overflow exception chapter 27 cpu instruction set details 532 addiu add immediate unsigned addiu rs addiu 0 0 1 0 0 1 rt immediate 31 26 25 21 20 16 15 0 655 16 format: addiu rt, rs, immediate description: the 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. the result is placed into general register rt. no integer overflow exception occurs under any circumstances. in 64-bit mode, the operand must be valid sign-extended, 32-bit values. the only difference between this instruction and the addi instruction is that addiu never causes an integer overflow exception. operation: 32 t: gpr [rt] <- gpr [rs] + (immediate 15 ) 16 || immediate 15...0 64 t: temp <- gpr [rs] + (immediate 15 ) 48 || immediate 15...0 gpr [rt] <- (temp 31 ) 32 || temp 31...0 exceptions: none chapter 27 cpu instruction set details 533 addu add unsigned addu rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 addu 1 0 0 0 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: addu rd, rs, rt description: the contents of general register rs and the contents of general register rt are added to form the result. the result is placed into general register rd . no integer overflow exception occurs under any circumstances. in 64-bit mode, the operands must be valid sign-extended, 32-bit values. the only difference between this instruction and the add instruction is that addu never causes an integer overflow exception. operation: 32 t: gpr [rd] <- gpr [rs] + gpr [rt] 64 t: temp <- gpr [rs] + gpr [rt] gpr [rd] <- (temp 31 ) 32 || temp 31...0 exceptions: none chapter 27 cpu instruction set details 534 and and and rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 and 1 0 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: and rd, rs, rt description: the contents of general register rs are combined with the contents of general register rt in a bit-wise logical and operation. the result is placed into general register rd . operation: 32 t: gpr [rd] <- gpr [rs] and gpr [rt] 64 t: gpr [rd] <- gpr [rs] and gpr [rt] exceptions: none chapter 27 cpu instruction set details 535 andi and immediate andi rs andi 0 0 1 1 0 0 rt immediate 31 26 25 21 20 16 15 0 655 16 format: andi rt, rs, immediate description: the 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical and operation. the result is placed into general register rt . operation: 32 t: gpr [rt] <- 0 16 || (immediate and gpr [rs] 15...0 ) 64 t: gpr [rt] <- 0 48 || (immediate and gpr [rs] 15...0 ) exceptions: none chapter 27 cpu instruction set details 536 bc0f branch on coprocessor 0 false bc0f bc 0 1 0 0 0 copz 0 1 0 0 x x note bcf 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 655 16 format: bc0f offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. if coprocessor 0s condition signal (cpcond: status register bit-18 ch field), as sampled during the previous instruction, is false, then the program branches to the target address with a delay of one instruction. because the condition line is sampled during the previous instruction, there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line. operation: 32 t-1: condition <- not sr 18 t: target <- (offset 15 ) 14 || offset || 0 2 t+1: if condition then pc <- pc + target endif 64 t-1: condition <- not sr 18 t: target <- (offset 15 ) 46 || offset || 0 2 t+1: if condition then pc <- pc + target endif exceptions: coprocessor unusable exception note see the opcode table below, or 27.6 cpu instruction opcode bit encoding . opcode table: 31 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 0 bc0f opcode coprocessor number bc sub-opcode branch condition chapter 27 cpu instruction set details 537 bc0fl branch on coprocessor 0 false likely bc0fl bc 0 1 0 0 0 copz 0 1 0 0 x x note bcfl 0 0 0 1 0 offset 31 26 25 21 20 16 15 0 655 16 format: bc0fl offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. if the contents of coprocessor 0s condition line, as sampled during the previous instruction, is false, the target address is branched to with a delay of one instruction. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. because the condition line is sampled during the previous instruction, there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line. operation: 32 t-1: condition <- not sr 18 t: target <- (offset 15 ) 14 || offset || 0 2 t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t-1: condition <- not sr 18 t: target <- (offset 15 ) 46 || offset || 0 2 t+1: if condition then pc <- pc + target else nullifycurrentlnstruction endif exceptions: coprocessor unusable exception note see the opcode table below, or 27.6 cpu instruction opcode bit encoding . opcode table: 31 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 1 16 0 0 bc0fl opcode coprocessor number bc sub-opcode branch condition chapter 27 cpu instruction set details 538 bc0t branch on coprocessor 0 true bc0t bc 0 1 0 0 0 copz 0 1 0 0 x x note bct 0 0 0 0 1 offset 31 26 25 21 20 16 15 0 655 16 format: bc0t offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. if the coprocessor 0s condition signal (cpcond: status register bit- 18 ch field) is true, then the program branches to the target address, with a delay of one instruction. because the condition line is sampled during the previous instruction, there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line. operation: 32 t-1: condition <- sr 18 t: target <- (offset 15 ) 14 || offset || 0 2 t+1: if condition then pc <- pc + target endif 64 t-1: condition <- sr 18 t: target <- (offset 15 ) 46 || offset || 0 2 t+1: if condition then pc <- pc + target endif exceptions: coprocessor unusable exception note see the opcode table below, or 27.6 cpu instruction opcode bit encoding . opcode table: 31 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 1 0 bc0t opcode coprocessor number bc sub-opcode branch condition chapter 27 cpu instruction set details 539 bc0tl branch on coprocessor 0 true likely bc0tl bc 0 1 0 0 0 copz 0 1 0 0 x x note bctl 0 0 0 1 1 offset 31 26 25 21 20 16 15 0 655 16 format: bc0tl offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. if the contents of coprocessor 0s condition line, as sampled during the previous instruction, is true, the target address is branched to with a delay of one instruction. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. because the condition line is sampled during the previous instruction, there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line. operation: 32 t-1: condition <- sr 18 t: target <- (offset 15 ) 14 || offset || 0 2 t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t-1: condition <- sr 18 t: target <- (offset 15 ) 46 || offset || 0 2 t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif exceptions: coprocessor unusable exception note see the opcode table below, or 27.6 cpu instruction opcode bit encoding . opcode table: 31 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 1 16 1 0 bc0tl opcode coprocessor number bc sub-opcode branch condition chapter 27 cpu instruction set details 540 beq branch on equal beq rs beq 0 0 0 1 0 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: beq rs, rt, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. the contents of general register rs and the contents of general register rt are compared. if the two registers are equal, then the program branches to the target address, with a delay of one instruction. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] = gpr [rt]) t+1: if condition then pc <- pc + target endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] = gpr [rt]) t+1: if condition then pc <- pc + target endif exceptions: none chapter 27 cpu instruction set details 541 beql branch on equal likely beql rs beql 0 1 0 1 0 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: beql rs, rt, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. the contents of general register rs and the contents of general register rt are compared. if the two registers are equal, the target address is branched to, with a delay of one instruction. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] = gpr [rt]) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] = gpr [rt]) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif exceptions: none chapter 27 cpu instruction set details 542 bgez branch on greater than or equal to zero bgez rs regimm 0 0 0 0 0 1 bgez 0 0 0 0 1 offset 31 26 25 21 20 16 15 0 655 16 format: bgez rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. if the contents of general register rs have the sign bit cleared, then the program branches to the target address, with a delay of one instruction. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 0) t+1: if condition then pc <- pc + target endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 0) t+1: if condition then pc <- pc + target endif exceptions: none chapter 27 cpu instruction set details 543 bgezal branch on greater than or equal to zero and link bgezal rs regimm 0 0 0 0 0 1 bgezal 1 0 0 0 1 offset 31 26 25 21 20 16 15 0 655 16 format: bgezal rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. unconditionally, the address of the instruction after the delay slot is placed in the link register, r31 . if the contents of general register rs have the sign bit cleared, then the program branches to the target address, with a delay of one instruction. general register rs may not be general register r31 , because such an instruction is not restartable. an attempt to execute this instruction is not trapped, however. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 0) gpr [31] <- pc + 8 t+1: if condition then pc <- pc + target endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 0) gpr [31] <- pc + 8 t+1: if condition then pc <- pc + target endif exceptions: none chapter 27 cpu instruction set details 544 bgezall branch on greater than or equal to zero and link likely bgezall rs regimm 0 0 0 0 0 1 bgezall 1 0 0 1 1 offset 31 26 25 21 20 16 15 0 655 16 format: bgezall rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. unconditionally, the address of the instruction after the delay slot is placed in the link register, r31 . if the contents of general register rs have the sign bit cleared, then the program branches to the target address, with a delay of one instruction. general register rs may not be general register 31 , because such an instruction is not restartable. an attempt to execute this instruction is not trapped, however. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 0) gpr [31] <- pc + 8 t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 0) gpr [31] <- pc + 8 t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif exceptions: none chapter 27 cpu instruction set details 545 bgezl branch on greater than or equal to zero likely bgezl rs regimm 0 0 0 0 0 1 bgezl 0 0 0 1 1 offset 31 26 25 21 20 16 15 0 655 16 format: bgezl rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. if the contents of general register rs have the sign bit cleared, then the program branches to the target address, with a delay of one instruction. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 0) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 0) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif exceptions: none chapter 27 cpu instruction set details 546 bgtz branch on greater than zero bgtz rs bgtz 0 0 0 1 1 1 0 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 655 16 format: bgtz rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. the contents of general register rs are compared to zero. if the contents of general register rs have the sign bit cleared and are not equal to zero, then the program branches to the target address, with a delay of one instruction. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 0) and (gpr [rs] z 0 32 ) t+1: if condition then pc <- pc + target endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 0) and (gpr [rs] z 0 64 ) t+1: if condition then pc <- pc + target endif exceptions: none chapter 27 cpu instruction set details 547 bgtzl branch on greater than zero likely bgtzl rs bgtzl 0 1 0 1 1 1 0 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 655 16 format: bgtzl rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. the contents of general register rs are compared to zero. if the contents of general register rs have the sign bit cleared and are not equal to zero, then the program branches to the target address, with a delay of one instruction. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 0) and (gpr [rs] z 0 32 ) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 0) and (gpr [rs] z 0 64 ) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif exceptions: none chapter 27 cpu instruction set details 548 blez branch on less than or equal to zero blez rs blez 0 0 0 1 1 0 0 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 655 16 format: blez rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. the contents of general register rs are compared to zero. if the contents of general register rs have the sign bit set, or are equal to zero, then the program branches to the target address, with a delay of one instruction. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 1) or (gpr [rs] = 0 32 ) t+1: if condition then pc <- pc + target endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 1) or (gpr [rs] = 0 64 ) t+1: if condition then pc <- pc + target endif exceptions: none chapter 27 cpu instruction set details 549 blezl branch on less than or equal to zero likely blezl rs blezl 0 1 0 1 1 0 0 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 655 16 format: blezl rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. the contents of general register rs is compared to zero. if the contents of general register rs have the sign bit set, or are equal to zero, then the program branches to the target address, with a delay of one instruction. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 1) or (gpr [rs] = 0 32 ) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 1) or (gpr [rs] = 0 64 ) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif exceptions: none chapter 27 cpu instruction set details 550 bltz branch on less than zero bltz rs regimm 0 0 0 0 0 1 bltz 0 0 0 0 0 offset 31 26 25 21 20 16 15 0 655 16 format: bltz rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. if the contents of general register rs have the sign bit set, then the program branches to the target address, with a delay of one instruction. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 1) t+1: if condition then pc <- pc + target endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 1) t+1: if condition then pc <- pc + target endif exceptions: none chapter 27 cpu instruction set details 551 bltzal branch on less than zero and link bltzal rs regimm 0 0 0 0 0 1 bltzal 1 0 0 0 0 offset 31 26 25 21 20 16 15 0 655 16 format: bltzal rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. unconditionally, the address of the instruction after the delay slot is placed in the link register, r31 . if the contents of general register rs have the sign bit set, then the program branches to the target address, with a delay of one instruction. general register rs may not be general register 31 , because such an instruction is not restartable. an attempt to execute this instruction with register 31 specified as rs is not trapped, however. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 1) gpr [31] <- pc + 8 t+1: if condition then pc <- pc + target endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 1) gpr [31] <- pc + 8 t+1: if condition then pc <- pc + target endif exceptions: none chapter 27 cpu instruction set details 552 bltzall branch on less than zero and link likely bltzall rs regimm 0 0 0 0 0 1 bltzall 1 0 0 1 0 offset 31 26 25 21 20 16 15 0 655 16 format: bltzall rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. unconditionally, the address of the instruction after the delay slot is placed in the link register, r31 . if the contents of general register rs have the sign bit set, then the program branches to the target address, with a delay of one instruction. general register rs may not be general register 31 , because such an instruction is not restartable. an attempt to execute this instruction with register 31 specified as rs is not trapped, however. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 1) gpr [31] <- pc + 8 t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 1) gpr [31] <- pc + 8 t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif exceptions: none chapter 27 cpu instruction set details 553 bltzl branch on less than zero likely bltzl rs regimm 0 0 0 0 0 1 bltzl 0 0 0 1 0 offset 31 26 25 21 20 16 15 0 655 16 format: bltz rs, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended. if the contents of general register rs have the sign bit set, then the program branches to the target address, with a delay of one instruction. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] 31 = 1) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] 63 = 1) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif exceptions: none chapter 27 cpu instruction set details 554 bne branch on not equal bne rs bne 0 0 0 1 0 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: bne rs, rt, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. the contents of general register rs and the contents of general register rt are compared. if the two registers are not equal, then the program branches to the target address, with a delay of one instruction. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] z gpr [rt]) t+1: if condition then pc <- pc + target endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] z gpr [rt]) t+1: if condition then pc <- pc + target endif exceptions: none chapter 27 cpu instruction set details 555 bnel branch on not equal likely bnel rs bnel 0 1 0 1 0 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: bnel rs, rt, offset description: a branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. the contents of general register rs and the contents of general register rt are compared. if the two registers are not equal, then the program branches to the target address, with a delay of one instruction. if the conditional branch is not taken, the instruction in the branch delay slot is nullified. operation: 32 t: target <- (offset 15 ) 14 || offset || 0 2 condition <- (gpr [rs] z gpr [rt]) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif 64 t: target <- (offset 15 ) 46 || offset || 0 2 condition <- (gpr [rs] z gpr [rt]) t+1: if condition then pc <- pc + target else nullifycurrentinstruction endif exceptions: none chapter 27 cpu instruction set details 556 break breakpoint break code special 0 0 0 0 0 0 break 0 0 1 1 0 1 31 26 25 6 5 0 6206 format: break description: a breakpoint trap occurs, immediately and unconditionally transferring control to the exception handler. the code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. operation: 32,64 t: breakpointexception exceptions: breakpoint exception chapter 27 cpu instruction set details 557 cache cache cache base cache 1 0 1 1 1 1 op offset 31 26 25 21 20 16 15 0 655 16 format: cache op, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the virtual address is translated to a physical address using the tlb, and the 5-bit sub-opcode specifies a cache operation for that address. if cp0 is not usable (user or supervisor mode) and the cp0 enable bit in the status register is clear, a coprocessor unusable exception is taken. the operation of this instruction on any operation/cache combination not listed below, or on a secondary cache, is undefined. the operation of this instruction on uncached addresses is also undefined. the index operation uses part of the virtual address to specify a cache block. for a primary cache of 2 cachebits bytes with 2 linebits bytes per tag, vaddr cachebits...linebits specifies the block. index load tag also uses vaddr linebits...3 to select the doubleword for reading parity. when the ce bit of the status register is set, fill cache op uses the perr register to store parity values into the cache. the hit operation accesses the specified cache as normal data references, and performs the specified operation if the cache block contains valid data with the specified physical address (a hit). if the cache block is invalid or contains a different address (a miss), no operation is performed. chapter 27 cpu instruction set details 558 cache cache cache (continued) write back from a primary cache goes to memory. the address to be written is specified by the cache tag and not the translated physical address. tlb refill and tlb invalid exceptions can occur on any operation. for index operations (where the physical address is used to index the cache but need not match the cache tag) unmapped addresses may be used to avoid tlb exceptions. this operation never causes a tlb modified exception. bits 17...16 of the instruction specify the cache as follows: code name cache 0 i primary instruction 1 d primary data 2, 3 na reserved (undefined) chapter 27 cpu instruction set details 559 cache cache cache (continued) bits 20...18 (this value is listed under the code column) of the instruction specify the operation as follows: code cache name operation 0 i index_invalidate set the cache state of the cache block to invalid. 0 d index_write_back invalidate examine the cache state and w bit of the primary data cache block at the index specified by the virtual address. if the state is not invalid and the w bit is set, then write back the block to memory. the address to write is taken from the primary cache tag. set cache state of primary cache block to invalid. 1 i, d index_load_tag read the tag for the cache block at the specified index and place it into the taglo cp0 registers, ignoring parity errors. also load the data parity bits into the ecc register. 2 i, d index_store_tag write the tag for the cache block at the specified index from the taglo and taghi cp0 registers. 3 d create_dirty_ exclusive this operation is used to avoid loading data needlessly from memory when writing new contents into an entire cache block. if the cache block does not contain the specified address, and the block is dirty, write it back to the memory. in all cases, set the cache state to dirty. 4 i, d hit_invalidate if the cache block contains the specified address, mark the cache block invalid. 5 d hit_write_back invalidate if the cache block contains the specified address, write back the data if it is dirty, and mark the cache block invalid. 5 i fill fill the primary instruction cache block from memory. if the ce bit of the status register is set, the contents of the ecc register is used instead of the computed parity bits for addressed doubleword when written to the instruction cache. 6 d hit_write_back if the cache block contains the specified address and the w bit is set, write back the data to memory and clear the w bit. 6 i hit_write_back if the cache block contains the specified address, write back the data unconditionally. chapter 27 cpu instruction set details 560 cache cache cache (continued) operation: 32, 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) cacheop (op, vaddr, paddr) exceptions: coprocessor unusable exception tlb refill exception tlb invalid exception bus error exception address error exception cache error exception chapter 27 cpu instruction set details 561 dadd doubleword add dadd rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 dadd 1 0 1 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dadd rd, rs, rt description: the contents of general register rs and the contents of general register rt are added to form the result. the result is placed into general register rd . an overflow exception occurs if the carries out of bits 62 and 63 differ (2s complement overflow). the destination register rd is not modified when an integer overflow exception occurs. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: gpr [rd] <- gpr [rs] + gpr [rt] exceptions: integer overflow exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 562 daddi doubleword add immediate daddi rs daddi 0 1 1 0 0 0 rt immediate 31 26 25 21 20 16 15 0 655 16 format: daddi rt, rs, immediate description: the 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. the result is placed into general register rt. an overflow exception occurs if carries out of bits 62 and 63 differ (2s complement overflow). the destination register rt is not modified when an integer overflow exception occurs. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: gpr [rt] <- gpr [rs] + (immediate 15 ) 48 || immediate 15...0 exceptions: integer overflow exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 563 daddiu doubleword add immediate unsigned daddiu rs daddiu 0 1 1 0 0 1 rt immediate 31 26 25 21 20 16 15 0 655 16 format: daddiu rt, rs, immediate description: the 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. the result is placed into general register rt. no integer overflow exception occurs under any circumstances. the only difference between this instruction and the daddi instruction is that daddiu never causes an overflow exception. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: gpr [rt] <- gpr [rs] + (immediate 15 ) 48 || immediate 15...0 exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 564 daddu doubleword add unsigned daddu rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 daddu 1 0 1 1 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: daddu rd, rs, rt description: the contents of general register rs and the contents of general register rt are added to form the result. the result is placed into general register rd . no overflow exception occurs under any circumstances. the only difference between this instruction and the dadd instruction is that daddu never causes an overflow exception. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: gpr [rd] <- gpr [rs] + gpr [rt] exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 565 ddiv doubleword divide ddiv rs special 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 ddiv 0 1 1 1 1 0 31 26 25 21 20 16 15 6 5 0 655 10 6 format: ddiv rs, rt description: the contents of general register rs are divided by the contents of general register rt, treating both operands as 2s complement values. no overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero. this instruction is typically followed by additional instructions to check for a zero divisor and for overflow. when the operation completes, the quotient word of the double result is loaded into special register lo , and the remainder word of the double result is loaded into special register hi . if either of the two preceding instructions is mfhi or mflo, the results of those instructions are undefined. correct operation requires separating reads of hi or lo from writes by two or more instructions. this is defined in this manner to take account of the v r 4000 tm hazards (for code compatibility) as well as the v r 4100s own hazards. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: lo <- gpr [rs] div gpr [rt] hi <- gpr [rs] mod gpr [rt] exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 566 ddivu doubleword divide unsigned ddivu rs special 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 655 10 ddivu 0 1 1 1 1 1 65 6 format: ddivu rs, rt description: the contents of general register rs are divided by the contents of general register rt, treating both operands as unsigned values. no integer overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero. this instruction may be followed by additional instructions to check for a zero divisor, inserted by the programmer. when the operation completes, the quotient word of the double result is loaded into special register lo , and the remainder word of the double result is loaded into special register hi . if either of the two preceding instructions is mfhi or mflo, the results of those instructions are undefined. correct operation requires separating reads of hi or lo from writes by two or more instructions. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: lo <- (0 || gpr [rs]) div (0 || gpr [rt]) hi <- (0 || gpr [rs]) mod (0 || gpr [rt]) exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 567 div divide div rs special 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 655 10 div 0 1 1 0 1 0 65 6 format: div rs, rt description: the contents of general register rs are divided by the contents of general register rt, treating both operands as 2s complement values. no overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero. in 64-bit mode, the operands must be valid sign-extended, 32-bit values. this instruction is typically followed by additional instructions to check for a zero divisor and for overflow. when the operation completes, the quotient word of the double result is loaded into special register lo , and the remainder word of the double result is loaded into special register hi . if either of the two preceding instructions is mfhi or mflo, the results of those instructions are undefined. correct operation requires separating reads of hi or lo from writes by two or more instructions. operation: 32 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: lo <- gpr [rs] div gpr [rt] hi <- gpr [rs] mod gpr [rt] 64 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: q <- gpr [rs] 31..0 div gpr [rt] 31..0 r <- gpr [rs] 31..0 mod gpr [rt] 31..0 lo <- (q 31 ) 32 || q 31..0 hi <- (r 31 ) 32 || r 31..0 exceptions: none chapter 27 cpu instruction set details 568 divu divide unsigned divu rs special 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 655 10 divu 0 1 1 0 1 1 65 6 format: divu rs, rt description: the contents of general register rs are divided by the contents of general register rt, treating both operands as unsigned values. no integer overflow exception occurs under any circumstances, and the result of this operation is undefined when the divisor is zero. in 64-bit mode, the operands must be valid sign-extended, 32-bit values. this instruction is typically followed by additional instructions to check for a zero divisor. when the operation completes, the quotient word of the double result is loaded into special register lo , and the remainder word of the double result is loaded into special register hi . if either of the two preceding instructions is mfhi or mflo, the results of those instructions are undefined. correct operation requires separating reads of hi or lo from writes by two or more instructions. operation: 32 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: lo <- (0 || gpr [rs]) div (0 || gpr [rt]) hi <- (0 || gpr [rs]) mod (0 || gpr [rt]) 64 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: q <- (0 || gpr [rs] 31..0 ) div (0 || gpr [rt] 31..0 ) r <- (0 || gpr [rs] 31..0 ) mod (0 || gpr [rt] 31..0 ) lo <- (q 31 ) 32 || q 31..0 hi <- (r 31 ) 32 || r 31..0 exceptions: none chapter 27 cpu instruction set details 569 dmadd16 doubleword multiply and add 16-bit integer dmadd16 rs special 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 655 10 dmadd16 1 0 1 0 0 1 65 6 format: dmadd16 rs, rt description: the contents of general registers rs and rt are multiplied, treating both operands as 16-bit 2s complement values. the operand[62:15] must be valid 15-bit, sign-extended values. if not, the result is unpredictable. this multiplied result and the 64-bit data joined of special register lo is added to form the result as a signed integer. when the operation completes, the doubleword result is loaded into special register lo . no integer overflow exception occurs under any circumstances. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. the following table shows hazard cycles between dmadd16 and other instructions. instruction sequence no. of cycles mult/multu -> dmadd16 1 cycle dmult/dmultu -> dmadd16 4 cycles div/divu -> dmadd16 36 cycles ddiv/ddivu -> dmadd16 68 cycles mfhi/mflo -> dmadd16 2 cycles madd16 -> dmadd16 0 cycles dmadd16 -> dmadd16 0 cycles chapter 27 cpu instruction set details 570 dmadd16 doubleword multiply and add 16-bit integer dmadd16 (continued) operation: 64 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: temp <- gpr [rs] * gpr [rt] temp <- temp + lo lo <- temp hi <- undefined exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 571 dmfc0 doubleword move from system control coprocessor dmfc0 dmf 0 0 0 0 1 cop0 0 1 0 0 0 0 rt rd 31 26 25 21 20 16 15 0 6 555 0 0 0 0 0 0 0 0 0 0 0 0 11 10 11 format: dmfc0 rt, rd description: the contents of coprocessor register rd of the cp0 are loaded into general register rt. this operation is defined for the v r 4102 operating in 64-bit mode and in 32-bit kernel mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. all 64-bits of the general register destination are written from the coprocessor register source. the operation of dmfc0 on a 32-bit coprocessor 0 register is undefined. operation: 64 t: data <- cpr [0, rd] t+1: gpr [rt] <- data exceptions: coprocessor unusable exception (user mode and supervisor mode if cp0 not enabled) reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 572 dmtc0 doubleword move to system control coprocessor dmtc0 dmt 0 0 1 0 1 cop0 0 1 0 0 0 0 rt rd 31 26 25 21 20 16 15 0 6 555 0 0 0 0 0 0 0 0 0 0 0 0 11 10 11 format: dmtc0 rt, rd description: the contents of general register rt are loaded into coprocessor register rd of the cp0. this operation is defined for the v r 4102 operating in 64-bit mode or in 32-bit kernel mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. all 64-bits of the coprocessor 0 register are written from the general register source. the operation of dmtc0 on a 32-bit coprocessor 0 register is undefined. because the state of the virtual address translation system may be altered by this instruction, the operation of load instructions, store instructions, and tlb operations immediately prior to and after this instruction are undefined. operation: 64 t: data <- gpr [rt] t+1: cpr [0, rd] <- data exceptions: coprocessor unusable exception (in user and supervisor mode if cp0 not enabled) reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 573 dmult doubleword multiply dmult rs special 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 655 10 dmult 0 1 1 1 0 0 65 6 format: dmult rs, rt description: the contents of general registers rs and rt are multiplied, treating both operands as 2s complement values. no integer overflow exception occurs under any circumstances. when the operation completes, the low-order word of the double result is loaded into special register lo , and the high-order word of the double result is loaded into special register hi . if either of the two preceding instructions is mfhi or mflo, the results of these instructions are undefined. correct operation requires separating reads of hi or lo from writes by a minimum of two other instructions. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: t <- gpr [rs] * gpr [rt] lo <- t 63..0 hi <- t 127..64 exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 574 dmultu doubleword multiply unsigned dmultu rs special 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 655 10 dmultu 0 1 1 1 0 1 65 6 format: dmultu rs, rt description: the contents of general register rs and the contents of general register rt are multiplied, treating both operands as unsigned values. no overflow exception occurs under any circumstances. when the operation completes, the low-order word of the double result is loaded into special register lo , and the high-order word of the double result is loaded into special register hi . if either of the two preceding instructions is mfhi or mflo, the results of these instructions are undefined. correct operation requires separating reads of hi or lo from writes by a minimum of two instructions. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: t <- (0 || gpr [rs]) * (0 || gpr [rt]) lo <- t 63..0 hi <- t 127..64 exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 575 dsll doubleword shift left logical dsll 0 0 0 0 0 0 special 0 0 0 0 0 0 rt rd sa dsll 1 1 1 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsll rd, rt, sa description: the contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits. the result is placed in register rd. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: s <- 0 || sa gpr [rd] <- gpr [rt] (63 - s)..0 || 0 s exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 576 dsllv doubleword shift left logical variable dsllv rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 dsllv 0 1 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsllv rd, rt, rs description: the contents of general register rt are shifted left by the number of bits specified by the low-order six bits contained in general register rs , inserting zeros into the low-order bits. the result is placed in register rd . this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: s <- gpr [rs] 5..0 gpr [rd] <- gpr [rt] (63 - s)..0 || 0 s exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 577 dsll32 doubleword shift left logical + 32 dsll32 0 0 0 0 0 0 special 0 0 0 0 0 0 rt rd sa dsll32 1 1 1 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsll32 rd, rt, sa description: the contents of general register rt are shifted left by 32 + sa bits, inserting zeros into the low-order bits. the result is placed in register rd . this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: s <- 1 || sa gpr [rd] <- gpr [rt] (63 - s)..0 || 0 s exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 578 dsra doubleword shift right arithmetic dsra 0 0 0 0 0 0 special 0 0 0 0 0 0 rt rd sa dsra 1 1 1 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsra rd, rt, sa description: the contents of general register rt are shifted right by sa bits, sign-extending the high-order bits. the result is placed in register rd . this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: s <- 0 || sa gpr [rd] <- (gpr [rt] 63 ) s || gpr [rt] 63..s exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 579 dsrav doubleword shift right arithmetic variable dsrav rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 dsrav 0 1 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 555 6 format: dsrav rd, rt, rs description: the contents of general register rt are shifted right by the number of bits specified by the low-order six bits of general register rs , sign-extending the high-order bits. the result is placed in register rd . this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: s <- gpr [rs] 5..0 gpr [rd] <- (gpr [rt] 63 ) s || gpr [rt] 63..s exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 580 dsra32 doubleword shift right arithmetic + 32 dsra32 0 0 0 0 0 0 special 0 0 0 0 0 0 rt rd sa dsra32 1 1 1 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsra32 rd, rt, sa description: the contents of general register rt are shifted right by 32 + sa bits, sign-extending the high-order bits. the result is placed in register rd . this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: s <- 1 || sa gpr [rd] <- (gpr [rt] 63 ) s || gpr [rt] 63..s exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 581 dsrl doubleword shift right logical dsrl 0 0 0 0 0 0 special 0 0 0 0 0 0 rt rd sa dsrl 1 1 1 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsrl rd, rt, sa description: the contents of general register rt are shifted right by sa bits, inserting zeros into the high-order bits. the result is placed in register rd . this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: s <- 0 || sa gpr [rd] <- 0 s || gpr [rt] 63..s exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 582 dsrlv doubleword shift right logical variable dsrlv rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 dsrlv 0 1 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsrlv rd, rt, rs description: the contents of general register rt are shifted right by the number of bits specified by the low-order six bits of general register rs, inserting zeros into the high-order bits. the result is placed in register rd . this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: s <- gpr [rs] 5..0 gpr [rd] <- 0 s || gpr [rt] 63..s exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 583 dsrl32 doubleword shift right logical + 32 dsrl32 0 0 0 0 0 0 special 0 0 0 0 0 0 rt rd sa dsrl32 1 1 1 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsrl32 rd, rt, sa description: the contents of general register rt are shifted right by 32 + sa bits, inserting zeros into the high-order bits. the result is placed in register rd . this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: s <- 1 || sa gpr [rd] <- 0 s || gpr [rt] 63..s exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 584 dsub doubleword subtract dsub rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 dsub 1 0 1 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsub rd, rs, rt description: the contents of general register rt are subtracted from the contents of general register rs to form a result. the result is placed into general register rd. the only difference between this instruction and the dsubu instruction is that dsubu never traps on overflow. an integer overflow exception takes place if the carries out of bits 62 and 63 differ (2s complement overflow). the destination register rd is not modified when an integer overflow exception occurs. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: gpr [rd] <- gpr [rs] - gpr [rt] exceptions: integer overflow exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 585 dsubu doubleword subtract unsigned dsubu rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 dsubu 1 0 1 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: dsubu rd, rs, rt description: the contents of general register rt are subtracted from the contents of general register rs to form a result. the result is placed into general register rd . the only difference between this instruction and the dsub instruction is that dsubu never traps on overflow. no integer overflow exception occurs under any circumstances. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: gpr [rd] <- gpr [rs] - gpr [rt] exceptions: reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 586 eret exception return eret co 1 cop0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 eret 0 1 1 0 0 0 31 26 25 24 6 5 0 61 19 6 format: eret description: eret is the v r 4102 instruction for returning from an interrupt, exception, or error trap. unlike a branch or jump instruction, eret does not execute the next instruction. eret must not itself be placed in a branch delay slot. if the processor is servicing an error trap ( sr 2 = 1), then load the pc from the errorepc register and clear the erl bit of the status register ( sr 2 ). otherwise ( sr 2 = 0), load the pc from the epc register, and clear the exl bit of the status register ( sr 1 ). operation: 32, 64 t: if sr 2 = 1 then pc <- errorepc sr <- sr 31..3 || 0 || sr 1..0 else pc <-epc sr <- sr 31..2 || 0 || sr 0 endif exceptions: coprocessor unusable exception chapter 27 cpu instruction set details 587 hibernate hibernate hibernate co 1 cop0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 hibernate 1 0 0 0 1 1 31 26 25 24 6 5 0 61 19 6 format: hibernate description: hibernate instruction starts mode transition from fullspeed mode to hibernate mode. when the hibernate instruction finishes the wb stage, the v r 4102 wait by the sysad bus is idle state, after then the internal clocks and the system interface clocks will shut down, thus freezing the pipeline. once the v r 4102 is in hibernate mode, the cold reset sequence will cause the v r 4102 to exit hibernate mode and to enter fullspeed mode. operation: 32, 64 t: t+1: hibernate operation () exceptions: coprocessor unusable exception remark refer to chapter 15 for details about the operation of the peripheral units at mode transition. chapter 27 cpu instruction set details 588 j jump j j 0 0 0 0 1 0 target 31 26 25 0 626 format: j target description: the 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the delay slot. the program unconditionally jumps to this calculated address with a delay of one instruction. operation: 32 t: temp <- target t+1: pc <- pc 31..28 || temp || 0 2 64 t: temp <- target t+1: pc <- pc 63..28 || temp || 0 2 exceptions: none chapter 27 cpu instruction set details 589 jal jump and link jal jal 0 0 0 0 1 1 target 31 26 25 0 626 format: jal target description: the 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the delay slot. the program unconditionally jumps to this calculated address with a delay of one instruction. the address of the instruction after the delay slot is placed in the link register, r31 . operation: 32 t: temp <- target gpr [31] <- pc + 8 t+1: pc <- pc 31..28 || temp || 0 2 64 t: temp <- target gpr [31] <- pc + 8 t+1: pc <- pc 63..28 || temp || 0 2 exceptions: none chapter 27 cpu instruction set details 590 jalr jump and link register jalr rs special 0 0 0 0 0 0 0 0 0 0 0 0 rd 0 0 0 0 0 0 jalr 0 0 1 0 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: jalr rs jalr rd, rs description: the program unconditionally jumps to the address contained in general register rs , with a delay of one instruction. the address of the instruction after the delay slot is placed in general register rd . the default value of rd , if omitted in the assembly language instruction, is 31. register specifiers rs and rd may not be equal, because such an instruction does not have the same effect when re-executed. however, an attempt to execute this instruction is not trapped, and the result of executing such an instruction is undefined. since instructions must be word-aligned, a jump and link register instruction must specify a target register ( rs ) which contains an address whose two low-order bits are zero. if these low-order bits are not zero, an address error exception will occur when the jump target instruction is subsequently fetched. operation: 32,64 t: temp <- gpr [rs] gpr [rd] <- pc + 8 t+1: pc <- temp exceptions: none chapter 27 cpu instruction set details 591 jr jump register jr rs special 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 0 65 15 jr 0 0 1 0 0 0 65 6 format: jr rs description: the program unconditionally jumps to the address contained in general register rs , with a delay of one instruction. since instructions must be word-aligned, a jump register instruction must specify a target register ( rs ) which contains an address whose two low-order bits are zero. if these low-order bits are not zero, an address error exception will occur when the jump target instruction is subsequently fetched. operation: 32,64 t: temp <- gpr [rs] t+1: pc <- temp exceptions: none chapter 27 cpu instruction set details 592 lb load byte lb base lb 1 0 0 0 0 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: lb rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the contents of the byte at the memory location specified by the effective address are sign-extended and loaded into general register rt . operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15..0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1..3 || (paddr 2..0 xor reverseendian 3 ) mem <- loadmemory (uncached, byte, paddr, vaddr, data) byte <- vaddr 2..0 xor bigendiancpu 3 gpr [rt] <- (mem 7 + 8* byte ) 24 || mem 7 + 8* byte..8* byte 64 t: vaddr <- ((offset 15 ) 48 || offset 15..0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1..3 || (paddr 2..0 xor reverseendian 3 ) mem <- loadmemory (uncached, byte, paddr, vaddr, data) byte <- vaddr 2..0 xor bigendiancpu 3 gpr [rt] <- (mem 7 + 8* byte ) 56 || mem 7 + 8* byte..8* byte exceptions: tlb refill exception tlb invalid exception bus error exception address error exception chapter 27 cpu instruction set details 593 lbu load byte unsigned lbu base lbu 1 0 0 1 0 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: lbu rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the contents of the byte at the memory location specified by the effective address are zero-extended and loaded into general register rt . operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15..0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1..3 || (paddr 2..0 xor reverseendian 3 ) mem <- loadmemory (uncached, byte, paddr, vaddr, data) byte <- vaddr 2..0 xor bigendiancpu 3 gpr [rt] <- 0 24 || mem 7 + 8* byte..8* byte 64 t: vaddr <- ((offset 15 ) 48 || offset 15..0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1..3 || (paddr 2..0 xor reverseendian 3 ) mem <- loadmemory (uncached, byte, paddr, vaddr, data) byte <- vaddr 2..0 xor bigendiancpu 3 gpr [rt] <- 0 56 || mem 7 + 8* byte..8* byte exceptions: tlb refill exception tlb invalid exception bus error exception address error exception chapter 27 cpu instruction set details 594 ld load doubleword ld base ld 1 1 0 1 1 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: ld rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the contents of the 64-bit doubleword at the memory location specified by the effective address are loaded into general register rt . if any of the three least-significant bits of the effective address are non-zero, an address error exception occurs. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: vaddr <- ((offset 15 ) 48 || offset 15..0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) data <- loadmemory (uncached, doubleword, paddr, vaddr, data) gpr [rt] <- data exceptions: tlb refill exception tlb invalid exception bus error exception address error exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 595 ldl load doubleword left ldl base ldl 0 1 1 0 1 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: ldl rt, offset (base) description: this instruction can be used in combination with the ldr instruction to load a register with eight consecutive bytes from memory, when the bytes cross a doubleword boundary. ldl loads the left portion of the register with the appropriate part of the high-order doubleword; ldr loads the right portion of the register with the appropriate part of the low-order doubleword. the ldl instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte. it reads bytes only from the doubleword in memory which contains the specified starting byte. from one to eight bytes will be loaded, depending on the starting byte specified. conceptually, it starts at the specified byte in memory and loads that byte into the high-order (left-most) byte of the register; then it loads bytes from memory into the register until it reaches the low-order byte of the doubleword in memory. the least-significant (right-most) byte(s) of the register will not be changed. address 8 address 0 memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a b c d e f g h 12 11 10 9 8 f g h before after $24 $24 register ldl $24, 12 ($0) chapter 27 cpu instruction set details 596 ldl load doubleword left ldl (continued) the contents of general register rt are internally bypassed within the processor so that no nop is needed between an immediately preceding load instruction which specifies register rt and a following ldl (or ldr) instruction which also specifies register rt . no address error exceptions due to alignment are possible. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: vaddr <- ((offset 15 ) 48 || offset 15..0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1..3 || (paddr 2..0 xor reverseendian 3 ) if bigendianmem = 0 then paddr <- paddr psize - 1..3 || 0 3 endif byte <- vaddr 2..0 xor bigendiancpu 3 mem <- loadmemory (uncached, byte, paddr, vaddr, data) gpr [rt] <- mem 7 + 8* byte..0 || gpr [rt] 55 - 8* byte..0 chapter 27 cpu instruction set details 597 ldl load doubleword left ldl (continued) given a doubleword in a register and a doubleword in memory, the operation of ldl is as follows: b c d e f g a h j k l m n o i p register memory ldl vaddr 2..0 bigendiancpu = 0 destination type offset (lem) 0 1 2 3 4 5 6 7 pbcdefgh opcde fgh nopde fgh mnop e f gh lmnopfgh klmnopgh jklmnoph ijklmnop 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 lem little-endian memory (bigendianmem = 0) type accesstype (see table 3-2) sent to memory offset paddr 2..0 sent to memory exceptions: tlb refill exception tlb invalid exception bus error exception address error exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 598 ldr load doubleword right ldr base ldr 0 1 1 0 1 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: ldr rt, offset (base) description: this instruction can be used in combination with the ldl instruction to load a register with eight consecutive bytes from memory, when the bytes cross a doubleword boundary. ldr loads the right portion of the register with the appropriate part of the low-order doubleword; ldl loads the left portion of the register with the appropriate part of the high-order doubleword. the ldr instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte. it reads bytes only from the doubleword in memory which contains the specified starting byte. from one to eight bytes will be loaded, depending on the starting byte specified. conceptually, it starts at the specified byte in memory and loads that byte into the low-order (right-most) byte of the register; then it loads bytes from memory into the register until it reaches the high-order byte of the doubleword in memory. the most significant (left-most) byte(s) of the register will not be changed. address 8 address 0 memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a b c d e f g h a b c d e 7 6 5 before after $24 $24 register ldr $24, 5 ($0) register chapter 27 cpu instruction set details 599 ldr load doubleword right ldr (continued) the contents of general register rt are internally bypassed within the processor so that no nop is needed between an immediately preceding load instruction which specifies register rt and a following ldr (or ldl) instruction which also specifies register rt . no address error exceptions due to alignment are possible. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: vaddr <- ((offset 15 ) 48 || offset 15..0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1..3 || (paddr 2..0 xor reverseendian 3 ) if bigendianmem = 1 then paddr <- paddr psize - 1..3 || 0 3 endif byte <- vaddr 2..0 xor bigendiancpu 3 mem <- loadmemory (uncached, doubleword-byte, paddr, vaddr, data) gpr [rt] <- gpr [rt] 63..64 C 8 * byte || mem 63..8 * byte chapter 27 cpu instruction set details 600 ldr load doubleword right ldr (continued) given a doubleword in a register and a doubleword in memory, the operation of ldr is as follows: b c d e f g a h j k l m n o i p register memory ldr vaddr 2..0 bigendiancpu = 0 destination type offset (lem) 0 1 2 3 4 5 6 7 ijklmnop aijklmno ab i jklmn abc i jklm abcd i jkl abcde i jk abcdef i j abcdefg i 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 lem little-endian memory (bigendianmem = 0) type accesstype (see table 3-2) sent to memory offset paddr 2..0 sent to memory exceptions: tlb refill exception tlb invalid exception bus error exception address error exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 601 lh load halfword lh base lh 1 0 0 0 0 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: lh rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the contents of the halfword at the memory location specified by the effective address are sign-extended and loaded into general register rt . if the least-significant bit of the effective address is non-zero, an address error exception occurs. operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian 2 || 0)) mem <- loadmemory (uncached, halfword, paddr, vaddr, data) byte <- vaddr 2...0 xor (bigendiancpu 2 || 0) gpr [rt] <- (mem 15 + 8 * byte ) 16 || mem 15 + 8 * byte...8 * byte 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian 2 || 0)) mem <- loadmemory (uncached, halfword, paddr, vaddr, data) byte <- vaddr 2...0 xor (bigendiancpu 2 || 0) gpr [rt] <- (mem 15 + 8 * byte ) 48 || mem 15 + 8 * byte...8 * byte exceptions: tlb refill exception tlb invalid exception bus error exception address error exception chapter 27 cpu instruction set details 602 lhu load halfword unsigned lhu base lhu 1 0 0 1 0 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: lhu rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the contents of the halfword at the memory location specified by the effective address are zero-extended and loaded into general register rt . if the least-significant bit of the effective address is non-zero, an address error exception occurs. operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian 2 || 0)) mem <- loadmemory (uncached, halfword, paddr, vaddr, data) byte <- vaddr 2...0 xor (bigendiancpu 2 || 0) gpr [rt] <- 0 16 || mem 15 + 8 * byte...8 * byte 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian 2 || 0)) mem <- loadmemory (uncached, halfword, paddr, vaddr, data) byte <- vaddr 2...0 xor (bigendiancpu 2 || 0) gpr [rt] <- 0 48 || mem 15 + 8 * byte...8 * byte exceptions: tlb refill exception tlb invalid exception bus error exception address error exception chapter 27 cpu instruction set details 603 lui load upper immediate lui 0 0 0 0 0 0 lui 0 0 1 1 1 1 rt immediate 31 26 25 21 20 16 15 0 655 16 format: lui rt, immediate description: the 16-bit immediate is shifted left 16 bits and concatenated to 16 bits of zeros. the result is placed into general register rt . in 64-bit mode, the loaded word is sign-extended. operation: 32 t: gpr [rt] <- immediate || 0 16 64 t: gpr [rt] <- (immediate 15 ) 32 || immediate || 0 16 exceptions: none chapter 27 cpu instruction set details 604 lw load word lw base lw 1 0 0 0 1 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: lw rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the contents of the word at the memory location specified by the effective address are loaded into general register rt . in 64-bit mode, the loaded word is sign-extended. if either of the two least-significant bits of the effective address is non-zero, an address error exception occurs. operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian || 0 2 )) mem <- loadmemory (uncached, word, paddr, vaddr, data) byte <- vaddr 2...0 xor (bigendiancpu || 0 2 ) gpr [rt] <- mem 31 + 8 * byte...8 * byte 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian || 0 2 )) mem <- loadmemory (uncached, word, paddr, vaddr, data) byte <- vaddr 2...0 xor (bigendiancpu || 0 2 ) gpr [rt] <- (mem 31 + 8 * byte ) 32 || mem 31 + 8 * byte...8 * byte exceptions: tlb refill exception tlb invalid exception bus error exception address error exception chapter 27 cpu instruction set details 605 lwl load word left lwl base lwl 1 0 0 0 1 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: lwl rt, offset (base) description: this instruction can be used in combination with the lwr instruction to load a register with four consecutive bytes from memory, when the bytes cross a word boundary. lwl loads the left portion of the register with the appropriate part of the high-order word; lwr loads the right portion of the register with the appropriate part of the low-order word. the lwl instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte. it reads bytes only from the word in memory which contains the specified starting byte. from one to four bytes will be loaded, depending on the starting byte specified. in 64-bit mode, the loaded word is sign-extended. conceptually, it starts at the specified byte in memory and loads that byte into the high-order (left-most) byte of the register; then it loads bytes from memory into the register until it reaches the low-order byte of the word in memory. the least-significant (right-most) byte(s) of the register will not be changed. address 4 address 0 memory 7 6 5 4 3 2 1 0 before after $24 $24 register lwl $24, 4 ($0) a b c d 4 b c d chapter 27 cpu instruction set details 606 lwl load word left lwl (continued) the contents of general register rt are internally bypassed within the processor so that no nop is needed between an immediately preceding load instruction which specifies register rt and a following lwl (or lwr) instruction which also specifies register rt . no address error exceptions due to alignment are possible. operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 0 then paddr <- paddr psize - 1...2 || 0 2 endif byte <- vaddr 1...0 xor bigendiancpu 2 word <- vaddr 2 xor bigendiancpu mem <- loadmemory (uncached, byte, paddr, vaddr, data) temp <- mem 32 * word + 8 * byte + 7...32 * word || gpr [rt] 23 C 8 * byte...0 gpr [rt] <- temp 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 0 then paddr <- paddr psize - 1...2 || 0 2 endif byte <- vaddr 1...0 xor bigendiancpu 2 word <- vaddr 2 xor bigendiancpu mem <- loadmemory (uncached, 0 || byte, paddr, vaddr, data) temp <- mem 32 * word + 8 * byte + 7...32 * word || gpr [rt] 23 C 8 * byte...0 gpr [rt] <- (temp 31 ) 32 || temp chapter 27 cpu instruction set details 607 lwl load word left lwl (continued) given a doubleword in a register and a doubleword in memory, the operation of lwl is as follows: b c d e f g a h j k l m n o i p register memory lwl vaddr 2..0 bigendiancpu = 0 destination type offset (lem) 0 1 2 3 4 5 6 7 sssspfgh ssssopgh ssssnoph ssssmnop sssslfgh ssssklgh ssssjklh ssss i jkl 0 1 2 3 0 1 2 3 0 0 0 0 4 4 4 4 lem little-endian memory (bigendianmem = 0) type accesstype (see table 3-2) sent to memory offset paddr 2...0 sent to memory s sign-extend of destination 31 exceptions: tlb refill exception tlb invalid exception bus error exception address error exception chapter 27 cpu instruction set details 608 lwr load word right lwr base lwr 1 0 0 1 1 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: lwr rt, offset (base) description: this instruction can be used in combination with the lwl instruction to load a register with four consecutive bytes from memory, when the bytes cross a word boundary. lwr loads the right portion of the register with the appropriate part of the low-order word; lwl loads the left portion of the register with the appropriate part of the high-order word. the lwr instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte. it reads bytes only from the word in memory which contains the specified starting byte. from one to four bytes will be loaded, depending on the starting byte specified. in 64-bit mode, the loaded word is sign-extended. conceptually, it starts at the specified byte in memory and loads that byte into the low-order (right-most) byte of the register; then it loads bytes from memory into the register until it reaches the high-order byte of the word in memory. the most significant (left-most) byte(s) of the register will not be changed. address 4 address 0 memory 7 6 5 4 3 2 1 0 before after $24 register lwr $24, 1 ($0) a b c d a 3 2 1 $24 chapter 27 cpu instruction set details 609 lwr load word right lwr (continued) the contents of general register rt are internally bypassed within the processor so that no nop is needed between an immediately preceding load instruction which specifies register rt and a following lwr (or lwl) instruction which also specifies register rt . no address error exceptions due to alignment are possible. operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 1 then paddr <- paddr psize - 1...3 || 0 3 endif byte <- vaddr 1...0 xor bigendiancpu 2 word <- vaddr 2 xor bigendiancpu mem <- loadmemory (uncached, 0 || byte, paddr, vaddr, data) temp <- gpr [rt] 31...32 C 8 * byte || mem 31 + 32 * word...32 * word + 8 * byte gpr [rt] <- temp 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 1 then paddr <- paddr psize - 1...3 || 0 3 endif byte <- vaddr 1...0 xor bigendiancpu 2 word <- vaddr 2 xor bigendiancpu mem <- loadmemory (uncached, word-byte, paddr, vaddr, data) temp <- gpr [rt] 31...32 C 8 * byte || mem 31 + 32 * word...32 * word + 8 * byte gpr [rt] <- (temp 31 ) 32 || temp chapter 27 cpu instruction set details 610 lwr load word right lwr (continued) given a word in a register and a word in memory, the operation of lwr is as follows: b c d e f g a h j k l m n o i p register memory lwr vaddr 2..0 bigendiancpu = 0 destination type offset (lem) 0 1 2 3 4 5 6 7 ssssmnop ssssemno ssssefmn ssssefgm ssss i jkl sssse i jk ssssef i j ssssefg i 3 2 1 0 3 2 1 0 0 1 2 3 4 5 6 7 lem little-endian memory (bigendianmem = 0) type accesstype (see table 3-2) sent to memory offset paddr 2...0 sent to memory s sign-extend of destination 31 exceptions: tlb refill exception tlb invalid exception bus error exception address error exception chapter 27 cpu instruction set details 611 lwu load word unsigned lwu base lwu 1 0 1 1 1 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: lwu rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the contents of the word at the memory location specified by the effective address are loaded into general register rt . the loaded word is zero-extended. if either of the two least-significant bits of the effective address is non-zero, an address error exception occurs. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian || 0 2 )) mem <- loadmemory (uncached, word, paddr, vaddr, data) byte <- vaddr 2...0 xor (bigendiancpu || 0 2 ) gpr [rt] <- 0 32 || mem 31 + 8 * byte...8 * byte 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian || 0 2 )) mem <- loadmemory (uncached, word, paddr, vaddr, data) byte <- vaddr 2...0 xor (bigendiancpu || 0 2 ) gpr [rt] <- 0 32 || mem 31 + 8 * byte...8 * byte exceptions: tlb refill exception tlb invalid exception bus error exception address error exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 612 madd16 multiply and add 16-bit integer madd16 rs special 0 0 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 655 10 dmadd16 1 0 1 0 0 0 65 6 format: madd16 rs, rt description: the contents of general registers rs and rt are multiplied, treating both operands as 16-bit 2s complement values. the operand[62:15] must be valid 15-bit, sign-extended values. if not, the results is unpredictable. this multiplied result and the 64-bit data joined special register hi to lo are added to form the result. no integer overflow exception occurs under any circumstances. when the operation completes, the low-order word of the double result is loaded into special register lo , and the high-order word of the double result is loaded into special register hi . the following table are hazard cycles between madd16 and other instructions. instruction sequence no. of cycles mult/multu -> madd16 1 cycle dmult/dmultu -> madd16 4 cycles div/divu -> madd16 36 cycles ddiv/ddivu -> madd16 68 cycles mfhi/mflo -> madd16 2 cycles dmadd16 -> madd16 0 cycles madd16 -> madd16 0 cycles operation: 32, 64 t: temp1<- gpr [rs] * gpr [rt] temp2<- temp1 + (hi 31...0 || lo 31...0 ) lo <- (temp1 31 ) 32 || temp2 31...0 hi <- (temp2 63 ) 32 || temp2 63...32 exceptions: none chapter 27 cpu instruction set details 613 mfc0 move from system control coprocessor mfc0 mf 0 0 0 0 0 cop0 0 1 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 555 11 10 11 rd format: mfc0 rt, rd description: the contents of coprocessor register rd of the cp0 are loaded into general register rt. when using a register used by the mfc0 by means of instructions before and after it, refer to chapter 28 and place the instructions in the appropriate location. operation: 32 t: data <- cpr [0, rd] t+1: gpr [rt] <- data 64 t: data <- cpr [0, rd] t+1: gpr [rt] <- (data 31 ) 32 || data 31...0 exceptions: coprocessor unusable exception (user and supervisor mode if cp0 not enabled) chapter 27 cpu instruction set details 614 mfhi move from hi mfhi 0 0 0 0 0 0 0 0 0 0 0 special 0 0 0 0 0 0 31 26 25 11 10 16 15 0 610 56 rd 0 0 0 0 0 0 mfhi 0 1 0 0 0 0 5 65 format: mfhi rd description: the contents of special register hi are loaded into general register rd . to ensure proper operation in the event of interruptions, the two instructions which follow a mfhi instruction may not be any of the instructions which modify the hi register: mult, multu, div, divu, mthi, dmult, dmultu, ddiv, ddivu. operation: 32, 64 t: gpr [rd] <- hi exceptions: none chapter 27 cpu instruction set details 615 mflo move from lo mflo 0 0 0 0 0 0 0 0 0 0 0 special 0 0 0 0 0 0 31 26 25 11 10 16 15 0 610 56 rd 0 0 0 0 0 0 mflo 0 1 0 0 1 0 5 65 format: mflo rd description: the contents of special register lo are loaded into general register rd . to ensure proper operation in the event of interruptions, the two instructions which follow a mflo instruction may not be any of the instructions which modify the lo register: mult, multu, div, divu, mtlo, dmult, dmultu, ddiv, ddivu. operation: 32, 64 t: gpr [rd] <- lo exceptions: none chapter 27 cpu instruction set details 616 mtc0 move to coprocessor0 mtc0 0 0 0 0 0 0 0 0 0 0 0 0 cop0 0 1 0 0 0 0 31 26 25 11 10 16 15 0 6 11 5 5 rt rd mt 0 0 1 0 0 5 21 20 format: mtc0 rt, rd description: the contents of general register rt are loaded into coprocessor register rd of coprocessor 0. because the state of the virtual address translation system may be altered by this instruction, the operation of load instructions, store instructions, and tlb operations immediately prior to and after this instruction are undefined. when using a register used by the mtc0 by means of instructions before and after it, refer to chapter 28 and place the instructions in the appropriate location. operation: 32, 64 t: data <- gpr [rt] t+1: cpr [0, rd] <- data exceptions: coprocessor unusable exception (user and supervisor mode if cp0 not enabled) chapter 27 cpu instruction set details 617 mthi move to hi mthi rs special 0 0 0 0 0 0 mthi 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 65 6 15 format: mthi rs description: the contents of general register rs are loaded into special register hi . if a mthi operation is executed following a mult, multu, div, or divu instruction, but before any mflo, mfhi, mtlo, or mthi instructions, the contents of special register hi are undefined. operation: 32, 64 t-2: hi <- undefined t-1: hi <- undefined t: hi <- gpr [rs] exceptions: none chapter 27 cpu instruction set details 618 mtlo move to lo mtlo rs special 0 0 0 0 0 0 mtlo 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 65 6 15 format: mtlo rs description: the contents of general register rs are loaded into special register lo. if an mtlo operation is executed following a mult, multu, div, or divu instruction, but before any mflo, mfhi, mtlo, or mthi instructions, the contents of special register lo are undefined. operation: 32, 64 t-2: lo <- undefined t-1: lo <- undefined t: lo <- gpr [rs] exceptions: none chapter 27 cpu instruction set details 619 mult multiply mult rs special 0 0 0 0 0 0 mult 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 65 6 10 rt 5 16 15 format: mult rs, rt description: the contents of general registers rs and rt are multiplied, treating both operands as 32-bit 2s complement values. no integer overflow exception occurs under any circumstances. in 64-bit mode, the operands must be valid 32- bit, sign-extended values. when the operation completes, the low-order word of the double result is loaded into special register lo , and the high-order word of the double result is loaded into special register hi . if either of the two preceding instructions is mfhi or mflo, the results of these instructions are undefined. correct operation requires separating reads of hi or lo from writes by a minimum of two other instructions. operation: 32 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: t <- gpr [rs] * gpr [rt] lo <- t 31...0 hi <- t 63...32 64 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: t <- gpr [rs] 31...0 * gpr [rt] 31...0 lo <- (t 31 ) 32 || t 31...0 hi <- (t 63 ) 32 || t 63...32 exceptions: none chapter 27 cpu instruction set details 620 multu multiply unsigned multu rs special 0 0 0 0 0 0 multu 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 6 5 0 65 6 10 rt 5 16 15 format: multu rs, rt description: the contents of general register rs and the contents of general register rt are multiplied, treating both operands as unsigned values. no overflow exception occurs under any circumstances. in 64-bit mode, the operands must be valid 32-bit, sign-extended values. when the operation completes, the low-order word of the double result is loaded into special register lo , and the high-order word of the double result is loaded into special register hi . if either of the two preceding instructions is mfhi or mflo, the results of these instructions are undefined. correct operation requires separating reads of hi or lo from writes by a minimum of two instructions. operation: 32 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: t <- (0 || gpr [rs]) * (0 || gpr [rt]) lo <- t 31...0 hi <- t 63...32 64 t-2: lo <- undefined hi <- undefined t-1: lo <- undefined hi <- undefined t: t <- (0 || gpr [rs] 31...0 ) * (0 || gpr [rt] 31...0 ) lo <- (t 31 ) 32 || t 31...0 hi <- (t 63 ) 32 || t 63...32 exceptions: none chapter 27 cpu instruction set details 621 n o r nor n o r rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 nor 1 0 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: nor rd, rs, rt description: the contents of general register rs are combined with the contents of general register rt in a bit-wise logical nor operation. the result is placed into general register rd . operation: 32, 64 t: gpr [rd] <- gpr [rs] nor gpr [rt] exceptions: none chapter 27 cpu instruction set details 622 o r or o r rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 or 1 0 0 1 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: or rd, rs, rt description: the contents of general register rs are combined with the contents of general register rt in a bit-wise logical or operation. the result is placed into general register rd . operation: 32, 64 t: gpr [rd] <- gpr [rs] or gpr [rt] exceptions: none chapter 27 cpu instruction set details 623 ori or immediate ori rs ori 0 0 1 1 0 1 rt immediate 31 26 25 21 20 16 15 0 655 16 format: ori rt, rs, immediate description: the 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical or operation. the result is placed into general register rt . operation: 32 t: gpr [rt] <- gpr [rs] 31...16 || (immediate or gpr [rs] 15...0 ) 64 t: gpr [rt] <- gpr [rs] 63...16 || (immediate or gpr [rs] 15...0 ) exceptions: none chapter 27 cpu instruction set details 624 sb store byte sb base sb 1 0 1 0 0 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: sb rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the least-significant byte of register rt is stored at the effective address. operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian 3 )) byte <- vaddr 2...0 xor bigendiancpu 3 data <- gpr [rt] 63 C 8 * byte...0 || 0 8 * byte storememory (uncached, byte, data, paddr, vaddr, data) 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian 3 )) byte <- vaddr 2...0 xor bigendiancpu 3 data <- gpr [rt] 63 C 8 * byte...0 || 0 8 * byte storememory (uncached, byte, data, paddr, vaddr, data) exceptions: tlb refill exception tlb invalid exception tlb modification exception bus error exception address error exception chapter 27 cpu instruction set details 625 sd store doubleword sd base sd 1 1 1 1 1 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: sd rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the contents of general register rt are stored at the memory location specified by the effective address. if either of the three least-significant bits of the effective address are non-zero, an address error exception occurs. this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) data <- gpr [rt] storememory (uncached, doubleword, data, paddr, vaddr, data) exceptions: tlb refill exception tlb invalid exception tlb modification exception bus error exception address error exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 626 sdl store doubleword left sdl base sdl 1 0 1 1 0 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: sdl rt, offset (base) description: this instruction can be used with the sdr instruction to store the contents of a register into eight consecutive bytes of memory, when the bytes cross a doubleword boundary. sdl stores the left portion of the register into the appropriate part of the high-order doubleword of memory; sdr stores the right portion of the register into the appropriate part of the low-order doubleword. the sdl instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte. it alters only the word in memory which contains that byte. from one to four bytes will be stored, depending on the starting byte specified. conceptually, it starts at the most-significant byte of the register and copies it to the specified byte in memory; then it copies bytes from register to memory until it reaches the low-order byte of the word in memory. no address error exceptions due to alignment are possible. address 8 address 0 memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a b c d e f g h before after $24 register sdl $24, 8 ($0) address 8 address 0 15 14 13 12 11 10 9 a 7 6 5 4 3 2 1 0 chapter 27 cpu instruction set details 627 sdl store doubleword left sdl (continued) this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 0 then paddr <- paddr psize - 1...3 || 0 3 endif byte <- vaddr 2...0 xor bigendiancpu 3 data <- 0 56 C 8 * byte || gpr [rt] 63...56 C 8 * byte storememory (uncached, byte, data, paddr, vaddr, data) chapter 27 cpu instruction set details 628 sdl store doubleword left sdl (continued) given a doubleword in a register and a doubleword in memory, the operation of sdl is as follows: b c d e f g a h j k l m n o i p register memory sdl vaddr 2..0 bigendiancpu = 0 destination type offset (lem) 0 1 2 3 4 5 6 7 ijklmnoa ijklmnab ijklmabc ijklabcd i jkabcde ijabcdef i abcdefg abcdefgh 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 lem little-endian memory (bigendianmem = 0) type accesstype (see table 3-2) sent to memory offset paddr 2...0 sent to memory exceptions: tlb refill exception tlb invalid exception tlb modification exception bus error exception address error exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 629 sdr store doubleword right sdr base sdr 1 0 1 1 0 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: sdr rt, offset (base) description: this instruction can be used with the sdl instruction to store the contents of a register into eight consecutive bytes of memory, when the bytes cross a boundary between two doublewords. sdr stores the right portion of the register into the appropriate part of the low-order doubleword; sdl stores the left portion of the register into the appropriate part of the low-order doubleword of memory. the sdr instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte. it alters only the word in memory which contains that byte. from one to eight bytes will be stored, depending on the starting byte specified. conceptually, it starts at the least-significant (rightmost) byte of the register and copies it to the specified byte in memory; then it copies bytes from register to memory until it reaches the high-order byte of the word in memory. no address error exceptions due to alignment are possible. address 8 address 0 memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a b c d e f g h before after $24 register sdr $24, 1 ($0) address 8 address 0 15 14 13 12 11 10 9 8 b c d e f g h 0 chapter 27 cpu instruction set details 630 sdr store doubleword right sdr (continued) this operation is only defined for the v r 4102 operating in 64-bit mode. execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. operation: 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 0 then paddr <- paddr psize - 1...3 || 0 3 endif byte <- vaddr 2...0 xor bigendiancpu 3 data <- gpr [rt] 63 C 8 * byte || 0 8 * byte storememory (uncached, doubleword-byte, data, paddr, vaddr, data) chapter 27 cpu instruction set details 631 sdr store doubleword right sdr (continued) given a doubleword in a register and a doubleword in memory, the operation of sdr is as follows: b c d e f g a h j k l m n o i p register memory sdr vaddr 2..0 bigendiancpu = 0 destination type offset (lem) 0 1 2 3 4 5 6 7 abcdefgh bcdefghp cdefghop defghnop efghmnop fghlmnop ghk lmnop hjklmnop 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 lem little-endian memory (bigendianmem = 0) type accesstype (see table 2-2) sent to memory offset paddr 2...0 sent to memory exceptions: tlb refill exception tlb invalid exception tlb modification exception bus error exception address error exception reserved instruction exception (v r 4102 in 32-bit user mode, v r 4102 in 32-bit supervisor mode) chapter 27 cpu instruction set details 632 sh store halfword sh base sh 1 0 1 0 0 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: sh rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form an unsigned effective address. the least-significant halfword of register rt is stored at the effective address. if the least- significant bit of the effective address is non-zero, an address error exception occurs. operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian 2 || 0)) byte <- vaddr 2...0 xor (bigendiancpu 2 || 0) data <- gpr [rt] 63 C 8 * byte...0 || 0 8 * byte storememory (uncached, halfword, data, paddr, vaddr, data) 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian 2 || 0)) byte <- vaddr 2...0 xor (bigendiancpu 2 || 0) data <- gpr [rt] 63 C 8 * byte...0 || 0 8 * byte storememory (uncached, halfword, data, paddr, vaddr, data) exceptions: tlb refill exception tlb invalid exception tlb modification exception bus error exception address error exception chapter 27 cpu instruction set details 633 sll shift left logical sll 0 0 0 0 0 0 special 0 0 0 0 0 0 rt rd sa sll 0 0 0 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: sll rd, rt, sa description: the contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits. the result is placed in register rd. in 64-bit mode, the 32-bit result is sign-extended when placed in the destination register. it is sign extended for all shift amounts, including zero; sll with zero shift amount truncates a 64-bit value to 32 bits and then sign extends this 32-bit value. sll, unlike nearly all other word operations, does not require an operand to be a properly sign-extended word value to produce a valid sign-extended word result. operation: 32 t: gpr [rd] <- gpr [rt] 31 - sa...0 || 0 sa 64 t: s <- 0 || sa temp <- gpr [rt] 31 - s...0 || 0 s gpr [rd] <- (temp 31 ) 32 || temp exceptions: none remark sll with a shift amount of zero may be treated as a nop by some assemblers, at some optimization levels. if using sll with a zero shift to truncate 64-bit values, check the assembler you are using. chapter 27 cpu instruction set details 634 sllv shift left logical variable sllv rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 sllv 0 0 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: sllv rd, rt, rs description: the contents of general register rt are shifted left the number of bits specified by the low-order five bits contained in general register rs , inserting zeros into the low-order bits. the result is placed in register rd . in 64-bit mode, the 32-bit result is sign-extended when placed in the destination register. it is sign extended for all shift amounts, including zero; sllv with zero shift amount truncates a 64-bit value to 32 bits and then sign extends this 32-bit value. sllv, unlike nearly all other word operations, does not require an operand to be a properly sign-extended word value to produce a valid sign-extended word result. operation: 32 t: s <- gpr [rs] 4...0 gpr [rd] <- gpr [rt] (31 - s)...0 || 0 s 64 t: s <- 0 || gpr [rs] 4...0 temp <- gpr [rt] (31 - s)...0 || 0 s gpr [rd] <- (temp 31 ) 32 || temp exceptions: none remark sllv with a shift amount of zero may be treated as a nop by some assemblers, at some optimization levels. if using sllv with a zero shift to truncate 64-bit values, check the assembler you are using. chapter 27 cpu instruction set details 635 s lt set on less than s lt rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 slt 1 0 1 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: slt rd, rs, rt description: the contents of general register rt are subtracted from the contents of general register rs . considering both quantities as signed integers, if the contents of general register rs are less than the contents of general register rt , the result is set to one; otherwise the result is set to zero. the result is placed into general register rd . no integer overflow exception occurs under any circumstances. the comparison is valid even if the subtraction used during the comparison overflows. operation: 32 t: if gpr [rs] < gpr [rt] then gpr [rd] <- 0 31 || 1 else gpr [rd] <- 0 32 endif 64 t: if gpr [rs] < gpr [rt] then gpr [rd] <- 0 63 || 1 else gpr [rd] <- 0 64 endif exceptions: none chapter 27 cpu instruction set details 636 slti set on less than immediate slti rs slti 0 0 1 0 1 0 rt immediate 31 26 25 21 20 16 15 0 655 16 format: slti rt, rs, immediate description: the 16-bit immediate is sign-extended and subtracted from the contents of general register rs. considering both quantities as signed integers, if rs is less than the sign-extended immediate, the result is set to one; otherwise the result is set to zero. the result is placed into general register rt. no integer overflow exception occurs under any circumstances. the comparison is valid even if the subtraction used during the comparison overflows. operation: 32 t: if gpr [rs] < (immediate 15 ) 16 || immediate 15...0 then gpr [rt] <- 0 31 || 1 else gpr [rt] <- 0 32 endif 64 t: if gpr [rs] < (immediate 15 ) 48 || immediate 15...0 then gpr [rt] <- 0 63 || 1 else gpr [rt] <- 0 64 endif exceptions: none chapter 27 cpu instruction set details 637 sltiu set on less than immediate unsigned sltiu rs sltiu 0 0 1 0 1 1 rt immediate 31 26 25 21 20 16 15 0 655 16 format: sltiu rt, rs, immediate description: the 16-bit immediate is sign-extended and subtracted from the contents of general register rs. considering both quantities as unsigned integers, if rs is less than the sign-extended immediate, the result is set to one; otherwise the result is set to zero. the result is placed into general register rt . no integer overflow exception occurs under any circumstances. the comparison is valid even if the subtraction used during the comparison overflows. operation: 32 t: if (0 || gpr [rs]) < (0 || (immediate 15 ) 16 || immediate 15...0 ) then gpr [rt] <- 0 31 || 1 else gpr [rt] <- 0 32 endif 64 t: if (0 || gpr [rs]) < (0 || (immediate 15 ) 48 || immediate 15...0 ) then gpr [rt] <- 0 63 || 1 else gpr [rt] <- 0 64 endif exceptions: none chapter 27 cpu instruction set details 638 sltu set on less than unsigned sltu rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 sltu 1 0 1 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: sltu rd, rs, rt description: the contents of general register rt are subtracted from the contents of general register rs. considering both quantities as unsigned integers, if the contents of general register rs are less than the contents of general register rt , the result is set to one; otherwise the result is set to zero. the result is placed into general register rd . no integer overflow exception occurs under any circumstances. the comparison is valid even if the subtraction used during the comparison overflows. operation: 32 t: if (0 || gpr [rs]) < 0 || gpr [rt] then gpr [rd] <- 0 31 || 1 else gpr [rd] <- 0 32 endif 64 t: if (0 || gpr [rs]) < 0 || gpr [rt] then gpr [rd] <- 0 63 || 1 else gpr [rd] <- 0 64 endif exceptions: none chapter 27 cpu instruction set details 639 sra shift right arithmetic sra 0 0 0 0 0 0 special 0 0 0 0 0 0 rt rd sa sra 0 0 0 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: sra rd, rt, sa description: the contents of general register rt are shifted right by sa bits, sign-extending the high-order bits. the result is placed in register rd . in 64-bit mode, the operand must be a valid sign-extended, 32-bit value. operation: 32 t: gpr [rd] <- (gpr [rt] 31 ) sa || gpr [rt] 31...sa 64 t: s <- 0 || sa temp <- (gpr [rt] 31 ) s || gpr [rt] 31...s gpr [rd] <- (temp 31 ) 32 || temp exceptions: none chapter 27 cpu instruction set details 640 srav shift right arithmetic variable srav rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 srav 0 0 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 655556 format: srav rd, rt, rs description: the contents of general register rt are shifted right by the number of bits specified by the low-order five bits of general register rs , sign-extending the high-order bits. the result is placed in register rd . in 64-bit mode, the operand must be a valid sign-extended, 32-bit value. operation: 32 t: s <- gpr [rs] 4...0 gpr [rd] <- (gpr [rt] 31 ) s || gpr [rt] 31...s 64 t: s <- gpr [rs] 4...0 temp <- (gpr [rt] 31 ) s || gpr [rt] 31...s gpr [rd] <- (temp 31 ) 32 || temp exceptions: none chapter 27 cpu instruction set details 641 srl shift right logical srl 0 0 0 0 0 0 special 0 0 0 0 0 0 rt rd sa srl 0 0 0 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: srl rd, rt, sa description: the contents of general register rt are shifted right by sa bits, inserting zeros into the high-order bits. the result is placed in register rd . in 64-bit mode, the operand must be a valid sign-extended, 32-bit value. operation: 32 t: gpr [rd] <- 0 sa || gpr [rt] 31...sa 64 t: s <- 0 || sa temp <- 0 s || gpr [rt] 31...s gpr [rd] <- (temp 31 ) 32 || temp exceptions: none chapter 27 cpu instruction set details 642 srlv shift right logical variable srlv rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 srlv 0 0 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: srlv rd, rt, rs description: the contents of general register rt are shifted right by the number of bits specified by the low-order five bits of general register rs, inserting zeros into the high-order bits. the result is placed in register rd . in 64-bit mode, the operand must be a valid sign-extended, 32-bit value. operation: 32 t: s <- gpr [rs] 4...0 gpr [rd] <- 0 s || gpr [rt] 31...s 64 t: s <- gpr [rs] 4...0 temp <- 0 s || gpr [rt] 31...s gpr [rd] <- (temp 31 ) 32 || temp exceptions: none chapter 27 cpu instruction set details 643 standby standby standby 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cop0 0 1 0 0 0 0 standby 1 0 0 0 0 1 31 26 25 6 5 0 6196 co 1 1 24 format: standby description: standby instruction starts mode transition from fullspeed mode to standby mode. when the standby instruction finishes the wb stage, the v r 4102 wait by the sysad bus is idle state, after then the internal clocks will shut down, thus freezing the pipeline. the pll, timer/interrupt clocks and the internal bus clocks (tclock and masterout) will continue to run. once the v r 4102 is in standby mode, any interrupt, including the internally generated timer interrupt, nmi, soft reset, and cold reset will cause the v r 4102 to exit standby mode and to enter fullspeed mode. operation: 32, 64 t: t+1: standby operation () exceptions: coprocessor unusable exception remark refer to chapter 15 for details about the operation of the peripheral units at mode transition. chapter 27 cpu instruction set details 644 sub subtract sub rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 sub 1 0 0 0 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: sub rd, rs, rt description: the contents of general register rt are subtracted from the contents of general register rs to form a result. the result is placed into general register rd. in 64-bit mode, the operands must be valid sign-extended, 32-bit values. the only difference between this instruction and the subu instruction is that subu never traps on overflow. an integer overflow exception takes place if the carries out of bits 30 and 31 differ (2s complement overflow). the destination register rd is not modified when an integer overflow exception occurs. operation: 32 t: gpr [rd] <- gpr [rs] - gpr [rt] 64 t: temp <- gpr [rs] - gpr [rt] gpr [rd] <- (temp 31 ) 32 || temp 31...0 exceptions: integer overflow exception chapter 27 cpu instruction set details 645 subu subtract unsigned subu rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 subu 1 0 0 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: subu rd, rs, rt description: the contents of general register rt are subtracted from the contents of general register rs to form a result. the result is placed into general register rd . in 64-bit mode, the operands must be valid sign-extended, 32-bit values. the only difference between this instruction and the sub instruction is that subu never traps on overflow. no integer overflow exception occurs under any circumstances. operation: 32 t: gpr [rd] <- gpr [rs] - gpr [rt] 64 t: temp <- gpr [rs] - gpr [rt] gpr [rd] <- (temp 31 ) 32 || temp 31...0 exceptions: none chapter 27 cpu instruction set details 646 suspend suspend suspend 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cop0 0 1 0 0 0 0 suspend 1 0 0 0 1 0 31 26 25 6 5 0 6196 co 1 1 24 format: suspend description: suspend instruction starts mode transition from fullspeed mode to suspend mode. when the suspend instruction finishes the wb stage, the v r 4102 wait by the sysad bus is idle state, after then the internal clocks including the tclock will shut down, thus freezing the pipeline. the pll, timer/interrupt clocks and masterout, will continue to run. once the v r 4102 is in suspend mode, any interrupt, including the internally generated timer interrupt, nmi, soft reset and cold reset will cause the v r 4102 to exit suspend mode and to enter fullspeed mode. operation: 32, 64 t: t+1: suspend operation () exceptions: coprocessor unusable exception remark refer to chapter 15 for details about the operation of the peripheral units at mode transition. chapter 27 cpu instruction set details 647 sw store word sw base sw 1 0 1 0 1 1 rt offset 31 26 25 21 20 16 15 0 655 16 format: sw rt, offset (base) description: the 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. the contents of general register rt are stored at the memory location specified by the effective address. if either of the two least-significant bits of the effective address are non-zero, an address error exception occurs. operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian || 0 2 )) byte <- vaddr 2...0 xor (bigendiancpu || 0 2 ) data <- gpr [rt] 63 C 8 * byte || 0 8 * byte storememory (uncached, word, data, paddr, vaddr, data) 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor (reverseendian || 0 2 )) byte <- vaddr 2...0 xor (bigendiancpu || 0 2 ) data <- gpr [rt] 63 C 8 * byte || 0 8 * byte storememory (uncached, word, data, paddr, vaddr, data) exceptions: tlb refill exception tlb invalid exception tlb modification exception bus error exception address error exception chapter 27 cpu instruction set details 648 swl store word left swl base swl 1 0 1 0 1 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: swl rt, offset (base) description: this instruction can be used with the swr instruction to store the contents of a register into four consecutive bytes of memory, when the bytes cross a word boundary. swl stores the left portion of the register into the appropriate part of the high-order word of memory; swr stores the right portion of the register into the appropriate part of the low-order word. the swl instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte. it alters only the word in memory which contains that byte. from one to four bytes will be stored, depending on the starting byte specified. conceptually, it starts at the most-significant byte of the register and copies it to the specified byte in memory; then it copies bytes from register to memory until it reaches the low-order byte of the word in memory. no address error exceptions due to alignment are possible. address 4 address 0 memory 7 6 5 4 3 2 1 0 before after $24 register swl $24, 4 ($0) a b c d address 4 address 0 7 6 5 a 3 2 1 0 chapter 27 cpu instruction set details 649 swl store word left swl (continued) operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 0 then paddr <- paddr psize - 1...2 || 0 2 endif byte <- vaddr 1...0 xor bigendiancpu 2 if (vaddr 2 xor bigendiancpu) = 0 then data <- 0 32 || 0 24 C 8 * byte || gpr [rt] 31...24 C 8 * byte else data <- 0 24 C 8 * byte || gpr [rt] 31...24 C 8 * byte || 0 32 endif storememory (uncached, byte, data, paddr, vaddr, data) 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 0 then paddr <- paddr psize - 1...2 || 0 2 endif byte <- vaddr 1...0 xor bigendiancpu 2 if (vaddr 2 xor bigendiancpu) = 0 then data <- 0 32 || 0 24 C 8 * byte || gpr [rt] 31...24 C 8 * byte else data <- 0 24 C 8 * byte || gpr [rt] 31...24 C 8 * byte || 0 32 endif storememory (uncached, byte, data, paddr, vaddr, data) chapter 27 cpu instruction set details 650 swl store word left swl (continued) given a doubleword in a register and a doubleword in memory, the operation of swl is as follows: b c d e f g a h j k l m n o i p register memory swl vaddr 2..0 bigendiancpu = 0 destination type offset (lem) 0 1 2 3 4 5 6 7 ijklmnoe ijklmnef ijklmefg ijklefgh ijkemnop ijefmnop iefgmnop efghmnop 0 1 2 3 0 1 2 3 0 0 0 0 4 4 4 4 lem little-endian memory (bigendianmem = 0) type accesstype (see table 3-2) sent to memory offset paddr 2...0 sent to memory exceptions: tlb refill exception tlb invalid exception tlb modification exception bus error exception address error exception chapter 27 cpu instruction set details 651 swr store word right swr base swr 1 0 1 1 1 0 rt offset 31 26 25 21 20 16 15 0 655 16 format: swr rt, offset (base) description: this instruction can be used with the swl instruction to store the contents of a register into four consecutive bytes of memory, when the bytes cross a boundary between two words. swr stores the right portion of the register into the appropriate part of the low-order word; swl stores the left portion of the register into the appropriate part of the low-order word of memory. the swr instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte. it alters only the word in memory which contains that byte. from one to four bytes will be stored, depending on the starting byte specified. conceptually, it starts at the least-significant (rightmost) byte of the register and copies it to the specified byte in memory; then copies bytes from register to memory until it reaches the high-order byte of the word in memory. no address error exceptions due to alignment are possible. address 4 address 0 memory 7 6 5 4 3 2 1 0 before after $24 register swr $24, 1 ($0) a b c d address 4 address 0 7 6 5 4 b c d 0 chapter 27 cpu instruction set details 652 swr store word right swr (continued) operation: 32 t: vaddr <- ((offset 15 ) 16 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 1 then paddr <- paddr psize - 1...2 || 0 2 endif byte <- vaddr 1...0 xor bigendiancpu 2 if (vaddr 2 xor bigendiancpu) = 0 then data <- 0 32 || gpr [rt] 31 C 8 * byte...0 || 0 8 * byte else data <- gpr [rt] 31 C 8 * byte || 0 8 * byte || 0 32 endif storememory (uncached, word-byte, data, paddr, vaddr, data) 64 t: vaddr <- ((offset 15 ) 48 || offset 15...0 ) + gpr [base] (paddr, uncached) <- addresstranslation (vaddr, data) paddr <- paddr psize - 1...3 || (paddr 2...0 xor reverseendian 3 ) if bigendianmem = 1 then paddr <- paddr psize - 1...2 || 0 2 endif byte <- vaddr 1...0 xor bigendiancpu 2 if (vaddr 2 xor bigendiancpu) = 0 then data <- 0 32 || gpr [rt] 31 C 8 * byte...0 || 0 8 * byte else data <- gpr [rt] 31 C 8 * byte || 0 8 * byte || 0 32 endif storememory (uncached, word-byte, data, paddr, vaddr, data) chapter 27 cpu instruction set details 653 swr store word right swr (continued) given a doubleword in a register and a doubleword in memory, the operation of swr is as follows: b c d e f g a h j k l m n o i p register memory swr vaddr 2..0 bigendiancpu = 0 destination type offset (lem) 0 1 2 3 4 5 6 7 ijklefgh ijklfghp ijklghop ijklhnop efghmnop fghlmnop ghk lmnop hjklmnop 3 2 1 0 3 2 1 0 0 1 2 3 4 5 6 7 lem little-endian memory (bigendianmem = 0) type accesstype (see table 3-2) sent to memory offset paddr 2...0 sent to memory exceptions: tlb refill exception tlb invalid exception tlb modification exception bus error exception address error exception chapter 27 cpu instruction set details 654 sync synchronize sync special 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 6 5 0 620 sync 0 0 1 1 1 1 6 format: sync description: the sync instruction is executed as a nop on the v r 4102. this operation maintains compatibility with code compiled for the v r 4000 and v r 4400. operation: 32, 64 t: syncoperation ( ) exceptions: none chapter 27 cpu instruction set details 655 syscall system call syscall special 0 0 0 0 0 0 code 31 26 25 6 5 0 620 syscall 0 0 1 1 0 0 6 format: syscall description: a system call exception occurs, immediately and unconditionally transferring control to the exception handler. the code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. operation: 32, 64 t: systemcallexception exceptions: system call exception chapter 27 cpu instruction set details 656 teq trap if equal teq rs special 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 655 10 teq 1 1 0 1 0 0 6 65 format: teq rs, rt description: the contents of general register rt are compared to general register rs . if the contents of general register rs are equal to the contents of general register rt , a trap exception occurs. the code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. operation: 32, 64 t: if gpr [rs] = gpr [rt] then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 657 teqi trap if equal immediate teqi rs regimm 0 0 0 0 0 1 teqi 0 1 1 0 0 immediate 31 26 25 21 20 16 15 0 655 16 format: teqi rs, immediate description: the 16-bit immediate is sign-extended and compared to the contents of general register rs . if the contents of general register rs are equal to the sign-extended immediate , a trap exception occurs. operation: 32 t: if gpr [rs] = (immediate 15 ) 16 || immediate 15...0 then trapexception endif 64 t: if gpr [rs] = (immediate 15 ) 48 || immediate 15...0 then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 658 tge trap if greater than or equal tge rs special 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 655 10 tge 1 1 0 0 0 0 6 65 format: tge rs, rt description: the contents of general register rt are compared to the contents of general register rs . considering both quantities as signed integers, if the contents of general register rs are greater than or equal to the contents of general register rt , a trap exception occurs. the code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. operation: 32, 64 t: if gpr [rs] > gpr [rt] then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 659 tgei trap if greater than or equal immediate tgei rs regimm 0 0 0 0 0 1 tgei 0 1 0 0 0 immediate 31 26 25 21 20 16 15 0 655 16 format: tgei rs, immediate description: the 16-bit immediate is sign-extended and compared to the contents of general register rs . considering both quantities as signed integers, if the contents of general register rs are greater than or equal to the sign-extended immediate , a trap exception occurs. operation: 32 t: if gpr [rs] > (immediate 15 ) 16 || immediate 15...0 then trapexception endif 64 t: if gpr [rs] > (immediate 15 ) 48 || immediate 15...0 then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 660 tgeiu trap if greater than or equal immediate unsigned tgeiu rs regimm 0 0 0 0 0 1 tgeiu 0 1 0 0 1 immediate 31 26 25 21 20 16 15 0 655 16 format: tgeiu rs, immediate description: the 16-bit immediate is sign-extended and compared to the contents of general register rs . considering both quantities as unsigned integers, if the contents of general register rs are greater than or equal to the sign- extended immediate , a trap exception occurs. operation: 32 t: if (0 || gpr [rs]) > (0 || (immediate 15 ) 16 || immediate 15...0 ) then trapexception endif 64 t: if (0 || gpr [rs]) > (0 || (immediate 15 ) 48 || immediate 15...0 ) then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 661 tgeu trap if greater than or equal unsigned tgeu rs special 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 655 10 tgeu 1 1 0 0 0 1 6 65 format: tgeu rs, rt description: the contents of general register rt are compared to the contents of general register rs . considering both quantities as unsigned integers, if the contents of general register rs are greater than or equal to the contents of general register rt , a trap exception occurs. the code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. operation: 32, 64 t: if (0 || gpr [rs]) > (0 || gpr [rt]) then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 662 tlbp probe tlb for matching entry tlbp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cop0 0 1 0 0 0 0 tlbp 0 0 1 0 0 0 31 26 25 6 5 0 6196 co 1 1 24 format: tlbp description: the index register is loaded with the address of the tlb entry whose contents match the contents of the entryhi register. if no tlb entry matches, the high-order bit of the index register is set. the architecture does not specify the operation of memory references associated with the instruction immediately after a tlbp instruction, nor is the operation specified if more than one tlb entry matches. operation: 32 t: index <- 1 || 0 25 || undefined 6 for i in 0...tlbentries - 1 if (tlb [i] 95...77 = entryhi 31...13 ) and (tlb [i] 76 or (tlb [i] 71...64 = entryhi 7...0 )) then index <- 0 26 || i 5...0 endif endfor 64 t: index <- 1 || 0 25 || undefined 6 for i in 0...tlbentries - 1 if (tlb [i] 167...141 and not (0 15 || tlb [i] 216...205 )) = (entryhi 39...13 ) and not (0 15 || tlb [i] 216...205 )) and (tlb [i] 140 or (tlb [i] 135...128 = entryhi 7...0 )) then index <- 0 26 || i 5...0 endif endfor exceptions: coprocessor unusable exception chapter 27 cpu instruction set details 663 tlbr read indexed tlb entry tlbr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cop0 0 1 0 0 0 0 tlbr 0 0 0 0 0 1 31 26 25 6 5 0 6196 co 1 1 24 format: tlbr description: the g bit (which controls asid matching) read from the tlb is written into both of the entrylo0 and entrylo1 registers. the entryhi and entrylo registers are loaded with the contents of the tlb entry pointed at by the contents of the tlb index register. the operation is invalid (and the results are unspecified) if the contents of the tlb index register are greater than the number of tlb entries in the processor. operation: 32 t: pagemask <- tlb [index 5...0 ] 127...96 entryhi <- tlb [index 5...0 ] 95...64 and not tlb [index 5...0 ] 127...96 entrylo1 <- tlb [index 5...0 ] 63...33 || tlb [index 5...0 ] 76 entrylo0 <- tlb [index 5...0 ] 31...1 || tlb [index 5...0 ] 76 64 t: pagemask <- tlb [index 5...0 ] 255...192 entryhi <- tlb [index 5...0 ] 191...128 and not tlb [index 5...0 ] 255...192 entrylo1 <- tlb [index 5...0 ] 127...65 || tlb [index 5...0 ] 140 entrylo0 <- tlb [index 5...0 ] 63...1 || tlb [index 5...0 ] 140 exceptions: coprocessor unusable exception chapter 27 cpu instruction set details 664 tlbwi write indexed tlb entry tlbwi 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cop0 0 1 0 0 0 0 tlbwi 0 0 0 0 1 0 31 26 25 6 5 0 6196 co 1 1 24 format: tlbwi description: the tlb entry pointed at by the contents of the tlb index register is loaded with the contents of the entryhi and entrylo registers. the g bit of the tlb is written with the logical and of the g bits in the entrylo0 and entrylo1 registers. the operation is invalid (and the results are unspecified) if the contents of the tlb index register are greater than the number of tlb entries in the processor. operation: 32, 64 t: tlb [index 5...0 ] <- pagemask || (entryhi and not pagemask) || entrylo1 || entrylo0 exceptions: coprocessor unusable exception chapter 27 cpu instruction set details 665 tlbwr write random tlb entry tlbwr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cop0 0 1 0 0 0 0 tlbwr 0 0 0 1 1 0 31 26 25 6 5 0 6196 co 1 1 24 format: tlbwr description: the tlb entry pointed at by the contents of the tlb random register is loaded with the contents of the entryhi and entrylo registers. the g bit of the tlb is written with the logical and of the g bits in the entrylo0 and entrylo1 registers. operation: 32, 64 t: tlb [random 5...0 ] <- pagemask || (entryhi and not pagemask) || entrylo1 || entrylo0 exceptions: coprocessor unusable exception chapter 27 cpu instruction set details 666 tlt trap if less than tlt rs special 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 655 10 tlt 1 1 0 0 1 0 6 65 format: tlt rs, rt description: the contents of general register rt are compared to general register rs . considering both quantities as signed integers, if the contents of general register rs are less than the contents of general register rt , a trap exception occurs. the code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. operation: 32, 64 t: if gpr [rs] < gpr [rt] then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 667 tlti trap if less than immediate tlti rs regimm 0 0 0 0 0 1 tlti 0 1 0 1 0 immediate 31 26 25 21 20 16 15 0 655 16 format: tlti rs, immediate description: the 16-bit immediate is sign-extended and compared to the contents of general register rs . considering both quantities as signed integers, if the contents of general register rs are less than the sign-extended immediate , a trap exception occurs. operation: 32 t: if gpr [rs] < (immediate 15 ) 16 || immediate 15...0 then trapexception endif 64 t: if gpr [rs] < (immediate 15 ) 48 || immediate 15...0 then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 668 tltiu trap if less than immediate unsigned tltiu rs regimm 0 0 0 0 0 1 tltiu 0 1 0 1 1 immediate 31 26 25 21 20 16 15 0 655 16 format: tltiu rs, immediate description: the 16-bit immediate is sign-extended and compared to the contents of general register rs . considering both quantities as unsigned integers, if the contents of general register rs are less than the sign-extended immediate , a trap exception occurs. operation: 32 t: if (0 || gpr [rs]) < (0 || (immediate 15 ) 16 || immediate 15...0 ) then trapexception endif 64 t: if (0 || gpr [rs]) < (0 || (immediate 15 ) 48 || immediate 15...0 ) then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 669 tltu trap if less than unsigned tltu rs special 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 655 10 tltu 1 1 0 0 1 1 6 65 format: tltu rs, rt description: the contents of general register rt are compared to general register rs . considering both quantities as unsigned integers, if the contents of general register rs are less than the contents of general register rt , a trap exception occurs. the code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. operation: 32, 64 t: if (0 || gpr [rs]) < (0 || gpr [rt]) then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 670 tne trap if not equal tne rs special 0 0 0 0 0 0 rt code 31 26 25 21 20 16 15 0 655 10 tne 1 1 0 1 1 0 6 65 format: tne rs, rt description: the contents of general register rt are compared to general register rs . if the contents of general register rs are not equal to the contents of general register rt , a trap exception occurs. the code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. operation: 32, 64 t: if gpr [rs] z gpr [rt] then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 671 tnei trap if not equal immediate tnei rs regimm 0 0 0 0 0 1 tnei 0 1 1 1 0 immediate 31 26 25 21 20 16 15 0 655 16 format: tnei rs, immediate description: the 16-bit immediate is sign-extended and compared to the contents of general register rs . if the contents of general register rs are not equal to the sign-extended immediate , a trap exception occurs. operation: 32 t: if gpr [rs] z (immediate 15 ) 16 || immediate 15...0 then trapexception endif 64 t: if gpr [rs] z (immediate 15 ) 48 || immediate 15...0 then trapexception endif exceptions: trap exception chapter 27 cpu instruction set details 672 xor exclusive or xor rs special 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 xor 1 0 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 format: xor rd, rs, rt description: the contents of general register rs are combined with the contents of general register rt in a bit-wise logical exclusive or operation. the result is placed into general register rd. operation: 32, 64 t: gpr [rd] <- gpr [rs] xor gpr [rt] exceptions: none chapter 27 cpu instruction set details 673 xori exclusive or immediate xori rs xori 0 0 1 1 1 0 rt immediate 31 26 25 21 20 16 15 0 655 16 format: xori rt, rs, immediate description: the 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical exclusive or operation. the result is placed into general register rt. operation: 32 t: gpr [rt] <- gpr [rs] xor (0 16 || immediate) 64 t: gpr [rt] <- gpr [rs] xor (0 48 || immediate) exceptions: none chapter 27 cpu instruction set details 674 27.6 cpu instruction opcode bit encoding the remainder of this chapter presents the opcode bit encoding for the cpu instruction set (isa and extensions), as implemented by the v r 4102. figure 27-2 lists the v r 4102 opcode bit encoding. figure 27-1. v r 4102 opcode bit encoding (1/2) 28...26 opcode 31...29 01234567 0 special regimm j jal beq bne blez bgtz 1 addi addiu slti sltiu andi ori xori lui 2cop0 ss * beql bnel blezl bgtzl 3 daddi h daddiu h ldl h ldr h **** 4 lb lh lwl lw lbu lhu lwr lwu h 5 sb sh swl sw sdl h sdr h swr cache g 6* ss ** ss ld h 7* ss ** ss sd h 2...0 special function 5...3 01234567 0 sll * srl sra sllv * srlv srav 1 jr jalr * * syscall break * sync 2 mfhi mthi mflo mtlo dsllv h *dsrlv h dsrav h 3 mult multu div divu dmult h dmultu h ddiv h ddivu h 4 add addu sub subu and or xor nor 5 madd16 dmadd16 slt sltu dadd h daddu h dsub h dsubu h 6 tge tgeu tlt tltu teq * tne * 7 dsll h * dsrl h dsra h dsll32 h * dsrl32 h dsra32 h 18...16 regimm rt 20...19 01234567 0bltzbgezbltzlbgezl**** 1 tgei tgeiu tlti tltiu teqi * tnei * 2bltzalbgezalbltzallbgezall**** 3******** chapter 27 cpu instruction set details 675 figure 27-1. v r 4102 opcode bit encoding (2/2) 23...21 cop0 rs 25, 2401234567 0mfdmf hj j mt dmt hj j 1bc jjjjjjj 2 3 co 18...16 cop0 rt 20...19 01234567 0 bcf bct bcfl bctl jjjj 1 jjjjjjjj 2 jjjjjjjj 3 jjjjjjjj 2...0 cp0 function 5...3 01234567 0 i tlbr tlbwi iii tlbwr i 1tlbp iiiiiii 2 [iiiiiii 3eret fiiiiiii 4 i standb suspend hibernate iiii 5 iiiiiiii 6 iiiiiiii 7 iiiiiiii key: * operation codes marked with an asterisk cause reserved instruction exceptions in all current implementations and are reserved for future versions of the architecture. j operation codes marked with a gamma cause a reserved instruction exception. they are reserved for future versions of the architecture. g operation codes marked with a delta are valid only for v r 4102 processors with cp0 enabled, and cause a reserved instruction exception on other processors. i operation codes marked with a phi are invalid but do not cause reserved instruction exceptions in v r 4102 implementations. [ operation codes marked with a xi cause a reserved instruction exception on v r 4102 processor. f operation codes marked with a chi are valid on r4x00 and v r 4102 only. h operation codes marked with epsilon are valid when the processor operating as a 64-bit processor. these instructions will cause a reserved instruction exception if 64-bit operation is not enabled. s operation codes marked with a pi are invalid and cause coprocessor unusable exception. 676 [memo] 677 chapter 28 v r 4102 coprocessor 0 hazards the v r 4100 cpu core avoids contention of its internal resources by causing a pipeline interlock in such cases as when the contents of the destination register of an instruction are used as a source in the succeeding instruction. therefore, instructions such as nop must not be inserted between instructions. however, interlocks do not occur on the operations related to the cp0 registers and the tlb. therefore, contention of internal resources should be considered when composing a program which manipulates the cp0 registers or the tlb. the cp0 hazards define the number of nop instructions which is required to avoid contention of internal resources, or the number of instructions unrelated to contention. this chapter describes the cp0 hazards of the v r 4100 cpu core. the cp0 hazards of the v r 4100 cpu core are equally or less stringent than those of the v r 4000; table 28-1 lists the coprocessor 0 hazards of the v r 4100 cpu core. code which complies with these hazards will run without modification on the v r 4000. the contents of the cp0 registers or the bits in the source column of this table can be used as a source after they are fixed. the contents of the cp0 registers or the bits in the destination column of this table can be available as a destination after they are stored. based on this table, the number of nop instructions required between instructions related to the tlb is computed by the following formula, and so is the number of instructions unrelated to contention: (destination hazard number of a) - [(source hazard number of b) + 1] as an example, to compute the number of instructions required between an mtc0 and a subsequent mfc0 instruction, this is: (5) - (3 + 1) = 1 instruction the cp0 hazards do not generate interlocks of pipeline. therefore, the required number of instruction must be controlled by program. chapter 28 v r 4102 coprocessor 0 haz ards 678 table 28-1. v r 4102 coprocessor 0 hazards source destination instruction or event cp0 data used, stage used no. of cycles cp0 data written, stage available no. of cycles mtc0 cpr [rd] 5 mfc0 cpr [rd] 3 tlbr index, tlb 2 pagemask, entryhi, entrylo0, entrylo1 5 tlbwi tlbwr index or random, pagemask, entryhi, entrylo0, entrylo1 2tlb 5 tlbp pagemask, entryhi 2 index 6 eret epc or errorepc, tlb 2 status [exl, erl] 4 status 2 cache index load tag taglo, taghi, perr 5 cache index store tag taglo, taghi, perr 3 cache hit ops. cache line 3 cache line 5 load/store entryhi [asid], status [ksu, exl, erl, re], config [k0c], tlb 3 config [ad, ep] 3 watchhi, watchlo 3 load/store exception epc, status, cause, badvaddr, context, xcontext 5 instruction fetch epc, status 4 exception cause, badvaddr, context, xcontext 5 instruction fetch entryhi [asid], status [ksu, exl, erl, re], config [k0c] 2 tlb 2 coproc. usable test status [cu, ksu, exl, erl] 2 interrupt signals sampled cause [ip], status [im, ie, exl, erl] 2 tlb shutdown status [ts] 2 (inst.), 4 (data) chapter 28 v r 4102 coprocessor 0 haz ards 679 cautions 1. if the setting of the k0 bit in the config register is changed to uncached mode by mtc0, the accessed memory area is switched to the uncached one at the instruction fetch of the third instruction after mtc0. 2. a stall of several instructions occurs if a jump or branch instruction is executed immediately after the setting of the its bit in the status register. remarks 1. the instruction following mtc0 must not be mfc0. 2. the five instructions following mtc0 to status register that changes ksu and sets exl and erl may be executed in the new mode, and not kernel mode. this can be avoided by setting exl first, leaving ksu set to kernel, and later changing ksu. 3. there must be two non-load, non-cache instructions between a store and a cache instruction directed to the same primary cache line as the store. the status during execution of the following instruction for which cp0 hazards must be considered is described below. (1) mtc0 destination: the completion of writing to a destination register (cp0) of mtc0. (2) mfc0 source: the confirmation of a source register (cp0) of mfc0. (3) tlbr source: the confirmation of the status of tlb and the index register before the execution of tlbr. destination: the completion of writing to a destination register (cp0) of tlbr. (4) tlbwi, tlbwr source: the confirmation of a source register of these instructions and registers used to specify a tlb entry. destination: the completion of writing to tlb by these instructions. (5) tlbp source: the confirmation of the pagemask register and the entryhi register before the execution of tlbp. destination: the completion of writing the result of execution of tlbp to the index register. (6) eret source: the confirmation of registers containing information necessary for executing eret. destination: the completion of the processor state transition by the execution of eret. (7) cache index load tag destination: the completion of writing the results of execution of this instruction to the related registers. chapter 28 v r 4102 coprocessor 0 haz ards 680 (8) cache index store tag source: the confirmation of registers containing information necessary for executing this instruction. (9) coprocessor usable test source: the confirmation of modes set by the bits of the cp0 registers in the source column. examples 1. when accessing the cp0 registers in user mode after the content of the cu0 bit of the status register is modified, or when executing an instruction such as tlb instructions, cache instructions, or branch instructions which use the resource of the cp0. 2. when accessing the cp0 registers in the operating mode set in the status register after the ksu, exl, and erl bits of the status register are modified. (10) instruction fetch source: the confirmation of the operating mode and tlb necessary for instruction fetch. examples 1. when changing the operating mode from user to kernel and fetching instructions after the ksu, exl, and erl bits of the status register are modified. 2. when fetching instructions using the modified tlb entry after tlb modification. (11) instruction fetch exception destination: the completion of writing to registers containing information related to the exception when an exception occurs on instruction fetch. (12) interrupts source: the confirmation of registers judging the condition of occurrence of interrupt when an interrupt factor is detected. (13) loads/sores source: the confirmation of the operating mode related to the address generation of load/store instructions, tlb entries, the cache mode set in the k0 bit of the config register, and the registers setting the condition of occurrence of a watch exception. example when loads/stores are executed in the kernel field after changing the mode from user to kernel. (14) load/store exception destination: the completion of writing to registers containing information related to the exception when an exception occurs on load or store operation. (15) tlb shutdown destination: the completion of writing to the ts bit of the status register when a tlb shutdown occurs. chapter 28 v r 4102 coprocessor 0 haz ards 681 table 28-2 indicates examples of calculation. table 28-2. calculation example of cp0 hazard and the number of instructions inserted destination source contending internal resource number of instructions inserted formula tlbwr/tlbwi tlbp tlb entry 2 5 - (2 + 1) tlbwr/tlbwi load or store using newly modified tlb tlb entry 1 5 - (3 + 1) tlbwr/tlbwi instruction fetch using newly modified tlb tlb entry 2 5 - (2 + 1) mtc0, status [cu] coprocessor instruction which requires the setting of cu status [cu] 2 5 - (2 + 1) tlbr mfc0 entryhi entryhi 1 5 - (3 + 1) mtc0 entrylo0 tlbwr/tlbwi entrylo0 2 5 - (2 + 1) tlbp mfc0 index index 2 6 - (3 + 1) mtc0 entryhi tlbp entryhi 2 5 - (2 + 1) mtc0 epc eret epc 2 5 - (2 + 1) mtc0 status eret status 2 5 - (2 + 1) mtc0 status [ie] note instruction which causes an interrupt status [ie] 2 5 - (2 + 1) note the number of hazards is undefined if the instruction execution sequence is changed by exceptions. in such a case, the minimum number of hazards until the ie bit value is confirmed may be the same as the maximum number of hazards until an interrupt request occurs which is pending and enabled. 682 [memo] 683 chapter 29 pll passive components the phase locked loop circuit requires several passive components for proper operation, which are connected to v dd p and gndp as illustrated in figure 29-1. figure 29-1. example of connection of pll passive components v dd v dd p gndp gnd v r 4102 r c1 c2 c3 r remarks1. c1, c2, c3 capacitors and r resistors are mounted on the printed circuit board. 2. since the value for the components depends upon the application system, the optimum values for each system should be decided after repeated experimentation. it is essential to isolate the analog power and ground for the pll circuit (v dd p/gndp) from the regular power and ground (v dd /gnd). initial evaluations have yielded good results with the following values: r = 5 : c1 = 1 nf c2 = 2 nf c3 = 10 p f since the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further experimentation within your specific application. in addition, the chokes (inductors: l ) can be considered for use as an alternative to the resistors ( r ) for use in filtering the power supply. 684 [memo] 685 appendix a differences between v r 4102 and v r 4101 a.1 summary of differences item v r 4102 v r 4101 cache size instruction: 4 kbytes, data: 1 kbyte instruction: 2 kbytes, data: 1 kbyte isa bus sizing 16-/8-bit dynamic bus sizing select 16-/8-bit bus with address spaces interface bus hold available not available i/o space 64 mbytes 4 mbytes memory space 64 mbytes 4 mbytes lcd memory space switches between lcd mode and high-speed memory mode supports only lcd mode max. dram capacity (edo type) 32 mbytes 8 mbytes max. rom capacity 32 mbytes 16 mbytes dram type 16 mbits, 64 mbits 16 mbits memory controller rom type 32 mbits, 64 mbits 16 mbits, 32 mbits power-on factor 4 factors 3 factors dma controller connected to aiu and fir uses a dma space for each page connected to aiu, piu, kiu, and siu uses a dma space linearly timer, counter 4 channels: 24 bits x 2 (32.768 khz) 48 bits x 1 (32.768 khz) 25 bits x 1 (for performance test, tclock) 3 channels: 24 bits x 1 (32.768 khz) 48 bits x 1 (32.768 khz) 31 bits x 1 (for performance test, tclock) keyboard interface supports 64/80/96 keys supports up to 64 keys audio interface supports pcm input/output on-chip d/a converter supports pwm/buzz output touch panel interface on-chip 10-bit a/d converter on-chip touch panel controller external 10/12-bit a/d converter external touch panel controller serial interface ns16650 compatible x 1 (max. data rate: 1.152 mbps) nec original x 1 (max. data rate: 115.2 kbps max.) nec original x 2 (max. data rate: 115.2 kbps) ports for led lighting available not available modem interface on-chip interface supporting software modem (equivalent to pct288i) not available irda interface fir (max. data rate: 4 mbps) sir (max. data rate: 115.2 kbps) general-purpose i/o ports 49 max. (including alternate-function pins) 12 max. clock input 32.768 khz (input to cg), 18.432 mhz (input to cg), 48 mhz (directly connected to on-chip irda interface) 32.768 khz (input to cg) package 216 pin lqfp, 224-pin fbga 160 pin lqfp appendix a differences between v r 4102 and v r 4101 686 a.2 details of differences a.2.1 cpu core (1) cache size the instruction cache of the v r 4102 is 4k bytes in size, on the other hand, that of the v r 4101 is 2k bytes. the size of the data cache of the v r 4102 is 1k bytes which is the same as that of the v r 4101. to specify cache data address used for cache instruction, the v r 4102 uses bit 31..12 of the taglo register, in contrast to the v r 4101 which uses bit 31..11. for data cache, both the v r 4102 and the v r 4101 use bit 13..10 of the taglo register. (2) settings of the config register bit 12 of the config register (cs) indicates cache size mode, bit 11..9 (ic) indicates instruction cache size, and bit 8..5 (dc) indicates data cache size. in the v r 4102, cs is set to 1 (cache of small capacity), ic to 010 (4k bytes), and dc to 000 (1k bytes). in the v r 4101, bit 12..5 of the config register are not defined and fix to 0 as a reserved field. bit 27..24 of the config register (ep) indicates transfer data pattern in the cache writeback. this field must be set to 0000 (dd) in the v r 4102, on the other hand, it must be set to 0011 (dxdx) in the v r 4101. a.2.2 address mapping (1) memory area in the v r 4102, 16m and 64m bits are selectable for dram space size, though only a 16m-bit dram can be connected to the v r 4101. similarly, 32m and 64m bits are selectable for rom space size in the v r 4102, though only a 32m-bit rom can be connected to the v r 4101. (2) lcd space the lcd space is mapped to 16m-byte area of 0x0a00 0000 through 0x0aff ffff in both the v r 4102 and the v r 4101. however, the v r 4102 can also use this area as the high speed memory space, and the switching is set in one of the bcu registers. (3) isa spaces the isa memory and i/o spaces have a size of 64m bytes respectively in the v r 4102. those in the v r 4101 have 4m bytes in total (2m bytes for 8-bit bus, 2m bytes for 16-bit bus). in addition, the v r 4102 supports 16/8-bit dynamic sizing for the isa bus. (4) internal i/o space the internal i/o space is expanded to 32m bytes in the v r 4102 compared to that of the v r 4101 which has a size of 16m bytes. appendix a differences between v r 4102 and v r 4101 687 a.2.3 bcu (1) setting of bcu transaction in the v r 4101, the intervals of bus transactions and the number of repetitions in the enabled bcu transaction intervals can be selectable. this function is deleted in the v r 4102. (2) memory access control 16 and 32 bits are selectable as the data bus width with dbus32 pin at reset in the v r 4102 except for isa memory area, on the other hand, the bus width is fixed to 16 bits in the v r 4101. though both the v r 4102 and the v r 4101 can select three memory types which are dram, masked rom, and flash memory, their memory sizes and mapping method are different as summarized below. memory type v r 4102 v r 4101 dram 16m-bit/64m-bit edo x 16 bits (access time: 60 ns) 16m-bit edo x 16 bits (access time: 60 ns) masked rom 32m-bit/64m-bit ordinary or page type x 16 bits 16-bit bus mode: selected as banks0/1 or 2/3 32-bit bus mode: selected as bank0 or 1 32m-bit ordinary or page type x 16 bits the whole rom space is selected flash memory 16-bit bus mode: selected as banks0/1 or 2/3 32-bit bus mode: selected as bank0 or 1 to use the whole rom space can be selected (3) lcd space the lcd space is used only for lcd access in the v r 4101, while it can be used for either lcd access or high- speed memory access in the v r 4102. which of lcd or high-speed memory the lcd space is used for is selected in bcucnt1reg register. when high-speed memory is selected, lcdcs# pin becomes active. the access time for lcd is selectable among 2, 4, 6, and 8 tclock cycles in both the v r 4102 and the v r 4101. for high-speed memory in the v r 4102, the access time is selectable among 1, 2, 3, 4, 5, 6, 7, and 8 tclock cycles. these selections of access time are set in bcuspeedreg register. when transferring lcd data, inverting the data values or not is selectable in the v r 4102 and is set in bcucnt2reg register. on the other hand, the v r 4101 always inverts the values at lcd data transfer. (4) isa space in the v r 4102, the bus size is dynamically controlled at every bus cycle with iocs# and memcs# pins. in the v r 4101, the bus size is fixed to 8 or 16 bits and is distinguished by the accessed address space. (5) others the v r 4102 has bus hold function and can make isa, lcd, and memory interfaces into bus hold state. the v r 4101 has no bus hold function, and therefore the cpu is always master state. bit 11..8 and bit 3..0 of previdreg register indicate the revision number of the on-chip peripheral units in both the v r 4102 and the v r 4101. in addition, bit 15..12 indicates the processor revision number in the v r 4102, though it is fixed to 0 in the v r 4101. the remaining bits, bit 7..4, are fixed to 0 in both processors. appendix a differences between v r 4102 and v r 4101 688 a.2.4 dma (1) sources of dma the v r 4102 uses dma transfer for aiu reception, aiu transmission, and fir transmission/reception (in priority order). on the other hand, the v r 4101 uses dma transfer for aiu, piu, siu reception, siu transmission, and kiu (in priority order). (2) dma operation the v r 4102 reloads the dma base address every time the dma transfer reaches page boundary. the v r 4101 uses dma address space linearly which starts at dma base address. for more details about dma address manipulation, see chapter 11. a.2.5 icu (1) sources of interrupts compared with the v r 4101, five interrupt sources, hsp, led, fir, rtc long timer 2, and tclock counter, are newly added in the v r 4102 icu. three more software interrupts which are caused by setting the softintreg register are also added. the number of interrupt factors are changed in eight interrupt sources which are siu, dsiu, giu, kiu, aiu, piu, kiu in suspend mode, and piu in suspend mode. (2) notification to the cpu core in the v r 4102, nmi and int[3..0] signals are used to notify interrupt requests to the cpu core, in contrast to the v r 4101 which uses nmi and int[1..0] signals. a.2.6 pmu (1) power-on function compared with the v r 4101, gpio[3..0] and gpio[12..9] inputs are added in the v r 4102 as a cpu activation factor. especially, gpio[3] can be used without any settings immediately after rtcrst. (2) battlock and cardlock notifications no dedicated pins for battlock and cardlock functions are assigned in the v r 4102. they must be assigned to either of gpio[12..9] pins and they are manipulated as two of giu interrupts. a.2.7 rtc (1) rtc long timers the v r 4102 has two rtc long timers, on the other hand the v r 4101 has only one. (2) tclock counter tclock counter of the v r 4102 is 25-bit long which is 6 bits shorter than that of the v r 4101. tclock counter of the v r 4102 is added as one of the interrupt factors, and an interrupt request occurs when its value becomes 1. in the v r 4101, no interrupt request is caused by tclock counter. appendix a differences between v r 4102 and v r 4101 689 a.2.8 giu (1) gpio pins the v r 4102 has 49 general-purpose i/o pins and 33 of them have alternate functions, while the v r 4101 has 12 general i/o pins and none of them have alternate functions. gpio[15] pin of the v r 4102 is assigned as dcd# input which has dedicated pin in the v r 4101. in both the v r 4102 and the v r 4101, giu controls dcd# input as well as gpio pins. gpio pins are also used as interrupt request inputs except for gpio[49..32] of the v r 4102, and in which power modes an interrupt request is enabled is different from each gpio pin. the functions of gpio pins are as summarized below. enabled power mode pins i/o interrupt input v r 4102 v r 4101 alternative functions in v r 4102 notes gpio[49] o n/a standby - - gpio[48] i/o n/a standby - dbus32 gpio[47..44] i/o n/a standby - dsiu pins gpio[43..32] o n/a standby - kscan[11..0] gpio[31..16] i/o a standby - data[31..16] gpio[15] i a hibernate - dcd# 1 gpio[14] i/o a suspend - - gpio[13] i/o a suspend hibernate - 2 gpio[12] i/o a suspend - - gpio[11] i/o a suspend standby - gpio[10..9] i/o a suspend suspend - gpio[8..4] i/o a standby standby - gpio[3..0] i/o a hibernate standby - notes 1. this pin is assigned as dcd# input in the v r 4102. 2. this pin does not exist in the v r 4101. dcd input is internally connected to the corresponding register bits for gpio[13] in giu and the v r 4101 manipulates those bits as input only. (2) interrupt input control in both the v r 4102 and the v r 4101, either edge, high level, or low level of the input signal is selectable as an interrupt input trigger. in the v r 4102, whether interrupt requests are held in giu or not is selectable, while they are not held in the v r 4101. appendix a differences between v r 4102 and v r 4101 690 a.2.9 piu piu of the v r 4102 is greatly changed from that of the v r 4101 as summarized below. item v r 4102 v r 4101 a/d converter on-chip (10 bits) external (10/12 bits) data transfer transfer to buffer in piu dma transfer data buffers four buffers (two pages each) for coordinate data only four buffers for a/d scan one buffer scan types coordinate data scan command scan a/d scan coordinate data scan command scan main battery scan sub battery scan a/d port scan activation states standby, waitpen touch, interval standby panel applied voltage stabilization standby time counter 6 bits 4 bits panel applied voltage during low- voltage mode all four touch panel pins are at low level all four touch panel pins are at hi-z panel state during disable state touch detection state (interrupts do not occur when cpu is in hibernate mode.) all four touch panel pins are at hi-z handling of valid data when data loss occurs valid data is always retained valid data is overwritten data interrupt three types of special-purpose interrupts (two coordinate data interrupts, a/d scan interrupt, and command scan interrupt) two types of page boundary interrupts piudatardyintr no yes appendix a differences between v r 4102 and v r 4101 691 a.2.10 aiu (1) audio output mode the pcm output is employed in the v r 4102 as an audio output mode. in the v r 4101, buzzer or pwm output is selectable. (2) audio input mode the v r 4102 has an analog audio input which is connected to the on-chip a/d converter. the v r 4101 does not support any audio inputs. (3) audio data transfer the v r 4102 uses dma transfer to prepare pcm data in the output operation and to store sampled data in the input operation. in the v r 4101, output frequency and period for the buzz mode are set in the aiu registers, or output high level and low level width for the pwm mode are prepared with dma transfer. (4) volume control volume of the audio outputs is controlled by an external circuit or by shifting data input to d/a converter in the v r 4102. in the v r 4101, four steps of audio output volume can be set in the aiumutereg register and are controlled by an external circuit based on the settings in the register. a.2.11 kiu (1) number of keys supported in the v r 4102, the number of scan lines used is selectable among 8, 10, and 12 by setting the scanline register, which determines the number of keys enabled to either of 64, 80, or 96. the v r 4102 can detect when any of enabled keys are pressed using selected scan lines and 8 detection lines. the v r 4101 can detect when any of 64 keys are pressed using 8 scan lines and 8 detection lines. when the v r 4102 uses only 8 or 10 scan lines, the unused scan lines can be used as general-purpose output ports. when the kiu is disabled in the v r 4102, all the scan lines (kscan[11..0] pins) can be used as general- purpose outputs (gpio[43..32]). (2) lcd brightness control the v r 4101 has lcd brightness control pins which are alternately used as kcsan[1..0] pins and indicate the contents of evvolreg register to specify brightness. the v r 4102 has no pins for lcd brightness control. (3) kiu data transfer the v r 4102 transfers kiu data by reading data buffers when an interrupt occurs, while the v r 4101 transfers with dma. appendix a differences between v r 4102 and v r 4101 692 a.2.12 dsiu (1) hardware flow control the v r 4102 has two pins for hardware flow control, dcts# and drts#, while the v r 4101 has no pins for it. (2) supported interrupts the v r 4102 dsiu supports receive error interrupt, receive completion interrupt, transmit completion interrupt, and cts interrupt. the v r 4101 dsiu supports receive error interrupt, receive completion interrupt, and transmit completion interrupt. (3) alternative functions of dsiu pins the v r 4102 dsiu pins can be used as general-purpose output port, gpio[47..44], when dsiu is disabled. those of the v r 4101 have no alternative functions. a.2.13 siu the v r 4102 siu is newly designed and is functionally compatible with ns16550 in contrast to that of the v r 4101 which is originally designed by nec. their differences are as summarized below. item v r 4102 v r 4102 architecture functionally compatible with ns16550 nec original maximum data rate 1.15 mbps 115 kbps ir communication available available data transfer read out of fifo buffers by software dma character length 5, 6, 7, or 8 bits 7 or 8 bits stop bit length 1, 1.5 (for 5 bits), or 2 (for 6, 7, or 8 bits) 1 or 2 parity check checked/generated is selectable checked/not generated (substituted by software) framing error automatically detected automatically detected break transmission available available break detection automatically detected automatically detected receive overrun error automatically detected occurs receive data lost interrupt flow control pins rts#, cts#, dtr#, dsr#, dcd# rts#, cts#, dtr#, dsr#, dcd transmit data flow 16450 mode: from siuth register to transmit shift register fifo mode: from fifo (16 bytes) to transmit shift register from dma (2k bytes) to siutxdatreg receive data flow 16450 mode: from receive shift register to siurb register fifo mode: from receive shift register to fifo (16 bytes) from siurxdatreg to dma (2k bytes) appendix a differences between v r 4102 and v r 4101 693 a.2.14 newly added units the v r 4102 has three newly designed peripheral units as described below which the v r 4101 does not have. (1) led this unit is used to control lighting of an led. this unit features as below: high level width (up to 2 seconds), low level width (up to 8 seconds), and the number of blink can be set supports stop interrupt request enabled during standby, suspend, and hibernate modes (2) hsp this unit is used to realize a software modem with externally connected codec and daa blocks. the hsp unit of the v r 4102 is compatible with pct288i produced by pctel. the assigned functions of software and each block are as below. software: protocol calculation, codec control, error correction, and os interface hsp unit: serial/parallel conversion of 16-bit data, control of status pins, and fifo buffer management codec: d/a, a/d conversion and operation clock supply based on mclk of hsp unit daa: interface for codec data and telephone circuits (3) fir this unit is used for irda communication in high-speed data transfer. supported transfer rates includes 0.576m, 1.152m, and 4m bps. 694 [memo] 695 a a/d converter ... 381, 383, 422 a/d port scan ... 404 access data size ... 247 address error exception ... 180 address translation 119, 120 addressing ... 47 aiu ... 31, 409 aiu registers ... 39, 409 aiuiahreg ... 275 aiuialreg ... 275 aiuibahreg ... 273 aiuibalreg ... 273 aiuintreg ... 298 aiuoahreg ... 278 aiuoalreg ... 278 aiuobahreg ... 276 aiuobalreg ... 276 asim00reg ... 438 asim01reg ... 439 asis0reg ... 444 audio interface unit (aiu) ... 31, 409 b badvaddr register ... 161 baud rates and divisors ... 466 bcu ... 31, 235 bcu registers ... 33, 235 bcucntreg 1 ... 236 bcucntreg 2 ... 238 bcuerrstreg ... 241 bcurfcntreg ... 242 bcurfcountreg ... 244 bcuspeedreg ... 239 bev ... 211 bootstrap exception vector (bev) ... 211 bprm0reg ... 446 branch address 93 branch delay ... 102 branch instruction ... 92, 528 breakpoint exception ... 186 bus control unit (bcu) ... 31, 235 bus error exception ... 185 bus hold ... 268 bus interface 43 bus mode 247 bypassing ... 115 c cache 51 cache data integrity ... 220 cache error check ... 212 cache error exception ... 184 cache error register ... 171 cache instruction 219, 220 cache line ... 214, 218 cache memory 213 cache operations ... 217 cache organization ... 214 cache state transition 219 cache states ... 218 cause register ... 165 clkspeedreg ... 245 clock generator 43 clock interface ... 53 clock mask unit (cmu) ... 31, 289 clock oscillator ... 54 cmu ... 31, 289 cmu register ... 34, 289 cmuclkmsk ... 290 code compatibility 115 cold reset ... 207 cold reset exception ... 177 compare register ... 162 computational instructions ... 86 config register ... 150 connection of address pins ... 246 context register ... 160 coordinate detection ... 382 coprocessor 0 (cp0) ... 44, 49, 141 coprocessor unusable exception ... 187 count register ... 161 cp0 ... 44, 49, 141 cp0 hazards ... 677 cp0 registers ... 49, 50, 141, 146 cpu 43 cpu bus interface 43 cpu core ... 43 cpu instruction ... 46, 81, 525 cpu instruction set ... 46, 81, 525 cpu registers ... 45 crcsr ... 508 crystal oscillation ... 54 appendix b index appendix b index 696 d d/a converter ... 421 data cache ... 44, 215 data cache addressing 216 data formats ... 47, 448 data loss ... 405 dcu ... 31, 281 dcu registers ... 34, 281 deadmans sw shutdown ... 320 deadmans switch ... 202 deadmans switch unit (dsu) ... 31, 355 debug serial interface unit (dsiu) ... 32, 435 defining access types 82 direct memory access (dma) 271, 421, 422, 513, 522 direct memory access address unit (dmaau) ... 31, 271 direct memory access control unit (dcu) ... 31, 281 dma priority levels ... 281 dmaau ... 31, 271 dmaau registers ... 33, 272 dmacr ... 512 dmaer ... 513 dmaidlereg ... 283 dmamskreg ... 285 dmareqreg ... 286 dmarstreg ... 282 dmasenreg ... 284 dpcntr ... 501 dpintr ... 500 dram 140 dram access ... 264 dram space ... 140 dsiu ... 32, 435 dsiu registers ... 40, 435 dsiuintreg ... 301 dsiuresetreg ... 447 dsu ... 31, 355 dsu registers ... 37, 355 dsuclrreg ... 358 dsucntreg ... 356 dsusetreg ... 357 dsutimreg ... 359 dvalidreg ... 418 e ecmphreg ... 340 ecmplreg ... 339 ecmpmreg ... 339 elapsed timer ... 335 endianness ... 47, 48 entryhi register ... 147 entrylo register ... 147 epc register ... 167 errorepc register ... 171 etimehreg ... 338 etimelreg ... 337 etimemreg ... 337 exception ... 109, 173 exception conditions ... 112 exception processing ... 157, 191 exception processing registers ... 159 exception program counter (epc) register ... 167 exception vector locations ... 173 external clock ... 54 f fast irda interface unit (fir) ... 32, 497 fifo interrupt modes ... 470 fifo polling mode ... 471 fir ... 32, 497 fir registers ... 42, 497 firahreg ... 280 firalreg ... 280 firbahreg ... 279 firbalreg ... 279 fircr ... 509 firintreg ... 313 flash memory ... 247 flash memory interface ... 249 frstr 499 fsr ... 505 fullspeed mode ... 210, 326 g general purpose i/o unit (giu) ... 31, 361 giu ... 31, 361 giu registers ... 37, 362 giuintalselh ... 374 giuintalsell ... 373 giuintenh ... 370 giuintenl ... 369 giuinthreg ... 312 giuinthtselh ... 376 giuinthtsell ... 375 giuintlreg ... 300 giuintstath ... 368 giuintstatl ... 367 giuinttyph ... 372 giuinttypl ... 371 giuioselh ... 364 giuiosell ... 363 appendix b index 697 giupiodh ... 366 giupiodl ... 365 giupodath ... 380 giupodatl ... 378 h haltimer shutdown ... 204, 320 hardware interrupts ... 232 hibernate mode ... 211, 327 hierarchy of memory ... 213 hsp ... 32, 481 hsp registers ... 41, 483 hspcntl ... 486 hspdata[15..0] ... 485 hsperrcnt ... 493 hspextin ... 492 hspextout ... 487 hspffsz ... 489 hspid ... 492 hspid[7:0] ... 493 hspindex[15..0] ... 485 hspinit ... 484 hspmclkd ... 488 hsppcs[7:0] ... 493 hsppctel[7:0] ... 493 hsprxdata ... 490 hspsts ... 491 hsptoc ... 488 hsptxdata ... 485 i i/o registers ... 33 icu ... 31, 291 icu registers ... 35, 294 ie bit 212 ifr ... 517 illegal access ... 251 imr ... 504 index register ... 146 initialization interface ... 199 instruction cache ... 43, 214 instruction cache addressing 216 instruction formats ... 46, 81 instruction pipeline 53 integer overflow exception ... 189 interlock ... 109 internal i/o space ... 139 interrupt 231 interrupt control ... 293 interrupt control unit (icu) ... 31, 291 interrupt enable (ie) ... 212 interrupt exception ... 190 interrupt request signal 232 intr0reg ... 445 intreg ... 420 irsr1 ... 507 j joint tlb ... 52 jtlb 52 jump instruction ... 92, 528 k kernel expanded addressing mode ... 211 kernel mode 127 kernel mode address space ... 128 keyboard interface unit (kiu) ... 32, 423 kiu ... 32, 423 kiu registers ... 40, 423 kiu sequencer ... 427, 428 kiudat0 ... 424 kiudat1 ... 424 kiudat2 ... 424 kiudat3 ... 424 kiudat4 ... 424 kiudat5 ... 424 kiugpen ... 433 kiuint ... 431 kiuintreg ... 299 kiurst ... 432 kiuscanrep ... 425 kiuscans ... 427 kiuwki ... 430 kiuwks ... 429 l lcd 140 lcd control interface ... 250 lcd interface ... 263 lcd space ... 140 led ... 32, 453 led control unit (led) ... 32, 453 led registers ... 41, 453 ledastcreg ... 457 ledcntreg ... 456 ledhtsreg ... 454 ledintreg ... 458 ledltsreg ... 455 load delay ... 102 load delay slot ... 82 load instruction ... 82, 527 load linked address (lladdr) register ... 151 appendix b index 698 local loopback ... 473 m maiuintreg ... 305 masterout ... 53 mcntreg ... 416 mcnvrreg ... 417 mdmadatreg ... 410 mdsiuintreg ... 308 memory management system (mmu) ... 52, 117 mfirintreg ... 316 mgiuinthreg ... 315 mgiuintlreg ... 307 midatreg ... 415 mircr ... 511 mkiuintreg ... 306 modem interface unit (hsp) ... 32, 481 modemreg ... 437 mpiuintreg ... 304 mrxf ... 522 msysint1reg ... 302 msysint2reg ... 314 n nmi exception ... 179 nmireg ... 309 non-maskable interrupt (nmi) ... 231 o opcode bit encoding ... 674 operating modes ... 121 operation when unbranched 93 ordinary interrupts ... 231 ordinary rom ... 248 p pagemask register ... 143, 147 pagerom ... 248 parity error prohibit ... 212 parity error register ... 170 pclock ... 53 phase lock loop (pll) 43 physical address ... 135 pin configuration 57 pin functions ... 57, 62 pipeline ... 99 piu ... 32, 381 piu registers ... 38, 386 piuab0reg ... 400 piuab1reg ... 400 piuab2reg ... 400 piuab3reg ... 400 piuamskreg ... 397 piuascnreg ...395 piucivlreg ... 398 piucmdreg ... 393 piucntreg ... 387 piuintreg (icu) ... 297 piuintreg (piu) ... 390 piupb00reg ... 399 piupb01reg ... 399 piupb02reg ... 399 piupb03reg ... 399 piupb04reg ... 399 piupb10reg ... 399 piupb11reg ... 399 piupb12reg ... 399 piupb13reg ... 399 piupb14reg ... 399 piusivlreg ... 391 piustblreg ... 392 pll 43 pll passive components ... 683 pmu ... 31, 319 pmu registers ... 35, 327 pmucnt2reg 333 pmucntreg ... 330 pmuint2reg 332 pmuintreg ... 328 portreg ... 436 power management unit (pmu) ... 31, 319 power mode 210, 325 power mode state transition ... 325 power-on control ... 321 power-on sequence ... 205 precision of exceptions ... 158 priority of exceptions ... 176 privilege mode ... 211 processor revision identifier (prid) register ... 149 r random register ... 146 rdr ... 503 real-time clock unit (rtc) ... 31, 335 refresh ... 267 reserved instruction exception ... 188 reset control ... 319 reset function ... 199 reverse endian ... 211 revidreg ... 243 rom 137 rom access 252 appendix b index 699 rom interface ... 248 rom space ... 137 rstsw ... 201, 319 rtc ... 31, 335 rtc registers ... 36, 336 rtc reset ... 199, 319 rtcintreg ... 353 rtcl1cnthreg ... 344 rtcl1cntlreg ... 343 rtcl1hreg ... 342 rtcl1lreg ... 341 rtcl2cnthreg ... 348 rtcl2cntlreg ... 347 rtcl2hreg ... 346 rtcl2lreg ... 345 rtclong timer ... 335 rxb0lreg ... 441 rxb0rreg ... 440 rxfl ... 523 rxir 515 rxsts ... 519 s scan sequencer ... 383, 425 scanline ... 434 scntreg ... 413 scnvrreg ... 414 sdmadatreg ... 411 seqreg ... 419 serial interface unit (siu) ... 32, 461 shutdown control ... 320 siu ... 32, 461 siu registers ... 41, 461 siudll ... 463 siudlm ... 465 siufc ... 469 siuie ... 464 siuiid ... 467 siuirsel ... 478 siulc ... 472 siuls ... 474 siumc ... 473 siums ... 476 siurb ... 462 siusc ... 477 siuth ... 462 slip conditions ... 114 sodatreg ... 412 soft reset ... 208 soft reset exception ... 178 softintreg ... 370 software interrupts ... 232 software shutdown ... 203, 320 special instructions ... 96 stall conditions ... 113 standby mode ... 210, 326 status after reset 164 status register ... 162 store delay slot ... 82 store instruction ... 82, 527 supervisor expanded addressing mode ... 211 supervisor mode ... 124 supervisor mode address space ... 125 suspend mode ... 210, 326 sysint1reg ... 295 sysint2reg ... 311 system call exception ... 186 system control coprocessor (cp0) ... 44, 49, 141 system control coprocessor (cp0) instructions ... 97, 528 t taghi register ... 152 taglo register ... 152 tclkcnthreg ... 352 tclkcntlreg ... 351 tclkhreg ... 350 tclklreg ... 349 tclock ... 53 tclock counter ... 335 tdr ... 502 tdreg ... 287 timer interrupt ... 232 tlb 52, 117 tlb entry ... 142 tlb exceptions ... 181 tlb instructions ... 155 tlb invalid exception ... 182 tlb misses 155 tlb modified exception ... 183 tlb refill exception ... 181 touch panel ... 381 touch panel interface unit (piu) ... 32, 381 touch/release detection ... 404 translation lookaside buffer (tlb) ... 52, 117 trap exception ... 188 txfl ... 521 txir 514 txs0lreg ... 443 txs0rreg ... 442 appendix b index 700 u user expanded addressing mode ... 211 user mode ... 121 user mode address space ... 122 v virtual address ... 117 virtual-to-physical address translation ... 118 w watch exception ... 189 watchhi register ... 168 watchlo register ... 168 wired register ... 148 x xcontext register ... 169 xtlb refill exception ... 181 although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we?e taken, you may encounter problems in the documentation. please complete this form whenever you? like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6465-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec corporation semiconductor solution engineering division technical information support dept. fax: 044-548-7900 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. 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